ọdịnaya zoo
1 Xilinx DDR2 MIG 7 Ntuziaka Atụmatụ arụmọrụ
2 Okwu mmalite
3 Bandwidth dị Irè
4 MIG Design Ọgbọ
5 Mgbanwe nke Simulation RTL
6 Na-eme ka ndị na-emepụta ihe na-arụ ọrụ okporo ụzọ
7 Ụzọ izugbe iji melite arụmọrụ
8 Oge ebe nchekwa gafere
9 Ọnụ ego njikwa
10 Ntụaka
11 Ntụaka
12 Ozi ndị metụtara

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Xilinx DDR2 MIG 7 Ntuziaka Atụmatụ arụmọrụ

Xilinx_DDR2_MIG_7_Arụmọrụ-atụmatụ-ngwaahịa

Ihe ndetu dị mkpa: A na-enye PDF nke a na-ebudata ndekọ azịza iji kwalite ojiji na ịgụ ya. Ọ dị mkpa ịmara na Ndekọ Azịza bụ WebỌdịnaya dabere na-emelite kwa mgbe ka ozi ọhụrụ na-adị. A na-echetara gị ileta Nkwado nka na ụzụ Xilinx Websaịtị na review (Xilinx Azịza 63234) maka ụdị azịza a kachasị ọhụrụ.

Okwu mmalite

N'ihi otu esi ahazi ebe nchekwa DDR2 na DDR3 yana ezubere njikwa usoro MIG 7, arụmọrụ anaghị aga n'ihu.
Ọ chọrọ nghọta dị iche iche Jedec Timing parameters na njikwa Architecture, na ị ga-mkpa na-eme simulations iji nweta atụmatụ.
Ụkpụrụ izugbe maka ikpebi arụmọrụ bụ otu ma akwụkwọ a na-enye ụzọ dị mfe iji nweta arụmọrụ site na iji MIG ex.ample imewe site n'enyemaka nke ule bench na mkpali files mmasị ebe a.

Bandwidth dị Irè

Ụgbọ ala data DRAM na-enweta bandwidth dị nso naanị n'oge a na-agụ ma na-ede ihe na n'elu ya na-ebelata ọnụego data dị irè.
Ole na ole exampIhe kacha mkpa bụ:

  • Ị nweta ahịrị ndị dị n'otu ụlọ akụ (nweta adreesị ọ bụghị n'otu ahịrị ibe akwụkwọ)
  • dee oge mgbake ka ị gbanwee site na ide gaa na ịnweta ọgụgụ
  • oge ntụgharị ụgbọ ala iji gbanwee site na ịgụ akwụkwọ gaa na ịnweta

Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-28
Bandwit dị irè = Bandwit kacha elu * arụmọrụ 

MIG Design Ọgbọ

Rụtụ aka na UG586 Isi nke 1 maka nkọwa nzọụkwụ site na nzọụkwụ na MIG IP na example imewe ọgbọ.
Tupu ị na-agba simulation arụmọrụ MIG 7, mee ihe ndị a ka ị hụ na gburugburu ịme anwansị gị dị mma. Mepee MIG example chepụta na map ndị kwesịrị ekwesị ọba akwụkwọ, na-agba ọsọ simulation, na hụ na ị nwere ike ịhụ ozi "ule gafere" na transcript.
Iji gosi na ọ na-erugharị m ewepụtala MIG IP maka xc7vx690tffg1761-2 wee kpọọ oku ex.ampimewe.
Ihe abụọ ekwesịrị ịdeba ama bụ ibe n'ibe ebe nchekwa na nhọrọ nke adreesị ebe nchekwa.
Maka exampLe, ahọpụtara m MT41J128M8XX-125 n'okpuru akụkụ ebe nchekwa dobe nhọrọ.Xilinx DDR2 MIG-7-Arụmọrụ-atụmatụ-fig-1

Maka akụkụ ebe nchekwa ahọpụtara site na eserese-1, ahịrị = 14, kọlụm = 10 na ụlọ akụ = 3, yabụ app_addr_width = ahịrị + kọlụm + akụ + ọkwa = 28 Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-2

Ị nwere ike họrọ otu BANK_ROW_COLUMN ma ọ bụ kọlụm BANK ROW.
Ahapụla m kọlụm ụlọ akụ ROW nke bụ maapụ adreesị nke ndabara.

Example imewe Simulation na synthesizable ule bench

N'okpuru ntọala Simulation, họrọ QuestaSim/ModelSim Simulator wee chọgharịa gaa na ebe ọba akwụkwọ achịkọtara.
Maka nkọwa gbasara nrụtụ aka na ngwaọrụ ndị ọzọ wụnye ụzọ, na-ahọpụta simulator ebumnuche, na ịchịkọta na nkewa ọba akwụkwọ, ị nwere ike zoo aka na (UG900) Vivado Design Suite User Guide Logic Simulation.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-3

Gbaa ịme anwansị ahụ site na GUI (pịa Run Simulation Tab na njikwa ọrụ) wee hụ na ị na-ahụ ozi “ule gafere” na transcript.

Mgbanwe nke Simulation RTL

  1. Pịa aka nri taabụ isi mmalite, họrọ "tinye ma ọ bụ mepụta isi mmalite ịme anwansị", wee chọgharịa na mig7_perfsim_traffic_generator.sv file wee pịa rụchaa ka ịgbakwunye ya.
  2. Pịa aka nri taabụ isi mmalite, họrọ “tinye ma ọ bụ mepụta isi mmalite ịme anwansị”, chọgharịa na perfsim_stimulus.txt, wee pịa rụchaa ka ịgbakwunye ya.
  3. Kwupụta onye bụbuample_top instantiation na sim_tb_top.v file.
  4. Tinye ahịrị RTL dị n'okpuru na sim_tb_top,v
  • localparam APP_ADDR_WIDTH = 28;
  • localparam APP_DATA_WIDTH = 64;
  • localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
  • localparam MEM_ADDR_ORDER = "BANK_ROW_COLUMN";
  • localparam BANK_WIDTH = 3;
  • localparam RANK_WIDTH = 1;
  • waya [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
  • waya [2:0] c0_ddr3_app_cmd;
  • waya c0_ddr3_app_en;
  • waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
  • waya c0_ddr3_app_wdf_end;
  • waya [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
  • waya c0_ddr3_app_wdf_wren;
  • waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
  • waya c0_ddr3_app_rd_data_end;
  • waya c0_ddr3_app_rd_data_valid;
  • waya c0_ddr3_app_rdy;
  • waya c0_ddr3_app_wdf_rdy;
  • waya c0_data_compare_error;
  • waya ui_clk;
  • waya ui_clk_sync_rst;
  • waya ngwa_sr_req = 0;
  • waya ngwa_ref_req = 0;
  • ngwa waya_zq_req =0;
  • waya c0_app_wdf_mask =0;

Ngwa ngwa njikwa ebe nchekwa FPGA

mig_7series_0_mig u_mig_7series_0_mig (
// Ebe nchekwa ọdụ ụgbọ mmiri

  • .ddr3_addr (ddr3_addr_fpga),
  • .ddr3_ba (ddr3_ba_fpga),
  • .ddr3_cas_n (ddr3_cas_n_fpga),
  • .ddr3_ck_n (ddr3_ck_n_fpga),
  • .ddr3_ck_p (ddr3_ck_p_fpga),
  • .ddr3_cke (ddr3_cke_fpga),
  • .ddr3_ras_n (ddr3_ras_n_fpga),
  • .ddr3_reset_n (ddr3_reset_n),
  • .ddr3_we_n (ddr3_we_n_fpga),
  • .ddr3_dq (ddr3_dq_fpga),
  • .ddr3_dqs_n (ddr3_dqs_n_fpga),
  • .ddr3_dqs_p (ddr3_dqs_p_fpga),
  • .init_calib_complete (init_calib_complete),
  • .ddr3_cs_n (ddr3_cs_n_fpga),
  • .ddr3_dm (ddr3_dm_fpga),
  • .ddr3_odt (ddr3_odt_fpga),

// Ngwa interface ọdụ ụgbọ mmiri

  • .app_addr (c0_ddr3_app_addr),
  • .app_cmd (c0_ddr3_app_cmd),
  • .app_en (c0_ddr3_app_en),
  • .app_wdf_data (c0_ddr3_app_wdf_data),
  • .app_wdf_end (c0_ddr3_app_wdf_end),
  • .app_wdf_wren (c0_ddr3_app_wdf_wren),
  • .app_rd_data (c0_ddr3_app_rd_data),
  • .app_rd_data_end (app_rd_data_end),
  • .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
  • .app_rdy (c0_ddr3_app_rdy),
  • .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
  • .app_sr_req (app_sr_req),
  • .app_ref_req (app_ref_req),
  • .app_zq_req (app_zq_req),
  • .app_sr_active (app_sr_active),
  • .app_ref_ack (app_ref_ack),
  • .app_zq_ack (app_zq_ack),
  • .ui_clk (ui_clk),
  • .ui_clk_sync_rst (ui_clk_sync_rst),
  • .app_wdf_mask (c0_ddr3_app_wdf_mask),

// Sistemụ elekere ọdụ ụgbọ mmiri

  • .sys_clk_i (sys_clk_i),

// ọdụ ụgbọ mmiri elekere

  • .clk_ref_i (clk_ref_i),
  • .sys_rst (sys_rst)
  • );

Ngwa ngwa generator na-arụ ọrụ

mig7_perfsim_traffic_generator#
(
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK ),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

u_traffic_gen
(
.clk (ui_clk),
.nke mbụ (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd),
.app_addr (c0_ddr3_app_addr),
.app_en (c0_ddr3_app_en),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

  • 5. Megharịa APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH na BANK_WIDTH dịka akụkụ ebe nchekwa gị siri dị.
    Enwere ike nweta uru site na _mig.v file.
  • Aha nzizi nke edo edo edochara anya mig_7series_0_mig nwere ike ịdịgasị iche dabere na aha akụrụngwa gị n'oge imepụta IP, lelee ma ị họrọla aha dị iche wee gbanwee ya otu a.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-4
  • Ozugbo emepụtara IP, mepee ya _mig.v file ma gafee-elele maka mgbanwe ọ bụla na aha akara LHS wee mezie ha.
  • app_sr_req, app_ref_req na app_zq_req kwesịrị ibido ka ọ bụrụ 0.
  • Dị ka example_top.v ka ekwuputara na nke ọhụrụ files na-agbakwunyere, eleghị anya ị ga-ahụ "?" n'akụkụ nke
    mig_7series_0_mig.v file n'okpuru isi mmalite ịme anwansị.
    Iji map nke ziri ezi file, pịa aka nri mig_7series_0_mig.v, họrọ "Tinye isi mmalite", Chọgharịa gaa na
    /mig_7usoro_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
    ma tinye mig_7series_0_mig_sim.v file.
  • Ọ bụrụ na ị na-ahụ "?" maka n'okpuru files, tinye RTL niile files na clocking, njikwa, ip_top, phy na UI nchekwa.
  • Ozugbo emere mgbanwe RTL yana ihe niile achọrọ files na-agbakwunyere na isi mmalite ịme anwansị gị, Ọchịchị kwesịrị ịdị ka foto 5.
    Nke fileA na-agbakwụnye ihe ndị e mere ka ọ pụta ìhè na ọbara ọbara, yana "?" A na-atụ anya na modul metụtara ECC dịka nhazi ebe nchekwa ahọpụtara nwere nhọrọ ECC nwere nkwarụ.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-5

Ihe mkpali File Nkọwa
Ụkpụrụ mkpali ọ bụla bụ 48 ibe n'ibe na usoro a kọwara na Figure 6-1 ruo 6-4.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-6

Idozi adreesị (adreesị [35:0])

Edere adreesị ahụ na mkpali dị ka eserese 7-1 ruo na eserese 7-6. Ekwesịrị itinye mpaghara adreesị niile n'ụdị hexadecimal. Oghere adreesị niile bụ obosara nke nwere ike kewaa site na anọ iji tinye n'ụdị hexadecimal. Oche ule na-eziga naanị ibe n'ibe adreesi achọrọ na njikwa ebe nchekwa.
Maka example, na nhazi ụlọ akụ asatọ, ọ bụ naanị bank Bits [2:0] ka a na-ezigara na Controller ebe nchekwa ma na-eleghara ihe ndị fọdụrụnụ anya. A na-enye gị ntakịrị ntakịrị maka mpaghara adreesị ka ị tinye adreesị ahụ n'ụdị hexadecimal.
Ị ga-akwadorịrị na uru etinyere dabara na obosara nke nhazi enyere.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-7

  • Adreesị kọlụm (kọlụm[11:0]) - A na-enye Adreesị kọlụm dị na mkpali ka ọ dịkarịa ala 12 bits, mana ịkwesịrị ilebara nke a dabere na oke obosara kọlụm edobere na nhazi gị.
  • Adreesị ahịrị ( Ahịrị[15:0]) - A na-enye adreesị ahịrị n'ime ihe mkpali ka ọ dịkarịa ala 16 bits, mana ịkwesịrị ilebara nke a dabere na oke obosara ahịrị edobere na nhazi gị.
  • Adreesị ụlọ akụ (Bank[3:0]) - A na-enye adreesị ụlọ akụ n'ime ihe mkpali ka ọ dịkarịa ala nkeji anọ, mana ịkwesịrị ilebara nke a dabere na oke obosara ụlọ akụ edobere na imewe gị.
  • Adreesị ọkwa (ọkwa [3:0]) - A na-enye adreesị ọkwa n'ime ihe mkpali ka ọ dịkarịa ala nkeji anọ, mana ịkwesịrị ilebara nke a dabere na oke obosara ọkwa nke edobere na nhazi gị.
    A na-agbakọta adreesị ahụ dabere na oke ọkwa MEM_ADDR_ORDER dị elu wee ziga ya na interface onye ọrụ.

Tinyegharịa iwu (Iwu kwugharịa [7:0])
Ngụ ugboro ugboro iwu bụ ọnụ ọgụgụ nke oge a na-emeghachi iwu otu ọ bụla na Interface Onye ọrụ. A na-agbakwunye adreesị maka nkwugharị ọ bụla site na 8. Ọnụ nkwughachi kachasị bụ 128.
Oche ule anaghị elele ókèala kọlụm ma ọ na-agbakọ gburugburu ma ọ bụrụ na agafere oke kọlụm kachasị n'oge mmụba.
Iwu 128 mejupụtara ibe ahụ. Maka adreesị kọlụm ọ bụla na-abụghị 0, nkwughachi nke 128 na-ejedebe na ịgafe oke kọlụm wee kechie ya na mmalite nke adreesị kọlụm.

Iji ụgbọ ala
A na-agbakọ ojiji ụgbọ ala na Interface Onye ọrụ na-ewere mkpokọta ọnụọgụgụ na-ede n'uche ma jiri nha anya ndị a:

Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-8

  • BL8 na-ewe okirikiri elekere ebe nchekwa anọ
  • end_of_stimulus bụ oge emere iwu niile.
  • calib_done bụ oge a ga-eme mmezi.

Example Ụkpụrụ
Ndị a bụ examples dabere na MEM_ADDR_ORDER atọrọ na BANK_ROW_COLUMN.

Ụkpụrụ Ọgụgụ Otu
00_0_2_000F_00A_1 - Usoro a bụ otu ọgụgụ sitere na kọlụm 10, ahịrị 15, na ụlọ akụ nke abụọ.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-9Ụkpụrụ Ode Otu Otu
00_0_1_0040_010_0 - Usoro a bụ otu ederede na kọlụm nke 32, ahịrị 128, na ụlọ akụ nke mbụ.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-10Naanị dee ma gụọ n'otu adreesị
00_0_2_000F_00A_0 – Ụkpụrụ a bụ otu ederede na kọlụm 10, ahịrị 15 na ụlọ akụ nke abụọ.
00_0_2_000F_00A_1 – Ụkpụrụ a bụ otu ọgụgụ sitere na kọlụm 10, ahịrị 15, na ụlọ akụ nke abụọXilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-11

Otu adreesị na-ede ma na-agụ ọtụtụ
0A_0_0_0010_000_0 – Nke a kwekọrọ na 10 na-ede na adreesị malite na 0 ruo 80 nke enwere ike ịhụ na kọlụm.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-12

0A_0_0_0010_000_1 – Nke a dabara na 10 na-agụ na adreesị malite na 0 ruo 80 nke enwere ike ịhụ na kọlụm.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-13

Kechie ibe n'oge a na-ede
0A_0_2_000F_3F8_0 – Nke a kwekọrọ na 10 na-ede na adreesị kọlụm ọbọp na mmalite nke ibe mgbe otu ederede gasịrị.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-14

Na-eme ka ndị na-emepụta ihe na-arụ ọrụ okporo ụzọ

N'oge a, ị ga-emecha na MIG example imewe ịme anwansị. Nke a na-egosi na ntọlitela ịme anwansị gị adịla njikere, ịmeela mmụgharị RTL arụmọrụ, usoro ịme anwansị ọhụrụ ahụ ziri ezi ma ghọtala usoro mkpali. Jiri 16 dee ma gụọ na perfsim_stimulus.txt ọzọ.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-15

Gbaa ọsọ-niile, chere ruo mgbe init_calib_complete mgbaàmà na-kwusiri ike, na ị ga-enwe ike ịhụ tụrụ aro ọnụ ọgụgụ nke na-ede na-agụ. Simulation ahụ ga-akwụsị. Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-16

Mgbe a kpaliri gị ịkwụsị ịme anwansị, họrọ Mba wee gaa na mpio ederede ebe ị ga-enwe ike ịhụ ọnụ ọgụgụ arụmọrụ. Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-17

Ọ bụrụ na ị họrọ "kwụsị ịme anwansị" A ga-edeta ọnụ ọgụgụ arụmọrụ na a file aha ya mig_band_width_output.txt dị na sim_1/akpa àgwà nchekwa.

Exampụzọ ndekọ aha:-
/mig_7usoro_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behavXilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-18

Ị nwere ike ịnọ na-eche ihe kpatara pasentị ahụtage bus utilization is ony 29. Tinyegharịa simulation na otu ntọala IP mana naanị ịgbanwe ihe mkpali. file ruo 256 na-ede na 256 na-agụ

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Ị ga-ahụ pasentịtage dị ka 85, nke na-egosi na DDR3 na-enye mma ụgbọ ala itinye n'ọrụ maka ogologo usoro nke na-ede na-agụ gbawara. Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-19

Ụzọ izugbe iji melite arụmọrụ

Enwere ike kewaa ihe ndị na-emetụta arụmọrụ na ngalaba abụọ:

  1. Specific ebe nchekwa
  2. Specific njikwaXilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-20

Ọnụ ọgụgụ 9 na-enye gị ohereview nke okwu ndị bụ ebe nchekwa kpọmkwem.
N'adịghị ka SRAMs na Block Memories DDR2 ma ọ bụ DDR3 arụmọrụ abụghị naanị ọnụ ọgụgụ data kacha.

Ọ dabere n'ọtụtụ ihe oge, gụnyere:

  • tRCD: Oge igbu oge n'ahịrị (ma ọ bụ ras ka ọ bụrụ igbu oge).
  • tCAS (CL): Adreesị kọlụm strobe latency.
  • tRP: Ahịrị prechaj gbue oge.
  • tRAS: Oge n'ahịrị (gbalite ka ịgbanwee).
  • tRC: Oge okirikiri ahịrị. tRC = tRAS + tRP
  • tRAC: Ịgba oge ịnweta Radom. tRAC = tRCD + tCAS
  • tCWL: Cas dee latency.
  • tZQ: Oge nhazi nke ZQ.
  • tRFC: Oge okirikiri ume ọhụrụ
  • tWTR: Dee ka ị gụọ igbu oge. Dee azụmahịa ikpeazụ ka ị gụọ oge iwu.
  • tWR: Dee oge mgbake. Dee azụmahịa ikpeazụ na oge ịkwụ ụgwọ

Oge usoro niile edepụtara na-adabere n'ụdị ebe nchekwa ejiri na ọkwa ọsọ nke ebe nchekwa.
Enwere ike ịchọta nkọwa ndị ọzọ na nkọwapụta na nkọwa oge na DDR2 DDR3 JEDEC ma ọ bụ na akwụkwọ data ngwaọrụ ebe nchekwa ọ bụla.

Ịrụ ọrụ dabere na ka esi enweta ebe nchekwa. Usoro adreesị dị iche iche na-enye nsonaazụ arụmọrụ dị iche iche.

Oge ebe nchekwa gafere

  1. Oge ịgbalite na oge ịkwụ ụgwọ mgbe ị na-agbanwe gaa na ụlọ akụ / ahịrị ọhụrụ ma ọ bụ na-agbanwe ahịrị na otu ụlọ akụ - Ya mere ọ bụrụ na ibelata mgbanwe mgbanwe, nke a nwere ike wepu tRCD na tRP.
  2. Zipụ na-aga n'ihu dee ma ọ bụ gụọ iwu - Ijikwa oge tCCD.
  3. Wedata ederede ịgụ na gụọ ka ị dee mgbanwe mgbanwe iwu - Dee oge mgbake ka ị gbanwee ịgụ ohere, oge ntụgharị ụgbọ ala iji gbanwee site na ịgụ ka ọ dee
  4. Tọọ oge ume ọhụrụ kwesịrị ekwesị.
    • DDR3 SDRAM chọrọ okirikiri ume ọhụrụ na nkezi nkeji oge nke tREFI.
    • Enwere ike ịnye iwu ume ọhụrụ 8 kacha karịa ("wetara"). Nke a anaghị ebelata ọnụọgụ ume ọhụrụ, mana oge kacha n'etiti iwu ume ọhụrụ abụọ gbara ya gburugburu bụ naanị 9 × tREFI.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-21
  • Jiri ụlọ akụ niile - Usoro okwu kwesịrị ekwesị ka mma.
    • Oghere-Bank-kọlụm: Maka azụmahịa na-eme na oghere adreesị usoro, isi na-emepe otu ahịrị na-akpaghị aka na ụlọ akụ na-esote nke ngwaọrụ DRAM iji gaa n'ihu na azụmahịa ahụ mgbe njedebe nke ahịrị dị adị ruru. Ọ dabara nke ọma na ngwa chọrọ mgbawa nnukwu ngwugwu data na ebe adreesị usoro.
    • Kọlụm-Ahiri Bank: Mgbe ị na-agafe oke ahịrị, a ga-emechi ahịrị dị ugbu a, a ga-emeghe ahịrị ọzọ n'ime otu ụlọ akụ. MSB bụ adreesị ụlọ akụ, nke enwere ike iji gbanwee site na ụlọ akụ dị iche iche. Ọ dabara maka mkpụmkpụ, azụmahịa ndị ọzọ na-enweghị usoro gaa n'otu ngọngọ nke ebe nchekwa ruo nwa oge wee wụba na ngọngọ ọzọ (ụlọ akụ)
  • Ogologo gbawara
    • A na-akwado BL 8 maka DDR3 na usoro 7. BC4 nwere arụmọrụ dị ala nke na-erughị 50%. Nke a bụ n'ihi na oge ogbugbu nke BC4 bụ otu BL8. A na-ekpuchi data ahụ naanị n'ime akụrụngwa ahụ.
    • N'ọnọdụ ebe ị na-achọghị ịde n'uju, ma nkpuchi data ma ọ bụ dee-mgbe-agụ nwere ike tụlee.
  • Tọọ oge ZQ kwesịrị ekwesị (naanị DDR3)
    Onye njikwa na-eziga ma ZQ Short (ZQCS) na ZQ Long (ZQCL) iwu calibration.
    • Jide n'aka DDR3 Jedec Standard
    • A tụlere calibration ZQ na ngalaba 5.5 nke JEDEC Spec JESD79-3 DDR3 SDRAM Standard.
    • ZQ Calibration calibration On Die Termination (ODT) n'oge oge niile iji kọwaa ọdịiche dị n'ofe VT.
    • Logic dị na bank_common.v/vhd
    • Parameter Tzqcs na-ekpebi ọnụego ezigara ZQ Calibration iwu na ebe nchekwa
    • t nwere ike gbanyụọ counter wee jiri aka zipu site na iji app_zq_req, ọ dị ka iji aka na-eziga ume ọhụrụ.
      Rụtụ aka na (Xilinx Azịza 47924) maka nkọwa.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-22

Ọnụ ego njikwa

  1. Ọgụgụ oge - rụtụ aka (Azịza nke Xilinx 43344) maka nkọwa.
    • Agbanwela oge ịgụ ihe
    • Mafere agụ oge n'oge a na-ede wee wepụta ọnụọgụgụ ndị a gụfuru tupu agụọ nke ọma
  2. Nhazigharị – rụtụ aka (Azịza nke Xilinx 34392) maka nkọwa.
    Maka atụmatụ onye ọrụ na AXI Interface ọ ka mma ịme nke a.
    • Ndozigharị bụ mgbagha na-ele anya n'ihu ọtụtụ iwu ma gbanwee iwu onye ọrụ iji mee ka iwu na-abụghị ebe nchekwa ghara ịdị na bandwidth bara uru. Arụmọrụ ahụ metụtakwara ụkpụrụ okporo ụzọ n'ezie.
    • Dabere na ụkpụrụ adreesị, nhazigharị na-enyere aka ịwụpụ precharge ma rụọ ọrụ iwu na-eme ka tRCD na tRP ghara ịnwe obosara data bandwit.Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-23
  3. Gbalịa ịbawanye ọnụ ọgụgụ nke Machines Bank.
    • Ọtụtụ n'ime mgbagha onye njikwa na-ebi na igwe ụlọ akụ ma ha na-edekọrịta na ụlọ akụ DRAM
    • Igwe akụ enyere na-ejikwa otu ụlọ akụ DRAM n'oge ọ bụla.
    • Ọrụ igwe ụlọ akụ dị ike n'ihi ya, ọ dịghị mkpa ịnwe igwe ụlọ akụ maka ụlọ akụ anụ ahụ ọ bụla.
    • Enwere ike ịhazi igwe ụlọ akụ, mana ọ bụ azụmaahịa n'etiti mpaghara na arụmọrụ.
    • Ọnụọgụ nke igwe ụlọ akụ enwere ike sitere na 2-8.
    • Site na ndabara, a na-ahazi igwe ụlọ akụ 4 site na paramita RTL.
    • Iji gbanwee igwe ụlọ akụ, tụlee oke nBANK_MACHS = 8 dị na memc_ui_top Ex.ample maka igwe ụlọ akụ 8 - nBANK_MACHS = 8

Ị mara ugbu a ihe ndị na-emetụta arụmọrụ.
Tụlee ngwa dị elu nke na-enye gị 512 data bytes kwa ngwugwu ma ịchọrọ ịchekwa ha na ebe nchekwa dị iche iche. Dị ka 512 data bytes hà nhata 64 DDR3 data gbawara, megharịa example imewe na ihe mkpali file nwere 512 na-ede, 512 na-agụ na ngbanwe ahịrị maka 64 ọ bụla na-ede ma ọ bụ na-agụ:

  • 3f_0_0_0000_000_0
  • 3f_0_0_0001_000_0
  • 3f_0_0_0002_000_0
  • 3f_0_0_0003_000_0
  • 3f_0_0_0004_000_0
  • 3f_0_0_0005_000_0
  • 3f_0_0_0006_000_0
  • 3f_0_0_0007_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_0_0001_000_1
  • 3f_0_0_0002_000_1
  • 3f_0_0_0003_000_1
  • 3f_0_0_0004_000_1
  • 3f_0_0_0005_000_1
  • 3f_0_0_0006_000_1
  • 3f_0_0_0007_000_1

Na njedebe nke ịme anwansị ahụ, ị ​​​​ga-ahụ na ojiji ụgbọ ala dị na pasent 77. Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-24

Ọgụgụ 11: Statistics Performance maka 512 na-ede na 512 na-agụ - Ngbanwe ahịrị maka 64 na-ede ma ọ bụ gụọ. 

Ị nwere ike itinye ihe ọmụma a mụtara na ngalaba mbụ iji melite arụmọrụ. Ya na a view iji tinye n'ọrụ ụlọ akụ niile kama ịgbanwe ahịrị ahịrị, gbanwee ụkpụrụ adreesị iji gbanwee ụlọ akụ dịka egosiri n'okpuru.
Nke a dabara na ịtọ ROW_BANK_Column na ntọala maapụ ebe nchekwa na MIG GUI.

  • 3f_0_0_0000_000_0
  • 3f_0_1_0000_000_0
  • 3f_0_2_0000_000_0
  • 3f_0_3_0000_000_0
  • 3f_0_4_0000_000_0
  • 3f_0_5_0000_000_0
  • 3f_0_6_0000_000_0
  • 3f_0_7_0000_000_0
  • 3f_0_0_0000_000_1
  • 3f_0_1_0000_000_1
  • 3f_0_2_0000_000_1
  • 3f_0_3_0000_000_1
  • 3f_0_4_0000_000_1
  • 3f_0_5_0000_000_1
  • 3f_0_6_0000_000_1
  • 3f_0_7_0000_000_1

Na njedebe nke ịme anwansị ị ga-ahụ na mbụ 77 Pasent Utiility Bus ugbu a bụ 87! Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-25

Ọ bụrụ na ị ka na-achọ ịrụ ọrụ dị elu, ị nwere ike ịga maka nnukwu ngwungwu 1024 ma ọ bụ 2048 bytes, ma ọ bụ tụlee ume ọhụrụ akwụkwọ ntuziaka.

Mara: Xilinx anaghị akwado ịgafe onye njikwa ume ọhụrụ n'ihi na anyị ejighị n'aka ma ị ga-enwe ike izute Jedec auto ume ọhụrụ oge nke na-emetụta ntụkwasị obi data.
Site n'akụkụ njikwa ị nwere ike ịgbanwe nBANk_MACH wee hụ ọganihu na arụmọrụ.
Agbanyeghị, nke a nwere ike imetụta oge imewe gị, biko rụtụ aka (Azịza nke Xilinx 36505) maka nkọwa na nBANk_MACHXilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-26

Mepee isi_name_mig_sim.v file wee gbanwee paramita nBANK_MACHS site na 4 ruo 8 wee megharịa simulation ahụ. Iji nweta uru paramita ga-arụ ọrụ na ngwaike, ịkwesịrị imelite core_name_mig.v file.
Ejiri m otu ụkpụrụ ahụ ebe anyị nwetara ntinye ụgbọ ala 87% (nọmba -12).
Ebe nBANK_MACHS atọrọ ka ọ bụrụ 8, arụmọrụ dị ugbu a 90%. Xilinx DDR2 MIG 7 Atụmatụ arụmọrụ-fig-27

Marakwa na ½ na ¼ ndị na-achịkwa na-emetụta arụmọrụ na-adịghị mma n'ihi latency ha.
Maka examplee, ebe ọ bụ na anyị nwere ike izipu iwu naanị okirikiri 4 CK ọ bụla enwere mgbakwunye mgbakwunye mgbe ụfọdụ mgbe ị na-agbaso nkọwa oge DRAM kacha nta, nke nwere ike ibelata arụmọrụ site na usoro iwu.
Gbalịa ndị njikwa dị iche iche ka ịchọta nke dabara na arụmọrụ gị chọrọ.

Ntụaka

  1. Zynq-7000 AP SoC na 7 Series FPGAs MIS v2.3 [UG586]
  2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Akụkọ ngbanwe
13/03/2015 - mwepụta mbụ

Budata PDF: Xilinx DDR2 MIG 7 Ntuziaka Atụmatụ arụmọrụ

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