Xilinx DDR2 MIG 7 Jagoran Ƙimar Ayyuka

Muhimmiyar Bayani: Wannan PDF ɗin da aka zazzage na rikodin Amsa an samar da shi don haɓaka amfani da iya karantawa. Yana da mahimmanci a lura cewa Bayanan Amsa su ne Web- tushen abun ciki wanda ake sabuntawa akai-akai yayin da sabbin bayanai ke samuwa. Ana tunatar da ku ziyarci Tallafin Fasaha Xilinx Website da review (Xilinx Amsa 63234) don sabuwar sigar wannan Amsa.

Gabatarwa

Saboda yadda aka tsara abubuwan ƙwaƙwalwar DDR2 da DDR3 kuma an tsara tsarin MIG 7, aikin ba ya kai tsaye.
Yana buƙatar fahimtar ma'auni na Jedec Timeing daban-daban da Architecture mai sarrafawa, kuma kuna buƙatar gudanar da simulations don samun ƙididdiga.
Gabaɗaya ka'ida don ƙayyadaddun aiki iri ɗaya ne amma wannan takaddar tana ba da hanya mai sauƙi don samun inganci ta amfani da MIG ex.ample zane tare da taimakon gwajin benci da kara kuzari filean makala anan.

Ingantaccen bandwidth

Bus ɗin bayanai na DRAM yana cimma kusan kololuwar bandwidth kawai yayin fashewar karatu da rubutu kuma saman sa yana rage ingantaccen ƙimar bayanai.
Wasu 'yan exampAbubuwan da ake bukata sune:

• precharge lokacin isa ga layuka a cikin banki ɗaya (Adreshin shiga ba a cikin bugun layi ɗaya ba)
• rubuta lokacin dawowa don canzawa daga rubutu zuwa damar karantawa
• lokacin juyawa bas don canzawa daga karantawa zuwa rubuta damar shiga

Bandwidth mai inganci = Matsakaicin Matsakaicin Mafi Girma * Inganci 

MIG Design Generation

Koma zuwa UG586 Babi na 1 don cikakkun bayanai na mataki-mataki akan MIG IP da example tsara tsara.
Kafin gudanar da aikin kwaikwayo na MIG 7 Series, yi waɗannan don tabbatar da yanayin simintin ku yana da kyau. Bude MIG exampzana da taswirar dakunan karatu masu dacewa, gudanar da simulation, kuma tabbatar da cewa za ku iya ganin saƙon "gwajin ya ci nasara" a cikin kwafin.
Don nuna kwarara Na ƙirƙiri MIG IP don xc7vx690tffg1761-2 kuma na kira tsohonampzane.
Abubuwa biyu da ya kamata a lura dasu sune ragowar adreshin ƙwaƙwalwar ajiya da zaɓin adireshin adireshin ƙwaƙwalwar ajiya.
Don misaliample, Na zaɓi MT41J128M8XX-125 a ƙarƙashin zaɓin juzu'in ɓangaren ƙwaƙwalwar ajiya.

Don zaɓin ɓangaren ƙwaƙwalwar ajiya daga Hoto-1, jere = 14, shafi = 10 da banki = 3, don haka app_addr_width = jere + shafi + banki + daraja = 28

Kuna iya zaɓar ko dai BANK_ROW_COLUMN ko ROW BANK Column.
Na bar ROW BANK Column wanda shine tsohuwar taswirar adireshin.

Example zane Simulation tare da synthesizable gwajin benci

Ƙarƙashin saitunan kwaikwayo, zaɓi QuestaSim/ModelSim Simulator kuma bincika wurin da aka haɗa ɗakunan karatu.
Don cikakkun bayanai kan nuni ga kayan aikin ɓangare na uku shigar da hanya, zaɓin na'urar kwaikwayo da aka yi niyya, da tattarawa da tsara ɗakunan karatu, zaku iya komawa zuwa (UG900) Vivado Design Suite Jagora Jagora Logic Simulation.

Gudun simulation ta hanyar GUI (Danna Run Simulation Tab a cikin mai sarrafa aikin) kuma tabbatar cewa kun ga saƙon "gwaji ya ci nasara" a cikin kwafin.

gyare-gyaren Simulators na RTL

1. Danna dama akan shafin tushen, zaɓi "ƙara ko ƙirƙirar kafofin kwaikwayo", sannan bincika zuwa mig7_perfsim_traffic_generator.sv file kuma danna gama don ƙara shi.
2. Danna maballin dama, zaɓi "ƙara ko ƙirƙirar kafofin kwaikwayo", bincika zuwa perfsim_stimulus.txt, sannan danna gama don ƙarawa.
3. Yi sharhi example_top instantiation a cikin sim_tb_top.v file.
4. Ƙara layin RTL na ƙasa zuwa sim_tb_top,v

• localparam APP_ADDR_WIDTH = 28;
• localparam APP_DATA_WIDTH = 64;
• localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
• localparam MEM_ADDR_ORDER = "BANK_ROW_COLUMN";
• localparam BANK_WIDTH = 3;
• localparam RANK_WIDTH = 1;
• waya [APP_ADDR_WIDTH-1:0] c0_ddr3_app_addr;
• waya [2:0] c0_ddr3_app_cmd;
• waya c0_ddr3_app_en;
• waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_wdf_data;
• waya c0_ddr3_app_wdf_end;
• waya [APP_MASK_WIDTH-1:0] c0_ddr3_app_wdf_mask;
• waya c0_ddr3_app_wdf_wren;
• waya [APP_DATA_WIDTH-1:0] c0_ddr3_app_rd_data;
• waya c0_ddr3_app_rd_data_end;
• waya c0_ddr3_app_rd_data_valid;
• waya c0_ddr3_app_rdy;
• waya c0_ddr3_app_wdf_rdy;
• waya c0_data_kwatanta_kuskure;
• waya ui_clk;
• waya ui_clk_sync_rst;
• waya app_sr_req = 0;
• waya app_ref_req = 0;
• waya app_zq_req =0;
• waya c0_app_wdf_mask =0;

FPGA Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa

mig_7series_0_mig u_mig_7series_0_mig (
// Ƙwaƙwalwar ƙwaƙwalwar ajiya

• ddr3_addr (ddr3_addr_fpga),
• ddr3_ba (ddr3_ba_fpga),
• ddr3_cas_n (ddr3_cas_n_fpga),
• ddr3_ck_n (ddr3_ck_n_fpga),
• ddr3_ck_p (ddr3_ck_p_fpga),
• ddr3_cke (ddr3_cke_fpga),
• ddr3_ras_n (ddr3_ras_n_fpga),
• .ddr3_reset_n (ddr3_reset_n),
• ddr3_we_n (ddr3_we_n_fpga),
• ddr3_dq (ddr3_dq_fpga),
• .ddr3_dqs_n (ddr3_dqs_n_fpga),
• ddr3_dqs_p (ddr3_dqs_p_fpga),
• .init_calib_complete (init_calib_complete),
• ddr3_cs_n (ddr3_cs_n_fpga),
• ddr3_dm (ddr3_dm_fpga),
• ddr3_odt (ddr3_odt_fpga),

// Aikace-aikacen tashar jiragen ruwa

• .app_addr (c0_ddr3_app_addr),
• .app_cmd (c0_ddr3_app_cmd),
• .app_en (c0_ddr3_app_en),
• .app_wdf_data (c0_ddr3_app_wdf_data),
• .app_wdf_end (c0_ddr3_app_wdf_end),
• .app_wdf_wren (c0_ddr3_app_wdf_wren),
• .app_rd_data (c0_ddr3_app_rd_data),
• .app_rd_karshen_data_(app_rd_data_end),
• .app_rd_data_valid (c0_ddr3_app_rd_data_valid),
• .app_rdy (c0_ddr3_app_rdy),
• .app_wdf_rdy (c0_ddr3_app_wdf_rdy),
• .app_sr_req (app_sr_req),
• .app_ref_req (app_ref_req),
• .app_zq_req (app_zq_req),
• .app_sr_active (app_sr_active),
• .app_ref_ack (app_ref_ack),
• .app_zq_ack (app_zq_ack),
• .ui_clk (ui_clk),
• .ui_clk_sync_rst (ui_clk_sync_rst),
• .app_wdf_mask (c0_ddr3_app_wdf_mask),

// Tsarin Agogon Mashigai

• sys_clk_i (sys_clk_i),

// Tashar jiragen ruwa na agogo

• .clk_ref_i (clk_ref_i),
• .sys_rst (sys_rst)
• );

Ana aiwatar da janareta na zirga-zirga nan take

mig7_perfsim_traffic_generator#
(
APP_DATA_WIDTH (APP_DATA_WIDTH),
.COL_WIDTH (COL_WIDTH),
ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER),
.tCK (tCK),
.ADDR_WIDTH (APP_ADDR_WIDTH)
)

u_traffic_gen
(
.clk (ui_clk),
.rst (ui_clk_sync_rst),
.init_calib_complete (init_calib_complete),
.cmp_error (c0_data_compare_error),
.app_wdf_rdy (c0_ddr3_app_wdf_rdy),
.app_rd_data_valid (c0_ddr3_app_rd_data_valid),
.app_rd_data (c0_ddr3_app_rd_data),
.app_rdy (c0_ddr3_app_rdy),
.app_cmd (c0_ddr3_app_cmd),
.app_addr (c0_ddr3_app_addr),
.app_en (c0_ddr3_app_en),
.app_wdf_mask (c0_ddr3_app_wdf_mask),
.app_wdf_data (c0_ddr3_app_wdf_data),
.app_wdf_end (c0_ddr3_app_wdf_end),
.app_wdf_wren (c0_ddr3_app_wdf_wren)
);

• 5. Gyara APP_ADDR_WIDTH, APP_DATA_WIDTH, RANK_WIDTH da BANK_WIDTH bisa ga zaɓin ɓangaren ƙwaƙwalwar ajiyar ku.
  Za a iya samun darajar daga _mig.v file.
• Sunan nan take mai launin rawaya mai haskakawa mig_7series_0_mig na iya bambanta dangane da sunan bangaren ku yayin ƙirƙirar IP, tabbatar da idan kun zaɓi wani suna daban kuma canza shi daidai.
• Da zarar an samar da IP bude _mig.v file da bincika kowane bambance-bambance a cikin sunayen siginar LHS kuma gyara su.
• app_sr_req, app_ref_req da app_zq_req yakamata a fara su zuwa 0.
• Kamar yadda example_top.v yayi sharhi kuma sabo fileAn ƙara, tabbas za ku ga "?" bayan da
  mig_7jeri_0_mig.v file karkashin simulation kafofin.
  Don taswirar daidai file, danna dama mig_7series_0_mig.v, zaɓi "Ƙara Sources", Bincika zuwa
  /mig_7jerin_0_example.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl
  kuma ƙara mig_7series_0_mig_sim.v file.
• Idan kun ga "?" ga na asali files, ƙara duk RTL files a cikin clocking, mai sarrafawa, ip_top, phy da manyan fayilolin UI.
• Da zarar an yi canje-canjen RTL da duk abin da ake buƙata fileAna ƙara s zuwa Tushen Simulations ɗin ku, Matsayin ya kamata ya yi kama da Hoto na 5.
  The files da aka haskaka a cikin ja an sake ƙara su, kuma "?" ana sa ran akan abubuwan da suka danganci ECC kamar yadda zaɓaɓɓen saitin ƙwaƙwalwar ajiya yana da zaɓi na ECC.

Ƙarfafawa File Bayani
Kowane tsari mai kara kuzari shine rago 48 kuma an siffanta tsarin a Figures 6-1 zuwa 6-4.

Rufaffen adireshi (Adireshi [35:0])

An sanya adireshin a cikin abin ƙarfafawa kamar yadda yake a cikin Hoto 7-1 zuwa Hoto 7-6. Ana buƙatar shigar da duk filayen adireshi cikin sigar hexadecimal. Duk filayen adireshi fadi ne da ke raba su hudu don shigar da tsarin hexadecimal. Benci na gwaji yana aika buƙatun da ake buƙata na filin adireshi ne kawai zuwa ga Mai sarrafa ƙwaƙwalwar ajiya.
Don misaliampLe, a cikin tsarin banki guda takwas, banki Bits [2:0] kawai ana aika zuwa Mai sarrafa ƙwaƙwalwar ajiya kuma sauran ragi ba a kula da su. Ana ba da ƙarin rago don filin adireshi don shigar da adireshin a cikin sigar hexadecimal.
Dole ne ku tabbatar da ƙimar da aka shigar yayi daidai da faɗin tsarin da aka bayar.

• Adireshin Rukunin (Shafi [11:0]) - Adireshin ginshiƙi a cikin abin ƙarfafawa ana bayar da shi zuwa matsakaicin ragi 12, amma kuna buƙatar magance wannan dangane da ma'aunin faɗin shafi da aka saita a ƙirar ku.
• Adireshin Layi (Layi[15:0]) - Adireshin layi a cikin abin ƙarfafawa ana bayar da shi zuwa matsakaicin ragi 16, amma kuna buƙatar magance wannan dangane da ma'aunin faɗin layin da aka saita a ƙirar ku.
• Adireshin Banki (Banki[3:0]) - Adireshin banki a cikin abin kara kuzari ana bayar da shi zuwa matsakaicin rago hudu, amma kuna buƙatar magance wannan bisa ma'aunin faɗin banki da aka saita a ƙirar ku.
• Adireshin Daraja (Rank[3:0]) - Adireshin matsayi a cikin abin ƙarfafawa ana bayar da shi zuwa matsakaicin rago huɗu, amma kuna buƙatar magance wannan bisa ma'aunin faɗin matsayi da aka saita a ƙirar ku.
  Adireshin an haɗa shi bisa babban matakin MEM_ADDR_ORDER kuma an aika zuwa ga mai amfani.

Maimaita Umurni (Maimaita Umurni [7:0])
Ƙididdigar maimaita umarni shine adadin lokacin da aka maimaita umarni daban-daban a Interface Mai amfani. Adireshin kowane maimaitu ana ƙara shi da 8. Matsakaicin ƙidayar maimaitawa shine 128.
Benci na gwaji baya duba iyakar shafi kuma yana zagaye idan an kai matsakaicin iyakar ginshiƙi yayin haɓakawa.
Dokokin 128 sun cika shafin. Ga kowane adireshin shafi ban da 0, adadin maimaitawa na 128 ya ƙare har ƙetare iyakar shafi kuma ya naɗe zuwa farkon adireshin shafi.

Amfani da bas
Ana ƙididdige amfani da bas ɗin a Interface Mai amfani yana ɗaukar jimlar adadin Karatu da Rubutu cikin la'akari kuma ana amfani da ma'auni mai zuwa:

• BL8 yana ɗaukar agogon ƙwaƙwalwar ajiya huɗu
• end_of_stimulus shine lokacin da aka yi duk umarni.
• calib_done shine lokacin da ake yin gyaran fuska.

Exampda Tsarin
Wadannan examples sun dogara ne akan MEM_ADDR_ORDER saita zuwa BANK_ROW_COLUMN.

Tsarin Karatu Guda
00_0_2_000F_00A_1 - Wannan tsarin karatu ɗaya ne daga shafi na 10, jere na 15, da banki na biyu.Tsarin Rubutu Guda Daya
00_0_1_0040_010_0 - Wannan tsarin rubutu guda ɗaya ne zuwa shafi na 32, jere na 128, da banki na farko.Rubutu Daya da Karanta zuwa Adireshi ɗaya
00_0_2_000F_00A_0 – Wannan tsarin rubutu guda ne zuwa shafi na 10, jere na 15, da banki na biyu.
00_0_2_000F_00A_1 – Wannan tsarin karatu ɗaya ne daga shafi na 10, jere na 15, da banki na biyu

Rubuce-rubuce da yawa da karantawa tare da Adireshi iri ɗaya
0A_0_0_0010_000_0 – Wannan yayi daidai da 10 ya rubuta tare da adireshin farawa daga 0 zuwa 80 wanda za'a iya gani a cikin shafi.

0A_0_0_0010_000_1 – Wannan yayi daidai da karantawa 10 tare da adireshin farawa daga 0 zuwa 80 wanda za'a iya gani a cikin shafi.

Rubutun Shafi Lokacin Rubutu
0A_0_2_000F_3F8_0 – Wannan yayi daidai da rubuce-rubuce 10 tare da adireshi shafi nannade zuwa farkon shafin bayan rubuta ɗaya.

Simulating da Performance Traffic Generator

A wannan lokacin an gama da MIG example zane kwaikwayo. Wannan yana nuna cewa saitin simintin ku ya shirya, kun yi gyare-gyare na simulation na RTL, sabon tsarin simintin daidai kuma kun fahimci tsarin ƙara kuzari. Shigar da simulation kuma tare da rubutawa 16 da karantawa a cikin perfsim_stimulus.txt.

Yi gudu-duk, jira har sai an tabbatar da siginar init_calib_complete, kuma za ku iya ganin adadin rubutu da karantawa. Daga nan za a daina simulation.

Lokacin da aka sa ka daina simulation, zaɓi A'a kuma je zuwa taga rubutun inda za ka iya ganin ƙididdigan aiki.

Idan ka zaɓa "bar simulation" za a rubuta kididdigar ayyuka zuwa a file mai suna mig_band_width_output.txt dake cikin sim_1/behave babban fayil.

ExampHanyar Hanyar:-
/mig_7jerin_0_example_perf_sim\mig_7series_0_example.sim/sim_1/behav

Kuna iya mamakin dalilin da yasa kashintagYi amfani da bas ɗin yana 29. Sake kunna simulation tare da saitunan IP iri ɗaya amma kawai canza abin ƙarfafawa. file zuwa 256 ya rubuta kuma 256 ya karanta

ff_0_0_0000_000_0
ff_0_0_0000_000_1

Yanzu zaku ga kashitage as 85, wanda ke nuna cewa DDR3 yana ba da mafi kyawun amfani da bas don dogon jerin rubuce-rubuce da karanta fashe.

Gaba ɗaya hanyoyin don Inganta Ayyuka

Abubuwan da ke tasiri tasiri za a iya raba su kashi biyu:

1. Ƙwaƙwalwar Ƙwaƙwalwa
2. Mai Gudanarwa Specific

Hoto na 9 yana ba ku gabaview daga cikin sharuddan da ke da takamaiman ƙwaƙwalwar ajiya.
Ba kamar SRAMs da Toshe Memories DDR2 ko DDR3 yi ba kawai matsakaicin adadin bayanai ba.

Ya dogara da dalilai masu yawa na lokaci, gami da:

• tRCD: Jinkirin Umurnin Layi (ko ras zuwa jinkirin cas).
• tCAS (CL): Latency adireshin ginshiƙi.
• tRP: Jinkirin cajin layi.
• tRASLokacin Aiki na Layi (kunna don canzawa).
• tRC: Lokacin zagayowar jere. tRC = tRAS + tRP
• tRAC: Jinkirin samun damar Radom. tRAC = tRCD + tCAS
• tCWL: Cas rubuta latency.
• tZQ: Lokacin daidaitawa ZQ.
• tRFC: Lokacin Zagayowar Layi
• tWTR: Rubutu zuwa jinkiri. Rubutun ciniki na ƙarshe zuwa lokacin karanta umarni.
• tWR: Rubuta lokacin farfadowa. Rubutun ciniki na ƙarshe zuwa lokacin caji

Lokaci na duk sigogin da aka lissafa ya dogara da nau'in ƙwaƙwalwar ajiya da aka yi amfani da ita da matakin saurin ɓangaren ƙwaƙwalwar ajiya.
Ana iya samun ƙarin cikakkun bayanai kan ma'anoni da ƙayyadaddun lokaci a cikin DDR2 DDR3 JEDEC ko a kowace takaddar bayanan na'urar ƙwaƙwalwar ajiya.

Ingancin ya dogara da yadda ake samun damar ƙwaƙwalwar ajiya. Hanyoyin adireshi daban-daban suna ba da sakamako daban-daban na inganci.

Yawan lokacin ƙwaƙwalwar ajiya

1. Lokacin kunnawa da lokacin caji lokacin canzawa zuwa sababbin bankuna/layi ko canza layuka tare da banki ɗaya.- Don haka idan kun rage canjin layi, wannan na iya cire tRCD da tRP.
2. Aika ci gaba da rubuta ko karanta umarni -Kiyayyar tCCD lokaci.
3. Rage rubuce-rubuce don karantawa da karantawa don rubuta canjin umarni - Rubuta lokacin dawowa don canzawa zuwa karanta abubuwan shiga, lokacin juyawa bas don canzawa daga karatu zuwa rubutu
4. Saita madaidaicin tazarar wartsakewa.
   • DDR3 SDRAM yana buƙatar sake sake zagayowar a matsakaicin lokaci na tREFI.
   • Ana iya ba da iyakar ƙarin umarni 8 na wartsakewa a gaba ("an jawo ciki"). Wannan baya rage adadin wartsakewa, amma matsakaicin tazara tsakanin umarnin wartsakewa guda biyu yana iyakance zuwa 9 × tREFI

• Yi amfani da duk bankunan - Hanyar magance da ta dace ya fi dacewa.
  • Rukunin-Banki-Layi: Don ma'amala da ke faruwa akan sararin adireshi na jeri, ainihin yana buɗe layi ɗaya ta atomatik a cikin banki na gaba na na'urar DRAM don ci gaba da ciniki lokacin da aka kai ƙarshen layin da ke akwai. Ya dace da aikace-aikacen da ke buƙatar fashe manyan fakitin bayanai zuwa wuraren adireshi na jere.
  • Rukunin Banki-Row-Shafin: Lokacin ƙetare kan iyaka, za a rufe layin na yanzu kuma za a buɗe wani layi a cikin banki ɗaya. MSB adireshin banki ne, wanda za'a iya amfani dashi don canzawa daga bankuna daban-daban. Ya dace da gajarta, ƙarin ma'amaloli na bazuwar zuwa toshe ɗaya na ƙwaƙwalwar ajiya na ɗan lokaci sannan tsalle zuwa wani toshe (banki)
• Tsawon Fashewa
  • Ana tallafawa BL 8 don DDR3 akan jerin 7. BC4 yana da ƙarancin inganci wanda bai wuce 50% ba. Wannan saboda lokacin aiwatar da BC4 daidai yake da BL8. An rufe bayanan kawai a cikin sashin.
  • A lokuta da ba kwa son rubuta cikakken fashe, ko dai abin rufe fuska na bayanai ko rubuta bayan karantawa ana iya la'akari da shi.
• Saita tazarar ZQ da ta dace (DDR3 Kawai)
  Mai sarrafawa yana aika duka ZQ Short (ZQCS) da ZQ Long (ZQCL) umarni calibration.
  • Rike da DDR3 Jedec Standard
  • Ana tattauna Calibration na ZQ a cikin sashe na 5.5 na JEDEC Spec JESD79-3 DDR3 SDRAM Standard
  • ZQ Calibration calibration On Die Termination (ODT) a tazara na yau da kullun don lissafin bambance-bambance a cikin VT
  • Hankali yana kunshe a cikin bank_common.v/vhd
  • Parameter Tzqcs yana ƙayyade ƙimar da aka aika umarni Calibration na ZQ zuwa ƙwaƙwalwar ajiya
  • t yana yiwuwa a kashe counter kuma aika da hannu ta amfani da app_zq_req, yayi kama da aika Refresh da hannu.
    Koma zuwa (Amsar Xilinx 47924) don cikakkun bayanai.

Mai Sarrafa Sama

1. Karatun lokaci-lokaci - Koma zuwa (Amsar Xilinx 43344) don cikakkun bayanai.
   • Kar a canza lokacin karatun
   • Tsallake karatun lokaci-lokaci yayin rubuce-rubuce kuma fitar da adadin waɗanda aka rasa kafin karatun gaskiya
2. Sake oda - Komawa (Amsar Xilinx 34392) don cikakkun bayanai.
   Don ƙirar mai amfani da AXI Interface yana da kyau a kunna wannan.
   • Sake yin oda shine ma'anar da ke kallon gaba da umarni da yawa kuma yana canza umarnin mai amfani don yin umarnin da ba na ƙwaƙwalwar ajiya ba ya mamaye ingantaccen bandwidth. Hakanan aikin yana da alaƙa da ainihin tsarin zirga-zirga.
   • Dangane da tsarin adireshi, sake tsarawa yana taimakawa wajen tsallake precharge da kunna umarni kuma yana sanya tRCD da tRP ba su mamaye fadin band ɗin bayanai ba.
3. Yi ƙoƙarin ƙara yawan Injin Banki.
   • Yawancin dabaru na mai sarrafawa suna zaune a cikin injinan banki kuma sun dace da bankunan DRAM
   • Injin banki da aka bayar yana sarrafa bankin DRAM guda ɗaya a kowane lokaci.
   • Aikin injin banki yana da ƙarfi don haka ba lallai ba ne a sami injin banki ga kowane banki na zahiri.
   • Ana iya daidaita injinan banki, amma ciniki ne tsakanin yanki da aiki.
   • Adadin da aka halatta na injinan banki daga 2-8.
   • Ta hanyar tsoho, ana saita Injin Banki 4 ta hanyar sigogi na RTL.
   • Don canza Injinan Banki, la'akari da siga nBANK_MACHS = 8 da ke cikin memc_ui_top Example don Injin Banki 8 - nBANK_MACHS = 8

Yanzu kun san abubuwan da ke tasiri aiki.
Yi la'akari da aikace-aikacen da ke sama wanda ke ba ku bayanan bayanan 512 a kowane fakiti kuma kuna buƙatar adana su zuwa wuraren ƙwaƙwalwar ajiya daban-daban. Kamar yadda bayanan bayanan 512 daidai yake da fashewar bayanan DDR64 3, sake gudanar da tsohonample zane tare da kara kuzari file dauke da 512 ya rubuta, 512 karantawa da jujjuya layi ga kowane 64 ya rubuta ko karanta:

• 3f_0_0_0000_000_0
• 3f_0_0_0001_000_0
• 3f_0_0_0002_000_0
• 3f_0_0_0003_000_0
• 3f_0_0_0004_000_0
• 3f_0_0_0005_000_0
• 3f_0_0_0006_000_0
• 3f_0_0_0007_000_0
• 3f_0_0_0000_000_1
• 3f_0_0_0001_000_1
• 3f_0_0_0002_000_1
• 3f_0_0_0003_000_1
• 3f_0_0_0004_000_1
• 3f_0_0_0005_000_1
• 3f_0_0_0006_000_1
• 3f_0_0_0007_000_1

A ƙarshen simulation za ku ga cewa amfani da bas yana kan kashi 77 cikin ɗari.

Hoto na 11: Kididdigar Ayyuka na 512 ya rubuta kuma 512 ya karanta - Canjin layi don 64 ya rubuta ko karantawa. 

Yanzu zaku iya amfani da ilimin da aka koya a sashin da ya gabata don inganta ingantaccen aiki. Da a view don amfani da duk bankunan maimakon canza layi, gyara tsarin adireshin don canza bankin kamar yadda aka nuna a ƙasa.
Wannan yayi daidai da saita ROW_BANK_Column a cikin saitin taswirar adireshin adreshin a cikin MIG GUI.

• 3f_0_0_0000_000_0
• 3f_0_1_0000_000_0
• 3f_0_2_0000_000_0
• 3f_0_3_0000_000_0
• 3f_0_4_0000_000_0
• 3f_0_5_0000_000_0
• 3f_0_6_0000_000_0
• 3f_0_7_0000_000_0
• 3f_0_0_0000_000_1
• 3f_0_1_0000_000_1
• 3f_0_2_0000_000_1
• 3f_0_3_0000_000_1
• 3f_0_4_0000_000_1
• 3f_0_5_0000_000_1
• 3f_0_6_0000_000_1
• 3f_0_7_0000_000_1

A ƙarshen simulation za ku ga cewa a baya kashi 77 na Amfani da Bus yanzu ya zama 87!

Idan har yanzu kuna buƙatar aiki mafi girma, zaku iya zuwa don manyan fakiti masu girma dabam na 1024 ko 2048 bytes, ko la'akari da sabuntawar hannu.

Lura: Xilinx baya ƙarfafa ƙetare wartsakewar mai sarrafawa kamar yadda ba mu da tabbas idan za ku iya saduwa da Jedec auto refresh timeing wanda ke shafar amincin bayanai.
Daga bangaren mai sarrafawa zaku iya canza nBANk_MACH kuma ku ga ingantaccen aiki.
Koyaya, wannan na iya shafar lokacin ƙirar ku, da fatan za a duba (Amsar Xilinx 36505) don cikakkun bayanai akan nBANk_MACH

Bude core_name_mig_sim.v file kuma canza sigogin nBANK_MACHS daga 4 zuwa 8 sannan a sake kunna simulation. Don samun tasirin siga a cikin hardware, kuna buƙatar sabunta core_name_mig.v file.
Na yi amfani da wannan tsari inda muka sami 87% amfani da bas (hoto -12).
Tare da nBANK_MACHS saita zuwa 8, ingancin aiki yanzu shine 90%.

Hakanan yi bayanin kula cewa ½ da ¼ masu sarrafawa suna yin tasiri mara kyau saboda latency ɗin su.
Don misaliampDon haka, tun da kawai za mu iya aika umarni kowane zagayowar CK 4 kawai akwai wasu lokuta ƙarin fakiti yayin bin ƙayyadaddun ƙayyadaddun ƙayyadaddun lokaci na DRAM, wanda zai iya rage inganci daga ka'idar.
Gwada masu sarrafawa daban-daban don nemo wanda ya dace da buƙatun aikin ku.

Magana

1. Zynq-7000 AP SoC da 7 Series FPGAs MIS v2.3 [UG586]
2. Xilinx MIG Solution Center http://www.xilinx.com/support/answers/34243.html

Tarihin Bita
13/03/2015 - Farkon fitarwa

Sauke PDF: Xilinx DDR2 MIG 7 Jagoran Ƙimar Ayyuka

Magana

• Manual mai amfani