intel UG-20093 ModelSim FPGA lomiga Fa'ata'ita'iga

ModelSim* – Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition

O lenei pepa o loʻo faʻaalia ai le faʻaogaina o se Intel® Quartus® Prime Pro Edition design i le ModelSim* - Intel FPGA Edition simulator. Fuafuaga fa'ata'ita'iga e fa'amaonia lau mamanu a'o le'i fa'apolokalameina masini. O le polokalama Intel Quartus Prime e fa'atupu fa'atusa files mo simulators EDA lagolagoina i le taimi o le tuufaatasia o mamanu.
Ata 1. ModelSim - Intel FPGA Edition

Fa'ata'ita'iga fa'atusa e aofia ai le fa'atupuina o fa'ata'ita'iga files, tuufaatasia faʻataʻitaʻiga faʻataʻitaʻiga, faʻatautaia le faʻataʻitaʻiga, ma viewi'uga. O laasaga nei e faʻamatalaina ai lenei tafe:

1. Tatala le Example Design i le itulau e 4
2. Fa'ailoa Fa'atonuga Meafaigaluega EDA ile itulau 4
3. Fausia se Fa'ata'ita'iga Fa'atonu Fa'atonu Fa'ata'ita'i ile itulau 5
4. Suia le Simulator Setup Script i le itulau 6
5. Tuufaatasi ma Faata'ita'i le Fuafuaga i le itulau e 8
6. View Fa'ailoga Fa'ailoga i le itulau 9
7. Fa'aopoopo Fa'ailoga ile Fa'ata'ita'iga ile itulau 11
8. Toe fai Simulation ile itulau 12
9. Suia le Simulation Testbench i le itulau 12

Tatala le Example Lisiina

O le PLL_RAM example mamanu e aofia ai le Intel FPGA IP cores e faʻaalia ai le tafe faʻataʻitaʻiga masani. La'u mai le example mamanu files ma tatala le poloketi i le polokalama Intel Quartus Prime.
Fa'aaliga: O lenei Quick-Start e manaʻomia ai se malamalamaga masani o le faʻamatalaga gagana faʻapipiʻi ma le Intel Quartus Prime design flow, e pei ona faamatalaina e le Intel Quartus Prime Pro Edition Foundation Online Training.

1. La'u mai ma tatala le sipuni le Quartus_Pro_PLL_RAM.zip mamanu example.
2. Tatala le Intel Quartus Prime Pro Edition software version 19.4 pe mulimuli ane.
3. E tatala le example mamanu poloketi, kiliki File ➤ Tatala Poloketi, filifili le pll_ram.qpf poloketi file, ona kiliki lea o le OK.

Ata 2. pll_ram Poloketi i le Intel Quartus Prime Pro Edition

Fa'ailoa Fa'atonuga Meafaigaluega EDA

Fa'ailoa fa'atonuga meafaigaluega a le EDA e fa'atupu fa'ata'ita'iga files mo simulators lagolagoina.

1. I le polokalama Intel Quartus Prime, kiliki Tofiga ➤ Seti ➤ EDA Tool Settings.
2. I lalo o le Simulation, filifili ModelSim-Intel FPGA o le igoa Meafaigaluega. Taofi le tulaga e le masani ai mo le Fa'asologa mo le lisi o upegatafa'ilagi ma le fa'atonuga.

Fausia se Fa'ata'ita'iga Fa'atonu Fa'asologa o Simulator

E fesoasoani le faʻatulagaina o faʻataʻitaʻiga ia oe e faʻataʻitaʻiina le IP cores i lau mamanu. Mulimuli i laasaga nei e fa'atupu ai le fa'ata'ita'iga fa'ata'ita'iga fa'atulagaina simulator fa'apitoa mo fa'aoga IP i le example mamanu. E mafai ona e fa'avasegaina lenei fa'ata'ita'iga mo au sini fa'atusa fa'apitoa.

1. Ina ia tuufaatasia le mamanu, kiliki Processing ➤ Start Compilation. O le fa'amalama o Savali e fa'ailoa mai pe a mae'a le tu'ufa'atasiga.
2. Kiliki Meafaigaluega ➤ Fa'atupu Fa'amatalaga Setup Simulator mo IP. Taofi le fa'atonuga o Fa'amatalaga Fa'atino ma Fa'aaoga ala feso'ota'i i so'o se taimi e mafai ai fa'atulaga mo le fa'asologa o tusitusiga file. O le fa'ata'ita'iga fa'asologa fa'atulagaina e fa'atupu i totonu o le fa'atonuga e te fa'ailoaina.

Ata 3. Fausia Tusi Fa'atonu Simulator Pusa Talanoaga IP

Suia le Fa'amatalaga Setup Simulator

Suia le faʻatulagaina o le simulator faʻatulagaina tusitusiga ina ia mafai ai ona faʻatonu tulafono faʻapitoa e faʻataʻitaʻiina ai le IP i totonu o le poloketi.

1. I totonu o se tusitala o tusitusiga, tatala le /PLL_RAM/mentor/msim_setup.tcl file.
2. Fausia se tusitusiga fou file ma le igoa mentor_example.do ma teu i le /PLL_RAM/mentor/ directory.
3. I le msim_setup.tcl file, kopi le vaega o le code o lo'o fa'apipi'iina i totonu o le TOP-LEVEL TEMPLATE – BEGIN ma TOP-LEVEL TEMPLATE – END fa'amatalaga, ona faapipii lea o le code lea i totonu ole mentor_ex fou.ample.do file.
4. I le mentor_example.do file, tape le pauna e tasi (#) mataitusi o loʻo muamua atu i laina faʻailoga nei e mafai ai ona tuʻufaʻatasia tulafono:

Ata 4. Fa'ailoga Fa'ailoga Poloaiga Fa'ata'ita'i i totonu o le Fa'amatalaga

1. Sui laina nei ile mentor_example.do tusitusiga:

Laulau 1. Fa'ailoa Tulaga Taua ile mentor_example.do Tusitusiga

Sui lenei Laina	Faatasi ai ma lenei Laina
seti QSYS_SIMDIR	../
vlog files>	vlog -vlog01compat -galuega galuega ../PLL_RAM.v vlog -vlog01compat -galuega galue ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -galuega galuega ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -galuega galuega ../ClockPLL/ClockPLL.v vlog -vlog01compat -galuega galue ../RAMhub/RAMhub.v vlog -vlog01compat -galuega galuega ../testbench_1.v
seti TOP_LEVEL_NAME	seti TOP_LEVEL_NAME tb
tamoe -a	faaopoopo galu* view fausaga view fa'ailoga tamo'e -uma

1. Faasaoina le /PLL_RAM/mentor/mentor_example.do file. O le ata o loʻo i lalo o loʻo faʻaalia ai le mentor_example.do file a mae'a toe iloiloga:

Ata 5. Fa'amae'a le Tulaga Tulaga Maualuga IP Simulation Setup Script

Tuufaatasi ma Fa'ata'ita'i le Fuafuaga

Faʻaauau le tulaga maualuga mentor_example.do tusitusiga i le ModelSim - Intel FPGA Edition polokalama e tuufaatasia ma faʻatusa lau mamanu.

1. Tatala le ModelSim - Intel FPGA Edition software. O le ModelSim - Intel FPGA Edition GUI faʻatulagaina elemene o lau faʻataʻitaʻiga i ni faʻamalama eseese ma faʻamau.
2. Mai le lisi o poloketi PLL_RAM, tatala le testbench_1.v file. Faʻapea foʻi, tatala le mentor/mentor_example.do file.
3. Ina ia faʻaalia le faamalama Transcript, kiliki View ➤ Tusitusi. E mafai ona e ulufale sa'o i totonu o le fa'amalama Transcript.
4. Faʻapipiʻi le faʻatonuga o loʻo i lalo i le faʻamalama Transcript ona lolomi lea Ulufale: fai mentor_example.do

O le mamanu faʻapipiʻi ma faʻataʻitaʻiina, e tusa ai ma au faʻamatalaga i le mentor_example.leai se tusitusiga. O le ata o loʻo i lalo o loʻo faʻaalia ai le ModelSim - Intel FPGA Edition simulator:

Ata 6. ModelSim - Intel FPGA Edition GUI

View Fa'ailoga Galue

Mulimuli i laasaga nei e view fa'ailoga i le testbench_1.v fa'ata'ita'iga galu:

1. Kiliki le faamalama Wave. O le faʻataʻitaʻiga faʻataʻitaʻiga e muta i le 11030 ns, e pei ona faʻamaonia mai e le testbench. Ole fa'amalama ole Wave o lo'o lisiina ai fa'ailoga uati, WE, OFFSET, RESET_N, ma RD_DATA.

Ata 7. ModelSim - Intel FPGA Edition Wave Window

1. I view o faailo i le pito i luga pll_ram.v mamanu, kiliki le Sim tab. O le fa'amalama Sim e fa'atasi ma le fa'amalama o Mea.

Ata 8. ModelSim – Intel FPGA Edition Sim ma Objects Pupuni

1. I view fa'ailoga module pito i luga, fa'alautele le faila tb i le fa'ailoga Mea. Faʻapena foʻi, faʻalautele le pusa Test1. O le fa'amalama o Mea e fa'aalia ai fa'ailoga UP_module, DOWN_module, PLL_module, ma le RAM_module.
2. I le faamalama Sim, kiliki se module i lalo o le Test1 e faʻaalia ai faʻailoga a le module i le faʻamalama o Mea.
3. View le faletusi fa'ata'ita'i files i le faamalama o le Faletusi.

Ata 9. ModelSim - Intel FPGA Edition Library Window

Fa'aopoopo Fa'ailoga i le Fa'ata'ita'iga

O le CLOCK, WE, OFFSET, RESET_N, ma le RD_DATA faʻailoga e otometi lava ona aliali i le Wave window aua o le faʻailoga pito i luga o loʻo faʻamalamalamaina ai nei I/O. E le gata i lea, e mafai ona e faʻaopoopoina faʻailoga i totonu i le simulation.

1. I le Objects window, su'e le UP_module, DOWN_module, PLL_module, ma le RAM_module modules.
2. I le faamalama Objects, filifili RAM_module. O mea fa'aoga ma fa'atinoga o le module
3. fa'aaliga.

Ata 10. Fa'aopoopo Fa'ailoga I Fa'amalama Galu

1. Ina ia faʻaopoopo faʻailoga i totonu i le va o le pito i lalo ma le lua-taulaga RAM module, kiliki-saʻo rdaddress ona kiliki ai lea o le Add Wave.
2. Ina ia fa'aopoopo fa'ailoga fa'alotoifale i le va o le pito i luga ma le lua-taulaga RAM module, kiliki-sa'o le wraddress ona kiliki lea o le Add Wave. I le isi itu, e mafai ona e tosoina ma tu'u i lalo nei fa'ailoga mai le fa'amalama Objects i le fa'amalama Wave.
3. Ina ia fa'atupu le galu mo fa'ailoga fou e te fa'aopoopoina, kiliki le Simulate ➤ Run ➤ Continue.

Toe fai Simulation

E tatau ona e toe faʻafoʻi le faʻataʻitaʻiga pe a fai e te faia ni suiga i le seti faʻataʻitaʻiga, e pei o le faʻaopoopoina o faʻailoga i le Wave window, poʻo le suia o le testbench_1.v file. Mulimuli i laasaga nei e toe faʻatautaia ai le faʻataʻitaʻiga:

1. I le ModelSim - Intel FPGA Edition simulator, kiliki Simulate ➤ Toe amata. Taofi le mea e le mafai ona fai ma kiliki le OK. O nei filifiliga e faʻamama ai le galu ma toe amata le taimi faʻataʻitaʻiga, aʻo faʻatumauina faailoilo talafeagai ma faʻatulagaga.
   Fa'aaliga: I le isi itu, e mafai ona e toe taʻavale le /PLL_RAM/mentor/mentor_example.do script e toe faʻataʻitaʻi faʻataʻitaʻiga i le laina o le poloaiga.
2. Kiliki Simulate ➤ Run ➤ Run -all. O le testbench_1.v file fa'atusa e tusa ai ma fa'amatalaga fa'ata'ita'iga. Ina ia faʻaauau le faʻataʻitaʻiga, kiliki Simulate ➤ Run ➤ Faʻaauau. O lenei poloaiga e faʻaauauina le faʻataʻitaʻiga seʻia e kiliki le taofi taofi.

Suia le Simulation Testbench

O le testbench_1.v exampe su'e e le testbench na'o se seti ma'oti o tulaga ma fa'ata'ita'iga. E mafai ona e fa'asa'o lima le testbench_1.v file i le ModelSim - Intel FPGA Edition simulator e suʻe ai isi mataupu ma tulaga:

1. Tatala le testbench_1.v file i le ModelSim - Intel FPGA Edition simulator.
2. Kiliki taumatau i le testbench_1.v file e faamaonia ai o le file e le o setiina i le Na'o Faitau.
3. Ulufale ma teu so'o se fa'ailoga fa'aopoopo i le testbench_1.v file.
4. Ina ia fa'atupu le galu mo se laulau su'esu'e e te suia, kiliki le Fa'atusa ➤ Toe amata.
5. Kiliki Simulate ➤ Run ➤ Run -all.

ModelSim – Intel FPGA Edition Simulation Vave-Amata Toe Iloilo Talafaasolopito

Fa'amatalaga Fa'amaumauga	Intel Quartus Prime Version	Suiga
2019.12.30	19.4	• Fa'afouina laasaga ma fa'amalama mo le Intel Quartus Prime Pro Edition version 19.4. • Fa'afouga mamanu example file so'oga ma anotusi.
2018.09.25	18.0	Fa'asa'o fa'asologa o mea sese ile mentor_example.do Tusitusiga.
2018.05.07	18.0	Ave'ese la'asaga le mana'omia mai Faʻataʻitaʻi faʻataʻitaʻiga ile Laina Poloaiga taualumaga.
2017.07.15	17.1	Fa'asalalauga muamua.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.

• O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Pepa / Punaoa

intel UG-20093 ModelSim FPGA lomiga Fa'ata'ita'iga [pdf] Taiala mo Tagata Fa'aoga UG-20093 Fa'ata'ita'iga Fa'ata'ita'iga FPGA Fa'ata'ita'iga, UG-20093, Fa'ata'ita'iga Fa'ata'ita'iga Fa'ata'ita'iga Fa'ata'ita'iga FPGA Fa'ata'ita'iga, Fa'ata'ita'iga Fa'ata'ita'iga Fa'ata'ita'iga FPGA, Fa'ata'ita'iga Fa'asologa

Fa'asinomaga

• Tusi Taiala