Intel UG-20093 ModelSim FPGA Khatiso ea Ketsiso

ModelSim* – Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition

Tokomane ena e bonts'a mokhoa oa ho etsisa moralo oa Intel® Quartus® Prime Pro Edition ho ModelSim* - simulator ea Intel FPGA Edition. Papiso ea moralo e netefatsa moralo oa hau pele ho mananeo a sesebelisoa. Software ea Intel Quartus Prime e hlahisa papiso files bakeng sa li-simulator tsa EDA tse tšehelitsoeng nakong ea ho hlophisoa ha moralo.
Setšoantšo sa 1. ModelSim - Intel FPGA Edition

Ketsiso ea moralo e kenyelletsa ho hlahisa ketsiso files, ho bokella mehlala ea ketsiso, ho tsamaisa ketsiso, le viewka liphetho. Mehato e latelang e hlalosa phallo ena:

1. Bula Example Design leqepheng la 4
2. Hlalosa Litlhophiso tsa Sesebelisoa sa EDA leqepheng la 4
3. Hlahisa Sebopeho sa Sengoloa sa Simulator Setup leqepheng la 5
4. Fetola Sengoloa sa Setupo sa Simulator leqepheng la 6
5. Kopanya le ho Etsisa Moralo leqepheng la 8
6. View Maqhubu a Pontšo leqepheng la 9
7. Kenya Lipontšo ho Ketsiso e leqepheng la 11
8. Phetha Papiso leqepheng la 12
9. Fetola Simulation Testbench leqepheng la 12

Bula Example Design

PLL_RAM example moralo o kenyelletsa li-cores tsa Intel FPGA IP ho bonts'a phallo ea mantlha ea papiso. Kopitsa example moralo files le ho bula projeke ho software ea Intel Quartus Prime.
Hlokomela: Ho Qala ka Potlako ho hloka kutloisiso ea mantlha ea syntax ea puo ea tlhaloso ea hardware le phallo ea moralo oa Intel Quartus Prime, joalo ka ha Intel Quartus Prime Pro Edition Foundation Online Training e hlalosa.

1. Khoasolla le ho notlolla moralo oa Quartus_Pro_PLL_RAM.zip example.
2. Qala mofuta oa software oa Intel Quartus Prime Pro Edition 19.4 kapa hamorao.
3. Ho bula example morero oa moralo, tobetsa File ➤ Open Project, khetha morero oa pll_ram.qpf file, ebe o tobetsa OK.

Setšoantšo sa 2. pll_ram Project ho Intel Quartus Prime Pro Edition

Hlalosa Litlhophiso tsa Sesebelisoa sa EDA

Hlalosa litlhophiso tsa lisebelisoa tsa EDA ho hlahisa papiso files bakeng sa li-simulator tse tšehetsoeng.

1. Ho software ea Intel Quartus Prime, tobetsa Mosebetsi ➤ Litlhophiso ➤ Lisebelisoa tsa EDA.
2. Tlas'a Simulation, khetha ModelSim-Intel FPGA e le Lebitso la Tool. Boloka li-setting tsa kamehla tsa Format bakeng sa netlist le Output directory.

Hlahisa Sebopeho sa Sengoloa sa ho Seta sa Simulator

Lingoliloeng tsa ho seta simulator li u thusa ho etsisa li-cores tsa IP moralong oa hau. Latela mehato ena ho hlahisa template e ikhethileng ea morekisi bakeng sa li-module tsa IP ho ex.ample moralo. Joale o ka etsa template ena ka mokhoa o ikhethileng bakeng sa lipheo tsa hau tse ikhethang tsa papiso.

1. Ho hlophisa moralo, tobetsa Ho sebetsa ➤ Qala ho Kopanya. Fesetere ea Melaetsa e bontša ha pokello e felile.
2. Tobetsa Lisebelisoa ➤ Hlahisa Sengoloa sa Setupo sa Simulator bakeng sa IP. Boloka lethathamo la kamehla la Output 'me U sebelise litsela tse lekanyelitsoeng neng kapa neng ha ho khonahala ho seta bakeng sa script ea ho seta file. Template ea setup script e hlahisa bukeng eo u e boletseng.

Setšoantšo sa 3. Hlahisa Lebokose la Lipuisano tsa IP tsa Setupo sa Simulator

Fetola Sengoloa sa Setupo sa Simulator

Fetola sengoloa sa ho seta sa simulator ho fana ka litaelo tse ikhethileng tse etsisang li-cores tsa IP morerong.

1. Ho sehlophisi sa mongolo, bula faele ea /PLL_RAM/mentor/msim_setup.tcl file.
2. Theha mongolo o mocha file ka lebitso mentor_example.do 'me u e boloke ho /PLL_RAM/mentor/ directory.
3. Ho msim_setup.tcl file, kopitsa karolo ea khoutu e kentsoeng ka har'a TOP-LEVEL TEMPLATE - BEGIN le TOP-LEVEL TEMPLATE - QETELA maikutlo, ebe u beha khoutu ena ho mentor_ex e ncha.ample.etsa file.
4. Ho mentor_example.etsa file, hlakola litlhaku tsa ponto e le 'ngoe (#) ka pele ho mela e latelang e totobalitsoeng ho nolofalletsa litaelo tsa ho bokella:

Setšoantšo sa 4. Uncomment e Totobalitse Litaelo tsa Ketsiso ho Script

1. Fetola mela e latelang ho mentor_exampscript ea le.do:

Letlapa la 1. Hlalosa Melao-motheo ho mentor_exampLe.do Script

Fetola Line ena	Ka Line ena
beha QSYS_SIMDIR	../
vlog files>	vlog -vlog01compat -work work ../PLL_RAM.v vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v vlog -vlog01compat -work work ../RAMhub/RAMhub.v vlog -vlog01compat -work work ../testbench_1.v
beha TOP_LEVEL_NAME	beha TOP_LEVEL_NAME tb
matha -a	eketsa leqhubu * view sebopeho view lipontšo matha -ohle

1. Boloka faele ea /PLL_RAM/mentor/mentor_example.etsa file. Setšoantšo se latelang se bontša moeletsi_example.etsa file ka mor'a hore liphetoho li phetheloe:

Setšoantšo sa 5. E phethiloe Sengoloa sa Setupo sa Boemo bo Phahameng ba IP Simulation

Kopanya le ho Etsisa Moralo

Matha moeletsi oa boemo bo holimoample.do ho software ea ModelSim - Intel FPGA Edition ho bokella le ho etsisa moralo oa hau.

1. Qala software ea ModelSim - Intel FPGA Edition. ModelSim - Intel FPGA Edition GUI e hlophisa likarolo tsa papiso ea hau ka lifensetere le li-tab tse arohaneng.
2. Ho tsoa bukeng ea projeke ea PLL_RAM, bula testbench_1.v file. Ka mokhoa o ts'oanang, bula moeletsi/mentor_example.etsa file.
3. Ho hlahisa fensetere ea Transcript, tobetsa View ➤ Sengoliloeng. U ka kenya litaelo tsa ModelSim - Intel FPGA Edition ka kotloloho fensetereng ea Transcript.
4. Tlanya taelo e latelang fensetereng ea Transcript ebe o tobetsa Enter: etsa mentor_example.etsa

Moralo oa bokella le ho etsisa, ho latela litlhaloso tsa hau ho mentor_example.ha ho mongolo. Setšoantšo se latelang se bontša simulator ea ModelSim - Intel FPGA Edition:

Setšoantšo sa 6. ModelSim - Intel FPGA Edition GUI

View Lipontšo tsa Waveforms

Latela mehato ena ho view lipontšo ka har'a testbench_1.v simulation waveform:

1. Tobetsa fensetere ea Wave. Sebopeho sa wave wave se qetella ho 11030 ns, joalo ka ha testbench e bolela. Fesetere ea Wave e thathamisa matšoao a CLOCK, WE, OFFSET, RESET_N, le RD_DATA.

Setšoantšo sa 7. ModelSim - Intel FPGA Edition Wave Window

1. Ho view matšoao a moralo oa boemo bo holimo pll_ram.v, tobetsa konopo ea Sim. Fesetere ea Sim e amahanya le fensetere ea Lintho.

Setšoantšo sa 8. ModelSim - Intel FPGA Edition Sim le Objects Windows

1. Ho view matshwao a mojule wa boemo bo hodimo, eketsa foldara ya tb ho tab ya Objects. Ka mokhoa o ts'oanang, eketsa foldara ea Test1. Fesetere ea Lintho e bonts'a UP_module, DOWN_module, PLL_module, le matšoao a RAM_module.
2. Fesetereng ea Sim, tobetsa mojule tlas'a Test1 ho hlahisa matšoao a module fensetereng ea Lintho.
3. View laebrari ea ketsiso files fensetereng ea Library.

Setšoantšo sa 9. ModelSim - Intel FPGA Edition Library Window

Eketsa Lipontšo ho Simulation

Lits'oants'o tsa CLOCK, WE, OFFSET, RESET_N, le RD_DATA li iponahatsa fensetereng ea Wave hobane moralo oa boemo bo holimo o hlalosa I/O tsena. Ho phaella moo, u ka khetha ho eketsa matšoao a ka hare ho papiso.

1. Ka fensetere ea Lintho, fumana UP_module, DOWN_module, PLL_module, le RAM_module.
2. Ka fensetere ea Lintho, khetha RAM_module. Lintho tse kenang le tse hlahisoang ke mojule ke
3. pontsho.

Setšoantšo sa 10. Eketsa Lipontšo ho Fensetere ea Wave

1. Ho kenyelletsa mats'oao a kahare lipakeng tsa mojule oa "down-counter" le "dual-port RAM", tobetsa ka ho le letona rdaddress ebe o tobetsa Add Wave.
2. Ho kenyelletsa mats'oao a kahare lipakeng tsa mojule oa holimo-le-port-port ea RAM, tobetsa ka ho le letona wraddress ebe o tobetsa Add Wave. Ntle le moo, o ka hula le ho theola matšoao ana ho tloha fensetereng ea Lintho ho ea fensetereng ea Wave.
3. Ho hlahisa mefuta ea maqhubu bakeng sa matshwao a matjha ao o a kenyang, tobetsa Etsisa ➤ Matha ➤ Tswelapele.

Tsamaisa Ketsiso hape

U tlameha ho khutlisetsa papiso haeba u etsa liphetoho ho seta sa ketsiso, joalo ka ho eketsa matšoao ho fensetere ea Wave, kapa ho fetola testbench_1.v file. Latela mehato ena ho etsa ketsiso hape:

1. Ho simulator ea ModelSim - Intel FPGA Edition, tobetsa Etsisa ➤ Qala hape. Boloka likhetho tsa kamehla ebe o tobetsa OK. Likhetho tsena li hlakola li-waveforms le ho qala nako ea papiso, ha u ntse u boloka matšoao le litlhophiso tse hlokahalang.
   Hlokomela: Ntle le moo, o ka sebelisa hape /PLL_RAM/mentor/mentor_example.do script ho etsa ketsiso hape moleng oa taelo.
2. Tobetsa Etsisa ➤ Matha ➤ Matha -kaofela. The testbench_1.v file e etsisa ho latela litlhaloso tsa testbench. Ho tsoela pele ka papiso, tobetsa Etsisa ➤ Matha ➤ Tsoela Pele. Taelo ena e tsoela pele ketsiso ho fihlela o tobetsa konopo ea Emisa.

Fetola Simulation Testbench

The testbench_1.v example testbench e leka feela sete e itseng ea maemo le linyeoe tsa liteko. U ka fetola testbench_1.v file ho ModelSim - Intel FPGA Edition simulator ho leka linyeoe le maemo a mang:

1. Bula testbench_1.v file ho simulator ea ModelSim - Intel FPGA Edition.
2. Tobetsa ka ho le letona ho testbench_1.v file ho tiisa hore the file ha ea beoa ho Bala Feela.
3. Kenya 'me u boloke li-parameter life kapa life tse ling tsa testbench ho testbench_1.v file.
4. Ho hlahisa li-waveforms bakeng sa testbench eo u e fetolang, tobetsa Etsisa ➤ Qala hape.
5. Tobetsa Etsisa ➤ Matha ➤ Matha -kaofela.

ModelSim – Intel FPGA Edition Simulation Quick-Start Revision History

Tokomane Version	Intel Quartus Prime Version	Liphetoho
2019.12.30	19.4	• Mehato e ntlafalitsoeng le li-skrini tsa Intel Quartus Prime Pro Edition 19.4. • Moetso o ntlafalitsoeng mohlalaample file sehokelo le dikahare.
2018.09.25	18.0	Liphoso tse lokisitsoeng tsa syntax ho mentor_exampLe.do Script.
2018.05.07	18.0	E tlositsoe mohato o sa hlokahaleng ho Matha Simulation ka Command Line mokhoa.
2017.07.15	17.1	Tokollo ea pele.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso.

• Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

Litokomane / Lisebelisoa

Intel UG-20093 ModelSim FPGA Khatiso ea Ketsiso [pdf] Bukana ea Mosebelisi UG-20093 ModelSim FPGA Edition Simulation, UG-20093, ModelSim FPGA Edition Simulation, FPGA Edition Simulation, Ketsiso ea Khatiso

Litšupiso

• Bukana ea Mosebelisi