Intel UG-20093 ModelSim FPGA Edition Simulation

ModelSim* – Intel® FPGA Edition Simulation Quick-Start Intel® Quartus® Prime Pro Edition

Chikalatachi chikuwonetsa momwe mungatengere kamangidwe ka Intel® Quartus® Prime Pro Edition mu ModelSim* - Intel FPGA Edition simulator. Kayeseleledwe ka mapangidwe amatsimikizira kapangidwe kanu musanakonzere chipangizo. Pulogalamu ya Intel Quartus Prime imapanga zoyerekeza files kwa zoyeserera za EDA zothandizidwa panthawi yopanga mapangidwe.
Chithunzi 1. ModelSim - Intel FPGA Edition

Kuyerekezera kwapangidwe kumaphatikizapo kupanga kayeseleledwe files, kupanga zitsanzo zoyeserera, kuyendetsa kayeseleledwe, ndi viewndi zotsatira. Njira zotsatirazi zikufotokozera kuyenda uku:

1. Tsegulani Example Design patsamba 4
2. Nenani Zokonda pa Chida cha EDA patsamba 4
3. Pangani template ya Simulator Setup Script patsamba 5
4. Sinthani Setup Script ya Simulator patsamba 6
5. Phatikizani ndi Kutsanzira Mapangidwe Patsamba 8
6. View Signal Waveforms patsamba 9
7. Onjezani Zizindikiro pa Kuyerekeza patsamba 11
8. Yambitsaninso Kuyerekeza patsamba 12
9. Sinthani Simulation Testbench patsamba 12

Tsegulani Exampndi Design

PLL_RAM wakaleampkapangidwe kake kumaphatikizapo ma Intel FPGA IP cores kuti awonetse mayendedwe oyambira. Koperani exampndi design files ndikutsegula pulojekitiyi mu pulogalamu ya Intel Quartus Prime.
Zindikirani: Quick-Start iyi imafuna kumvetsetsa koyambira kafotokozedwe ka chilankhulo cha Hardware ndi ma Intel Quartus Prime design flow, monga Intel Quartus Prime Pro Edition Foundation Online Training ikufotokozera.

1. Tsitsani ndikutsegula mawonekedwe a Quartus_Pro_PLL_RAM.zip akaleample.
2. Yambitsani pulogalamu ya Intel Quartus Prime Pro Edition 19.4 kapena mtsogolo.
3. Kutsegula example design project, dinani File ➤ Tsegulani Project, sankhani pulojekiti ya pll_ram.qpf file, ndiyeno dinani Chabwino.

Chithunzi 2. pll_ram Project mu Intel Quartus Prime Pro Edition

Tchulani Zokonda za EDA Tool

Tchulani makonda a zida za EDA kuti mupange zoyerekeza files kwa ma simulators othandizira.

1. Mu pulogalamu ya Intel Quartus Prime, dinani Ntchito ➤ Zokonda ➤ Zokonda pa Chida cha EDA.
2. Pansi pa Kuyerekeza, sankhani ModelSim-Intel FPGA ngati dzina lachida. Sungani zosintha zosasinthika za Format kwa linanena bungwe netlist ndi Linanena bungwe lowongolera.

Pangani template ya Simulator Setup Script

Zolemba zokhazikitsira simulator zimakuthandizani kutengera ma IP cores pamapangidwe anu. Tsatirani izi kuti mupange template yokhazikitsidwa ndi mavenda eni eni a ma module a IP mu ex.ampndi design. Mutha kusintha template iyi kuti ikhale ndi zolinga zanu zofananira.

1. Kuti mupange mapangidwewo, dinani Kukonza ➤ Yambani Kuphatikiza. Zenera la Mauthenga limasonyeza pamene kusonkhanitsa kwatha.
2. Dinani Zida ➤ Pangani Simulator Yokhazikitsira Script ya IP. Sungani bukhu losasinthika la Output ndi Gwiritsani ntchito njira zofananira ngati kuli kotheka kukhazikitsa script file. The setup script template imapanga mu chikwatu chomwe mwafotokoza.

Chithunzi 3. Pangani Sitima Yokonzekera Zolemba za IP Dialog Box

Sinthani Setup Script ya Simulator

Sinthani script yokhazikitsidwa ndi simulator yopangidwa kuti mutsegule malamulo omwe amatsanzira ma IP cores mu projekiti.

1. Mumawu osintha, tsegulani /PLL_RAM/mentor/msim_setup.tcl file.
2. Pangani mawu atsopano file ndi dzina mentor_example.do ndikusunga mu /PLL_RAM/mentor/ directory.
3. Mu msim_setup.tcl file, koperani gawo la code lomwe lili mkati mwa TOP-LEVEL TEMPLATE - BEGIN ndi TOP-LEVEL TEMPLATE - END ndemanga, ndiyeno muyike code iyi mu mentor_ex watsopano.ample.do file.
4. Mu mentor_example.do file, chotsani zilembo za pounds imodzi (#) patsogolo pa mizere yotsatirayi kuti mutsegule malamulo ophatikiza:

Chithunzi 4. Uncomment Anatsindika Kayeseleledwe Malamulo mu Script

1. Sinthani mizere yotsatirayi mu mentor_example.do script:

Table 1. Tchulani Makhalidwe mu mentor_example.do Script

Sinthani Mzere uwu	Ndi Line iyi
khazikitsani QSYS_SIMDIR	../
vlog files>	vlog -vlog01compat -ntchito ntchito ../PLL_RAM.v vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v vlog -vlog01compat -work work ../RAMhub/RAMhub.v vlog -vlog01compat -work work ../testbench_1.v
konzani TOP_LEVEL_NAME	konzani TOP_LEVEL_NAME t
thamanga -a	onjezera mphamvu * view kapangidwe view zizindikiro zimathamanga - zonse

1. Sungani /PLL_RAM/mentor/mentor_example.do file. Chithunzi chotsatira chikuwonetsa mentor_example.do file kukonzanso kukamalizidwa:

Chithunzi 5. Anatsirizidwa Top-Level IP Simulation Setup Script

Sungani ndi Kutsanzira Mapangidwe

Thamangani mentor_ex wapamwambaample.do mu pulogalamu ya ModelSim - Intel FPGA Edition kuti mupange ndikutengera kapangidwe kanu.

1. Kukhazikitsa pulogalamu ya ModelSim - Intel FPGA Edition. ModelSim - Intel FPGA Edition GUI imakonza zinthu zomwe mungayesere kukhala mazenera ndi ma tabu osiyana.
2. Kuchokera pa chikwatu cha polojekiti ya PLL_RAM, tsegulani testbench_1.v file. Momwemonso, tsegulani metor/mentor_example.do file.
3. Kuti muwonetse zenera la Transcript, dinani View ➤ Zolemba. Mutha kuyika malamulo a ModelSim - Intel FPGA Edition mwachindunji pawindo la Transcript.
4. Lembani lamulo ili pawindo la Transcript ndikusindikiza Enter: do mentor_example.do

Mapangidwewo amaphatikiza ndi kufananiza, malinga ndi zomwe mwalemba mu mentor_example.no script. Chithunzi chotsatira chikuwonetsa simulator ya ModelSim - Intel FPGA Edition:

Chithunzi 6. ModelSim - Intel FPGA Edition GUI

View Signal Waveforms

Tsatirani izi kuti view zizindikiro mu testbench_1.v kayeseleledwe waveform:

1. Dinani pa Wave zenera. Mawonekedwe oyeserera amatha ku 11030 ns, monga momwe testbench imanenera. Zenera la Wave limatchula zizindikiro za CLOCK, WE, OFFSET, RESET_N, ndi RD_DATA.

Chithunzi 7. ModelSim - Intel FPGA Edition Wave Window

1. Ku view ma sign omwe ali pamapangidwe apamwamba a pll_ram.v, dinani Sim tabu. Zenera la Sim limalumikizana ndi zenera la Zinthu.

Chithunzi 8. ModelSim - Intel FPGA Edition Sim ndi Zinthu Windows

1. Ku view ma siginecha apamwamba kwambiri, kulitsa chikwatu cha tb mu tabu ya Zinthu. Mofananamo, onjezerani chikwatu cha Test1. Zenera la Zinthu likuwonetsa UP_module, DOWN_module, PLL_module, ndi ma siginolo a RAM_module.
2. Pa zenera la Sim, dinani gawo lomwe lili pansi pa Test1 kuti muwonetse zizindikiro za gawoli pawindo la Zinthu.
3. View laibulale yoyeserera files pawindo la Library.

Chithunzi 9. ModelSim - Intel FPGA Edition Library Window

Onjezani Zizindikiro ku Simulation

Zizindikiro za CLOCK, WE, OFFSET, RESET_N, ndi RD_DATA zimawonekera pawindo la Wave chifukwa mapangidwe apamwamba amatanthauzira I/O izi. Komanso, inu mukhoza optionally kuwonjezera zizindikiro mkati kayeseleledwe.

1. Pazenera la Zinthu, pezani UP_module, DOWN_module, PLL_module, ndi RAM_module.
2. Pazenera la Zinthu, sankhani RAM_module. Zolowa ndi zotuluka mu module ndizo
3. chiwonetsero.

Chithunzi 10. Onjezani Zizindikiro Zopangira Mawindo

1. Kuti muwonjezere zizindikiro zamkati pakati pa gawo lotsika-kauntala ndi lapawiri-doko la RAM, dinani kumanja rdaddress ndikudina Add Wave.
2. Kuti muwonjezere ma sign amkati pakati pa module ya up-counter ndi dual-port RAM, dinani kumanja wraddress ndikudina Add Wave. Kapenanso, mutha kukoka ndikugwetsa zizindikiro izi kuchokera pawindo la Zinthu kupita pawindo la Wave.
3. Kuti mupange mawonekedwe a mafunde a ma siginolo atsopano omwe mwawonjeza, dinani Sanzanitsa ➤ Thamangani ➤ Pitirizani.

Yambitsaninso Mayesedwe

Muyenera kuyambiranso kuyerekezera ngati musintha kusintha kofananira, monga kuwonjezera ma sign pawindo la Wave, kapena kusintha testbench_1.v file. Tsatirani izi kuti muyambitsenso kayeseleledwe:

1. Mu simulator ya ModelSim - Intel FPGA Edition, dinani Sanzanitsa ➤ Yambitsaninso. Sungani zosankha zokhazikika ndikudina Chabwino. Zosankha izi zimachotsa ma waveform ndikuyambitsanso nthawi yofananira, ndikusunga zizindikiro ndi zoikamo zofunika.
   Zindikirani: Kapenanso, mutha kuyambiranso /PLL_RAM/mentor/mentor_example.do script kuti muyambenso kuyerekezera pamzere wolamula.
2. Dinani Sanzirani ➤ Thamangani ➤ Thamangani -onse. The testbench_1.v file imatsanzira molingana ndi ma testbench. Kuti mupitirize kuyerekezera, dinani Sanzanitsa ➤ Thamangani ➤ Pitirizani. Lamuloli likupitiliza kuyerekezera mpaka mutadina batani la Imani.

Sinthani Simulation Testbench

The testbench_1.v example testbench amayesa kokha seti yeniyeni ya zinthu ndi milandu mayeso. Mutha kusintha pamanja testbench_1.v file mu ModelSim - Intel FPGA Edition simulator kuyesa milandu ndi mikhalidwe ina:

1. Tsegulani testbench_1.v file mu ModelSim - Intel FPGA Edition simulator.
2. Dinani kumanja pa testbench_1.v file kutsimikizira kuti file sichinasinthidwe kukhala Read Only.
3. Lowetsani ndikusunga magawo ena owonjezera a testbench mu testbench_1.v file.
4. Kuti mupange ma waveform a testbench yomwe mwasintha, dinani Sanzirani ➤ Yambitsaninso.
5. Dinani Sanzirani ➤ Thamangani ➤ Thamangani -onse.

ModelSim - Mbiri ya Intel FPGA Edition Simulation Quick-Start Revision History

Document Version	Intel Quartus Prime Version	Zosintha
2019.12.30	19.4	• Masitepe osinthidwa ndi zithunzi za Intel Quartus Prime Pro Edition 19.4. • Mapangidwe osinthidwa example file ulalo ndi zomwe zili.
2018.09.25	18.0	Zolakwika za syntax mu mentor_example.do Script.
2018.05.07	18.0	Kuchotsedwa sitepe yosafunika Thamangani Kayeseleledwe pa Command Line ndondomeko.
2017.07.15	17.1	Kutulutsidwa koyamba.

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa chakugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito.

• Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

Zolemba / Zothandizira

Intel UG-20093 ModelSim FPGA Edition Simulation [pdf] Buku Logwiritsa Ntchito UG-20093 ModelSim FPGA Edition Simulation, UG-20093, ModelSim FPGA Edition Simulation, FPGA Edition Simulation, Edition Simulation

Maumboni

• Buku Logwiritsa Ntchito