Intel UG-20093 ModelSim FPGA Edition Ukulinganisa

IModeliSim* –I-Intel® FPGA yoHlelo lokulinganisa uQalo oluKhawulezayo lwe-Intel® Quartus® Prime Pro Edition

Olu xwebhu lubonisa indlela yokulinganisa uyilo lwe-Intel® Quartus® Prime Pro Edition kwiModelSim* – i-Intel FPGA Edition simulator. Ukulinganisa uyilo luqinisekisa uyilo lwakho phambi kokwenza inkqubo yesixhobo. I-Intel Quartus Prime software yenza ukulinganisa files kwi-simulators ye-EDA exhaswayo ngexesha loqulunqo loyilo.
Umzobo 1. ImodeliSim - Ushicilelo lwe-Intel FPGA

Ukulinganisa uyilo kubandakanya ukuvelisa ukulinganisa files, ukuqulunqa iimodeli zokulinganisa, ukuqhuba ukulinganisa, kunye viewngokujonga iziphumo. La manyathelo alandelayo achaza oku kuhamba:

1. Vula iExample Yila kwiphepha lesi-4
2. Chaza imimiselo yesixhobo se-EDA kwiphepha lesi-4
3. Yenza iSifanekiso seSikripthi sokuSeta iSifaniso kwiphepha lesi-5
4. Guqula iSikripthi sokuSeta iSimulator kwiphepha lesi-6
5. Qokelela uze Ufanise Uyilo kwiphepha lesi-8
6. View Umqondiso weefom zamaza kwiphepha lesi-9
7. Yongeza iMiqondiso kuMfaniso kwiphepha le-11
8. Yenza kwakhona ukulinganisa kwiphepha le-12
9. Guqula iSimulation Testbench kwiphepha le-12

Vula iExample Design

I-PLL_RAM example uyilo lubandakanya i-Intel FPGA IP cores ukubonisa ukuhamba kokulinganisa okusisiseko. Khuphela i example uyilo files kwaye uvule iprojekthi kwi-Intel Quartus Prime software.
Phawula: Le Quick-Start ifuna ukuqonda okusisiseko kwe-Hardware inkcazo ye-syntax yolwimi kunye ne-Intel Quartus Prime flow design, njengoko i-Intel Quartus Prime Pro Edition Foundation ichaza uQeqesho lwe-Intanethi.

1. Khuphela kwaye uvule iQuartus_Pro_PLL_RAM.zip uyilo example.
2. Qalisa i-Intel Quartus Prime Pro Edition software version 19.4 okanye kamva.
3. Ukuvula i-exampkwiprojekthi yoyilo, cofa File ➤ Vula iProjekthi, khetha iprojekthi ye-pll_ram.qpf file, kwaye emva koko ucofe u-Kulungile.

Umzobo 2. pll_ram Iprojekthi kwi-Intel Quartus Prime Pro Edition

Cacisa Izicwangciso zesixhobo se-EDA

Cacisa useto lwesixhobo se-EDA ukuvelisa ukulinganisa files izilingisi ezixhaswayo.

1. Kwi-Intel Quartus Prime software, cofa izabelo ➤ Useto ➤ Isetingi seSixhobo se-EDA.
2. Ngaphantsi kokulinganisa, khetha iModelSim-Intel FPGA njengegama lesiXhobo. Gcina useto olungagqibekanga lweFomathi yoluhlu lwemveliso lwenethi kunye nolawulo Lwemveliso.

Yenza isiXhobo sokuSeta isiXhobo seSilinganisi

Izikripthi zokuseta iSimulator ziyakunceda ulinganise ii-IP cores kuyilo lwakho. Landela la manyathelo ukuvelisa umthengisi-isimo esithile sokucwangcisa itemplate yemodyuli ye IP kwi ex.ample uyilo. Unokwenza ngokwezifiso le template kwiinjongo zakho zokulinganisa.

1. Ukuqokelela uyilo, cofa uKuqhubekisa ➤ Qalisa ukuHlanganisa. Imiyalezo yefestile ibonisa xa uqokelelo lugqityiwe.
2. Cofa kwiZixhobo ➤ Ukuvelisa iSikripthi sokuSeta iSifanisi se-IP. Gcina i Imveliso engagqibekanga ulawulo kwaye Sebenzisa iindledlana ezizalanayo nanini na xa kukho ucwangciso locwangciso locwangciso file. Itemplate yokucwangcisa iscript yenza kulawulo olukhankanyileyo.

Umzobo 3. Yenza iSimulator yokuSeta iZikripthi zeBhokisi yeDiyalog ye-IP

Guqula iSikripthi sokuSeta iSifanisi

Guqula iscript esenziweyo sokuseta isifanisi ukwenza imiyalelo ethile elinganisa i-IP cores kwiprojekthi.

1. Kumhleli wombhalo, vula i/PLL_RAM/mentor/msim_setup.tcl file.
2. Yila isicatshulwa esitsha file enegama mentor_example.do kwaye uyigcine kwi/PLL_RAM/mentor/ directory.
3. Kwi msim_setup.tcl file, khuphela icandelo lekhowudi efakwe ngaphakathi kwe-TOP-LEVEL TEMPLATE - BEGIN kunye ne-TOP-LEVEL TEMPLATE - END izimvo, kwaye emva koko unamathisele le khowudi kwi-mentor_ex entsha.ampyenza file.
4. Kwi-mentor_exampyenza file, cima iphawundi enye (#) abasebenzi abandulele le migca ilandelayo iphawulweyo ukwenza imiyalelo yoqulunqo:

Umzobo 4. Imiyalelo ye-Uncomment ePhakamileyo yokulinganisa kwiSikripthi

1. Buyisela le migca ilandelayo kwimentor_exampiskripthi se-le.do:

Itheyibhile 1. Chaza amaxabiso kwi-mentor_example.do iSibhalo

Faka endaweni yalo Line	Ngalo Line
seta QSYS_SIMDIR	../
vlog files>	vlog -vlog01compat -sebenza umsebenzi ../PLL_RAM.v vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v vlog -vlog01compat -work work ../RAMhub/RAMhub.v vlog -vlog01compat -work work ../testbench_1.v
seta TOP_LEVEL_NAME	misela TOP_LEVEL_NAME tb
baleka -a	Yongeza iliza * view isakhiwo view iimpawu zibaleka -zonke

1. Gcina i /PLL_RAM/mentor/mentor_exampyenza file. Lo mfanekiso ulandelayo ubonisa i-mentor_exampyenza file emva kokuba uhlaziyo lugqityiwe:

Umzobo 5. ISikripthi esigqityiweyo seNqanaba eliphezulu le-IP yokulinganisa ukulinganisa

Qokelela kwaye Ufanise uYilo

Qhuba inqanaba eliphezulu mentor_exampiskripthi se-le.do kwi-ModelSim-Intel FPGA Edition software ukuqokelela kunye nokulinganisa uyilo lwakho.

1. Yazisa i-ModelSim-Intel FPGA Edition software. I-ModelSim-Intel FPGA Edition GUI iququzelela izinto zokulinganisa kwakho kwiifestile ezahlukeneyo kunye neethebhu.
2. Ukusuka kuluhlu lweprojekthi ye-PLL_RAM, vula i-testbench_1.v file. Ngokufanayo, vula i-mentor/mentor_exampyenza file.
3. Ukubonisa ifestile yeSikripthi, cofa View ➤ Ushicilelo. Ungangenisa imiyalelo ye-ModelSim-Intel FPGA Edition ngqo kwi-Transcript window.
4. Chwetheza lo myalelo ulandelayo kwifestile ye-Transcript uze ucinezele u-Enter: do mentor_exampyenza

Uyilo luqokelela kwaye lufanise, ngokweenkcukacha zakho kwi-mentor_example.akukho script. Lo mzobo ulandelayo ubonisa iModelSim-Intel FPGA Edition simulator:

Umzobo 6. ImodeliSim - Intel FPGA Edition GUI

View Iimpawu zamaza oMqondiso

Landela la manyathelo ukuze view Imiqondiso kwi-testbench_1.v yokulinganisa ifom yokulinganisa:

1. Cofa i Wave window. I-waveform yokulinganisa iphelela kwi-11030 ns, njengoko i-testbench ichaza. Ifestile yeWave idwelisa IXESHA, WE, OFFSET, RESET_N, kunye neempawu ze-RD_DATA.

Umzobo 7. ImodeliSim - Intel FPGA Edition Wave Window

1. Ukuya view imiqondiso kuyilo lwenqanaba eliphezulu pll_ram.v, cofa i Sim tab. Iwindow yeSim ingqamanisa kunye nefestile yeZinto.

Umzobo 8. ImodeliSim -Intel FPGA Edition Sim kunye neZinto zeWindows

1. Ukuya view imiqondiso yemodyuli yomgangatho ophezulu, yandisa incwadi eneenkcukacha ye tb kwiZinto isithuba. Ngokufanayo, yandisa ifolda ye-Test1. Ifestile yeZinto ibonisa UP_modyuli, DOWN_modyuli, PLL_modyuli, kunye neempawu ze-RAM_modyuli.
2. Kwifestile ye-Sim, cofa umnqongo phantsi koVavanyo1 ukubonisa imiqondiso yemodyuli kwi-Objects window.
3. View ithala leencwadi lokulinganisa files kwifestile yeThala leencwadi.

Umzobo 9. IModeliSim – iWindow yeThala leeNcwadi ze-Intel FPGA

Yongeza iMiqondiso kuMfaniso

ICLOCK, WE, OFFSET, RESET_N, kunye ne-RD_DATA iimpawu zivela ngokuzenzekelayo kwi-Wave window kuba uyilo olukwinqanaba eliphezulu luchaza ezi I/O. Ukongeza, unokongeza ngokuzikhethela imiqondiso yangaphakathi ekufaniseni.

1. Kwifestile yeZinto, fumana i-UP_modyuli, DOWN_modyuli, i-PLL_modyuli, kunye ne-RAM_modyuli.
2. Kwifestile yeZinto, khetha i-RAM_modyuli. Amagalelo kunye neziphumo zemodyuli zezi
3. umboniso.

Umzobo 10. Yongeza iMiqondiso kwiWindowri yokuMangalisa

1. Ukongeza imiqondiso yangaphakathi phakathi kwekhawuntara ephantsi kunye nemodyuli ye-RAM yezibuko ezimbini, cofa ekunene rdaddress uze ucofe Yongeza i-Wave.
2. Ukongeza imiqondiso yangaphakathi phakathi kwe-counter-counter kunye ne-double-port yemodyuli ye-RAM, cofa ekunene i-wraddress kwaye emva koko ucofe Yongeza i-Wave. Kungenjalo, ungatsala kwaye ulahle le miqondiso kwi-Objects window ukuya kwiWave window.
3. Ukuvelisa iifom zamaza kwiimpawu ezintsha ozongezayo, cofa Lingisa ➤ Qhuba ➤ Qhuba.

Phinda usebenzise ukulinganisa

Kuya kufuneka uphinde wenze ukulinganisa ukuba wenza utshintsho kulungiselelo lokulinganisa, njengokongeza imiqondiso kwifestile yeWave, okanye ukuguqula i-testbench_1.v file. Landela la manyathelo ukwenza ukulinganisa kwakhona:

1. KwiModelSim-Intel FPGA Edition simulator, cofa Lingisa ➤ Qala kwakhona. Gcina iinketho ezingagqibekanga kwaye ucofe u-Kulungile. Ezi zikhetho zicacisa iifom zamaza kwaye ziqalise kwakhona ixesha lokulinganisa, ngelixa ligcina iimpawu eziyimfuneko kunye nezicwangciso.
   Phawula: Kungenjalo, ungaphinda usebenzise i/PLL_RAM/mentor/mentor_example.do iskripthi sokuphinda siqhube ukulinganisa kumgca womyalelo.
2. Cofa Lingisa ➤ Baleka ➤ Baleka -konke. I-testbench_1.v file ilinganisa ngokweenkcukacha ze-testbench. Ukuqhubeka nokulinganisa, cofa Lingisa ➤ Qhuba ➤ Qhubeka. Lo myalelo uqhubeka nokulinganisa ude ucofe iqhosha elithi Misa.

Guqula iSimulation Testbench

I testbench_1.v example testbench iimvavanyo kuphela iseti ethile yeemeko kunye namatyala uvavanyo. Uyakwazi ukuhlela ngesandla i-testbench_1.v file kwiModelSim-Intel FPGA Edition simulator ukuvavanya ezinye iimeko kunye neemeko:

1. Vula i-testbench_1.v file kwiModelSim-Intel FPGA Edition simulator.
2. Cofa ekunene kwi-testbench_1.v file ukuqinisekisa ukuba file ayimiselwanga kuFunda Kuphela.
3. Ngena kwaye ugcine nayiphi na imilinganiselo eyongezelelweyo ye-testbench kwi-testbench_1.v file.
4. Ukuvelisa iifomati zamaza kwi-testbench oyiguqulayo, cofa Lingisa ➤ Qala kwakhona.
5. Cofa Lingisa ➤ Baleka ➤ Baleka -konke.

IModelSim-Intel FPGA Edition Ukulinganisa iMbali yoHlaziyo oluKhawulezayo

Inguqulelo yoXwebhu	Intel Quartus Prime Version	Iinguqu
2019.12.30	19.4	• Amanyathelo ahlaziyiweyo kunye nescreenshots kwi-Intel Quartus Prime Pro Edition version 19.4. • Uyilo oluhlaziyiweyo umzample file ikhonkco kunye nomxholo.
2018.09.25	18.0	Kulungiswe iimpazamo zesintaksi kwi-mentor_example.do iSibhalo.
2018.05.07	18.0	Kususwe inyathelo elingeyomfuneko ukusuka Qhuba ukulinganisa kumgca womyalelo inkqubo.
2017.07.15	17.1	Ukukhutshwa kokuqala.

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo.

• Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

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Intel UG-20093 ModelSim FPGA Edition Ukulinganisa [pdf] Isikhokelo somsebenzisi UG-20093 ModelSim FPGA Edition Ukulinganisa, UG-20093, ModelSim FPGA Edition Ukulinganisa, FPGA Edition Ukulinganisa, Edition Ukulinganisa

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