Intel UG-20093 ModelSim FPGA Edition Simulation

ModelSim* - Intel® FPGA Edition Simulation Kurumidza-Kutanga Intel® Quartus® Prime Pro Edition

Gwaro iri rinoratidza maitiro ekutevedzera dhizaini yeIntel® Quartus® Prime Pro Edition muModelSim* - Intel FPGA Edition simulator. Dhizaini simulation inosimbisa dhizaini yako isati yagadzirwa dhizaini. Iyo Intel Quartus Prime software inogadzira simulation files yekutsigirwa EDA simulators panguva yekugadzira dhizaini.
Mufananidzo 1. ModelSim - Intel FPGA Edition

Dhizaini simulation inosanganisira kugadzira simulation files, kuunganidza mamodheru ekufananidza, kumhanyisa simulation, uye viewnemhinduro. Matanho anotevera anotsanangura kuyerera uku:

1. Vhura Example Dhizaini papeji 4
2. Taura EDA Tool Settings pane peji 4
3. Gadzira aSimulator Setup Script template pane peji 5
4. Shandura iyo Simulator Setup Script pane peji 6
5. Gadzira uye Tevedzera Magadzirirwo ari papeji 8
6. View Signal Waveforms papeji 9
7. Wedzera Zviratidzo kune Simulation iri papeji 11
8. Dzokorora Simulation papeji 12
9. Shandura iyo Simulation Testbench pane peji 12

Vhura Example Dhizaini

Iyo PLL_RAM example dhizaini inosanganisira Intel FPGA IP cores kuratidza yekutanga simulation kuyerera. Dhaunirodha example design files uye uvhure purojekiti muIntel Quartus Prime software.
Cherechedza: Iyi Kurumidza-Kutanga inoda nzwisiso yekutanga ye Hardware tsananguro yemutauro syntax uye Intel Quartus Prime dhizaini inoyerera, sekutsanangurwa kweIntel Quartus Prime Pro Edition Foundation Online Training.

1. Dhawunirodha uye unzip iyo Quartus_Pro_PLL_RAM.zip dhizaini example.
2. Tangisa iyo Intel Quartus Prime Pro Edition software vhezheni 19.4 kana gare gare.
3. Kuvhura example design project, tinya File ➤ Vhura Project, sarudza pll_ram.qpf chirongwa file, wobva wadzvanya OK.

Mufananidzo 2. pll_ram Project muIntel Quartus Prime Pro Edition

Taura EDA Tool Settings

Rondedzera EDA chishandiso kuseta kugadzira simulation files yemasimulators anotsigirwa.

1. MuIntel Quartus Prime software, tinya Mabasa ➤ Zvirongwa ➤ EDA Tool Settings.
2. Pazasi Simulation, sarudza ModelSim-Intel FPGA sezita reChishandiso. Chengetedza zvigadziriso zvakasarudzika zveFormat yezvinobuda netlist uye Output dhairekitori.

Gadzira yeSimulator Setup Script template

Simulator yekuseta zvinyorwa zvinokubatsira kutevedzera IP cores mudhizaini yako. Tevedza nhanho idzi kugadzira mutengesi-chaiwo simulator yekuseta script template yeIP modules mune ex.ample design. Iwe unogona ipapo kugadzirisa iyi template kune yako chaiyo simulation zvinangwa.

1. Kubatanidza dhizaini, tinya Kugadzirisa ➤ Tanga Kuunganidza. Iwindo reMharidzo rinoratidza kana kuunganidzwa kwapera.
2. Dzvanya Zvishandiso ➤ Gadzira Simulator Setup Script yeIP. Chengetedza iyo default Output dhairekitori uye Shandisa nzira dzehukama pese pazvinogoneka kuseta yekuseta script file. Iyo setup script template inogadzira mudhairekitori yaunotsanangura.

Mufananidzo 3. Gadzira Simulator Setup Scripts IP Dialog Box

Shandura iyo Simulator Setup Script

Shandura iyo yakagadzirwa simulator yekuseta script kuti igone kugonesa mirairo inoteedzera iyo IP cores muprojekiti.

1. Mune chinyorwa chekunyora, vhura iyo /PLL_RAM/mentor/msim_setup.tcl file.
2. Gadzira chinyorwa chitsva file ine zita mentor_example.do uye chengetedza mu /PLL_RAM/mentor/ dhairekitori.
3. In the msim_setup.tcl file, kopira chikamu chekodhi chakavharirwa mukati me TOP-LEVEL TEMPLATE - BEGIN uye TOP-LEVEL TEMPLATE - END makomendi, wobva waisa kodhi iyi mune itsva mentor_ex.ample.do file.
4. Mune mentor_example.do file, bvisa pondo imwechete (#) mavara anotungamira anotevera akaiswa mitsetse kuti agone kuunganidza mirairo:

Mufananidzo 4. Uncomment Yakasimbiswa Yekutevedzera Mirairo muScript

1. Tsiva mitsetse inotevera mumentor_example.do script:

Tafura 1. Rondedzera Hunhu mu mentor_example.do Script

Tsiva Mutsara uyu	NeMutsetse uyu
seta QSYS_SIMDIR	../
vlog files>	vlog -vlog01compat -basa basa ../PLL_RAM.v vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v vlog -vlog01compat -work work ../RAMhub/RAMhub.v vlog -vlog01compat -work work ../testbench_1.v
seta TOP_LEVEL_NAME	seta TOP_LEVEL_NAME tb
kumhanya -a	wedzera wave * view chimiro view zviratidzo zvinomhanya -zvose

1. Sevha iyo /PLL_RAM/mentor/mentor_example.do file. Mufananidzo unotevera unoratidza mentor_example.do file mushure mekudzokorora kwapera:

Mufananidzo 5. Yakapedzwa Top-Level IP Simulation Setup Script

Gadzira uye Tevedzera Dhizaini

Mhanya iyo yepamusoro-level mentor_example.do script muModelSim - Intel FPGA Edition software kuunganidza uye kutevedzera dhizaini yako.

1. Tangisa iyo ModelSim - Intel FPGA Edition software. Iyo ModelSim - Intel FPGA Edition GUI inoronga zvinhu zvekufungidzira kwako mumahwindo akasiyana uye ma tabo.
2. Kubva PLL_RAM dhairekitori reprojekiti, vhura testbench_1.v file. Saizvozvo, vhura iyo mentor/mentor_example.do file.
3. Kuti uratidze hwindo reTranscript, tinya View ➤ Zvinyorwa. Unogona kuisa mirairo yeModelSim - Intel FPGA Edition zvakananga muhwindo reTranscript.
4. Nyora murairo unotevera muhwindo reTranscript wobva wadzvanya Enter: do mentor_example.do

Iyo dhizaini inounganidza uye inoteedzera, zvinoenderana nezvako zvakatemwa mune mentor_example.no script. Iyi inotevera nhamba inoratidza iyo ModelSim - Intel FPGA Edition simulator:

Mufananidzo 6. ModelSim - Intel FPGA Edition GUI

View Signal Waveforms

Tevera matanho aya kuti view zviratidzo mu testbench_1.v simulation waveform:

1. Dzvanya iyo Wave hwindo. Iyo yekufananidza waveform inopera pa11030 ns, sekutsanangurwa kwazvinoitwa testbench. Hwindo reWave rinonyora CLOCK, WE, OFFSET, RESET_N, uye RD_DATA masiginecha.

Mufananidzo 7. ModelSim - Intel FPGA Edition Wave Window

1. To view masaini ari pamusoro-mwero pll_ram.v dhizaini, tinya Sim tab. Iwindo reSim rinopindirana nehwindo reZvinhu.

Mufananidzo 8. ModelSim - Intel FPGA Edition Sim uye Zvinhu Windows

1. To view iyo yepamusoro-level module masaini, wedzera iyo tb dhairekitori muZvinhu tab. Saizvozvo, wedzera iyo Test1 folda. Iwindo reZvinhu rinoratidza iyo UP_module, DOWN_module, PLL_module, uye RAM_module masiginecha.
2. Muhwindo reSim, tinya module iri pasi peTest1 kuratidza masaini emodule muhwindo reZvinhu.
3. View raibhurari yokutevedzera files muhwindo reLibhurari.

Mufananidzo 9. ModelSim - Intel FPGA Edition Library Window

Wedzera Zviratidzo kune Simulation

Iyo CLOCK, WE, OFFSET, RESET_N, uye RD_DATA masiginecha anongoerekana abuda muWave hwindo nekuti iyo yepamusoro-level dhizaini inotsanangura izvi I/O. Mukuwedzera, iwe unogona kusarudza kuwedzera zviratidzo zvemukati kune simulation.

1. Muwindo reZvinhu, tsvaga iyo UP_module, DOWN_module, PLL_module, uye RAM_module module.
2. Muwindo reZvinhu, sarudza RAM_module. Mamepu uye zvinobuda zvemodule ndizvo
3. kuratidza.

Mufananidzo 10. Wedzera Zviratidzo Kuti Wave Window

1. Kuti uwedzere masaini emukati pakati pepasi-kaunda uye mbiri-chiteshi RAM module, tinya-kurudyi rdaddress wobva wadzvanya Wedzera Wave.
2. Kuti uwedzere masaini emukati pakati pe-up-counter uye dual-port RAM module, tinya-kurudyi wraddress wobva wadzvanya Wedzera Wave. Neimwe nzira, unogona kudhonza nekudonhedza aya masaini kubva kuZvinhu hwindo kuenda kuWave hwindo.
3. Kuti ugadzire masaisai emasaini matsva aunowedzera, tinya Simulate ➤ Mhanya ➤ Ramba.

Rerun Simulation

Iwe unofanirwa kudzokorodza iyo simulation kana iwe ukaita shanduko kune simulation setup, sekuwedzera masaini kuWave hwindo, kana kugadzirisa testbench_1.v file. Tevedza matanho aya kuti udzokorore simulation:

1. MuModelSim - Intel FPGA Edition simulator, tinya Simulate ➤ Tangazve. Chengetedza sarudzo dzakasarudzika uye tinya OK. Idzi sarudzo dzinojekesa ma waveform uye kutangazve nguva yekufananidza, uchichengeta masaini anodiwa uye marongero.
   Cherechedza: Neimwe nzira, unogona kumhanyisazve /PLL_RAM/mentor/mentor_example.do script kumhanyisa zvakare simulation pamutsetse wekuraira.
2. Click Simulate ➤ Mhanya ➤ Mhanya -zvose. The testbench_1.v file inotevedzera zvinoenderana neiyo testbench yakatarwa. Kuti uenderere mberi nekuenzanisa, baya Simbisa ➤ Mhanya ➤ Ramba. Uyu murairo unoenderera mberi nekufananidza kusvika wadzvanya bhatani reStop.

Shandura iyo Simulation Testbench

The testbench_1.v example testbench bvunzo chete yakatarwa seti yemamiriro uye bvunzo makesi. Unogona kugadzirisa nemaoko testbench_1.v file muModelSim - Intel FPGA Edition simulator yekuyedza mamwe makesi uye mamiriro:

1. Vhura testbench_1.v file muModelSim - Intel FPGA Edition simulator.
2. Tinya kurudyi mu testbench_1.v file kusimbisa kuti file haina kuiswa kuti Read Only.
3. Pinda uye chengetedza chero yakawedzera testbench paramita mu testbench_1.v file.
4. Kugadzira masaisai ebhenji rebvunzo raunogadzirisa, tinya Simulate ➤ Tangazve.
5. Click Simulate ➤ Mhanya ➤ Mhanya -zvose.

ModelSim - Intel FPGA Edition Simulation Kurumidza-Kutanga Revision Nhoroondo

Document Version	Intel Quartus Prime Version	Kuchinja
2019.12.30	19.4	• Yakagadziridzwa matanho uye zviratidziro zveIntel Quartus Prime Pro Edition vhezheni 19.4. • Magadzirirwo akavandudzwa example file link uye zvirimo.
2018.09.25	18.0	Yakagadziriswa zvikanganiso zvesyntax mune mentor_example.do Script.
2018.05.07	18.0	Yakabviswa nhanho isingakoshi kubva Mhanya Simulation pa Command Line nzira.
2017.07.15	17.1	Kusunungurwa kwekutanga.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi.

• Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.

Zvinyorwa / Zvishandiso

Intel UG-20093 ModelSim FPGA Edition Simulation [pdf] Bhuku reMushandisi UG-20093 ModelSim FPGA Edition Simulation, UG-20093, ModelSim FPGA Edition Simulation, FPGA Edition Simulation, Edition Simulation

References

• User Manual