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intel UG-20093 ModelSim FPGA Edition Simulation

intel-UG-20093-NlereanyaSim-FPGA-Ebipụta-ịme anwansị-ngwaahịa

ModelSim* – Intel® FPGA Edition Simulation Quick-Malite Intel® Quartus® Prime Pro Edition

Akwụkwọ a na-egosi otu esi emepụta Intel® Quartus® Prime Pro Edition na ModelSim* - Intel FPGA Edition simulator. Simulation chepụta na-enyocha imewe gị tupu mmemme ngwaọrụ. Ngwa Intel Quartus Prime na-emepụta simulation files maka simulators EDA akwadoro n'oge nhazi nhazi.
Ọgụgụ 1. ModelSim – Intel FPGA Editionintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-11

Imewe imewe gụnyere imepụta ịme anwansị files, na-achịkọta ụdị ịme anwansị, na-agba simulation, na viewna-arụpụta. Usoro ndị a na-akọwa usoro a:

  1. Mepee Example Kere na ibe 4
  2. Ezipụta Ntọala Ngwaọrụ EDA na ibe 4
  3. Mepụta Template Script Simulator na ibe 5
  4. Megharịa Simulator Setup Script na ibe 6
  5. Chịkọta ma megharịa atụmatụ ahụ na ibe 8
  6. View Ụdị mgbama na ibe 9
  7. Tinye akara ngosi na Simulation na ibe 11
  8. Megharịa Simulation na ibe 12
  9. Megharịa Simulation Testbench na ibe 12
Mepee Example Design

PLL_RAM example imewe na-agụnye Intel FPGA IP cores iji gosi isi simulation eruba. Budata example imewe files wee mepee oru ngo na Intel Quartus Prime software.
Mara: Nke a ngwa ngwa-mmalite chọrọ nghọta bụ isi nke nkọwa nkọwa ngwaike asụsụ syntax na Intel Quartus Prime imewe eruba, dị ka Intel Quartus Prime Pro Edition Foundation Online Ọzụzụ na-akọwa.

  1. Budata ma budata Quartus_Pro_PLL_RAM.zip imewe example.
  2. Mepee ụdị sọftụwia Intel Quartus Prime Pro Edition 19.4 ma ọ bụ karịa.
  3. Iji mepee example imewe oru ngo, pịa File ➤ Mepee Project, họrọ ọrụ pll_ram.qpf file, wee pịa OK.

Ọgụgụ 2. pll_ram Project na Intel Quartus Prime Pro Editionintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-1

Ezipụta Ntọala Ngwaọrụ EDA

Ezipụta ntọala ngwaọrụ EDA iji mepụta ịme anwansị files maka simulators akwadoro.

  1. N'ime sọftụwia Intel Quartus Prime, pịa Ọrụ ➤ Ntọala ➤ Ntọala Ngwa EDA.
  2. N'okpuru Simulation, họrọ ModelSim-Intel FPGA dị ka aha ngwaọrụ. Jido ntọala ndabara maka Ọkpụkpọ maka netlist mmepụta na ndekọ mmepụta.intel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-2

Mepụta Template Ederede Mbido Simulator

Edemede ntọlite ​​​​Simulator na-enyere gị aka ime ka isi ihe IP dị na imewe gị. Soro usoro ndị a ka iwepụta ndebiri edemede simulator akọwapụtara nke onye na-ere ihe maka modul IP dị na mbụ.ample imewe. Ị nwere ike hazie ndebiri a maka ebumnuche ịme anwansị gị.

  1. Iji chịkọta imewe ahụ, pịa Nhazi ➤ Malite Nchịkọta. Window ozi na-egosi mgbe nchikota zuru ezu.
  2. Pịa Ngwa ➤ Mepụta Simulator Mbido Script maka IP. Jido ndekọ ndekọ mmepụta nke ndabara wee jiri ụzọ ndị ikwu mgbe ọ bụla enwere ike ịtọ ntọala maka edemede ntọlite ​​​​ file. Ndebiri edemede ntọlite ​​​​na-ebute na ndekọ nke ị ezipụta.

Ọgụgụ 3. Mepụta Simulator Setup Scripts igbe igbe okwu IPintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-3

Megharịa Simulator Setup Script

Gbanwee edemede ntọlite ​​simulator emepụtara iji mee ka iwu dị iche iche na-eme ka cores IP dị na ọrụ a.

  1. Na ndezi ederede, mepee /PLL_RAM/mentor/msim_setup.tcl file.
  2. Mepụta ederede ọhụrụ file ya na aha mentor_example.do wee chekwaa ya na /PLL_RAM/mentor/ directory.
  3. Na msim_setup.tcl file, detuo akụkụ nke koodu agbakwunyere n'ime TOP-LEVEL TEMPLATE - BEGIN na TOP-LEVEL TEMPLATE - Kwụsị okwu, wee mado koodu a n'ime mentor_ex ọhụrụ.ample.do file.
  4. N'ime onye ndụmọdụ_example.do file, hichapụ mkpụrụedemede otu paụnd (#) bu ụzọ ahịrị ndị a pụtapụtara iji mee ka iwu mkpokọta:

Ọgụgụ 4. Iwu ịme anwansị akọwapụtaghị okwu n'edemedeintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-4

  1. Dochie ahịrị ndị a na mentor_example.do edemede:

Tebụl 1. Ezipụta ụkpụrụ na mentor_example.do Script

Dochie ahịrị a Na ahịrị a
tọọ QSYS_SIMDIR

../
vlog files>  

vlog -vlog01compat -ọrụ ọrụ ../PLL_RAM.v

vlog -vlog01compat -ọrụ ọrụ ../UP_COUNTER_IP/UP_COUNTER_IP.v vlog -vlog01compat -ọrụ ọrụ ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.vlog -vlog01compat -ọrụ ọrụ ../ClockPLL/ClockPLL.v

vlog -vlog01compat -ọrụ ọrụ ../RAMhub/RAMhub.v vlog -vlog01compat -ọrụ ọrụ ../testbench_1.v

tọọ TOP_LEVEL_NAME

tọọ TOP_LEVEL_NAME tb
agba -a  

tinye ife* view nhazi view mgbaàmà na-agba ọsọ - niile

  1. Chekwaa /PLL_RAM/onye ndụmọdụ/mentor_example.do file. Ọnụ ọgụgụ na-esonụ na-egosi mentor_example.do file mgbe emechara nlegharị anya:

Ọgụgụ 5. Ederede Ntọlite ​​Ntọlite ​​Nhazi IP Emecharaintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-5

Chịkọta ma megharịa atụmatụ ahụ

Gbaa mentor_ex ọkwa dị eluample.do script na ModelSim – Intel FPGA Edition sọftụwia iji chịkọta ma mekwaa atụmatụ gị.

  1. Ẹkedori ModelSim – Intel FPGA Edition software. ModelSim – Intel FPGA Edition GUI na-ahazi ihe nke ịme anwansị gị n'ime windo na taabụ dị iche iche.
  2. Site na ndekọ ọrụ PLL_RAM, mepee testbench_1.v file. N'otu aka ahụ, mepee mentor/mentor_example.do file.
  3. Iji gosi mpio transcript, pịa View ➤ transcript. Ị nwere ike tinye iwu maka ModelSim – Intel FPGA Edition ozugbo na mpio transcript.
  4. Pịnye iwu a na mpio transcript wee pịa Tinye: do mentor_example.do

Nhazi ahụ na-achịkọta na simulates, dịka nkọwapụta gị siri dị na mentor_example.enweghị edemede. Ihe onyonyo a na-egosi ModelSim – Intel FPGA Edition simulator:

Ọgụgụ 6. ModelSim - Intel FPGA Edition GUIintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-6

View Ụdị nrịbama

Soro usoro ndị a ka view akara na testbench_1.v simulation waveform:

  1. Pịa windo Wave. The simulation waveform na-agwụ na 11030 ns, dị ka testbench na-akọwapụta. Window Wave depụtara akara CLOCK, WE, OFFSET, RESET_N na RD_DATA.

Ọgụgụ 7. ModelSim – mpio ebili mmiri nke Intel FPGAintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-7

  1. Iji view akara na elu-larịị pll_ram.v imewe, pịa Sim taabụ. Window Sim na-emekọrịta na windo Ihe.

Ọgụgụ 8. ModelSim – Intel FPGA Edition Sim na Ihe Windowsintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-8

  1. Iji view akara ngosi modul dị elu, gbasaa folda tb na taabụ Ihe. N'otu aka ahụ, gbasaa Test1 nchekwa. Window ihe na-egosiputa akara UP_module, DOWN_module, PLL_module na RAM_module.
  2. Na mpio Sim, pịa modul n'okpuru Test1 iji gosi akara modul na mpio ihe.
  3. View ụlọ akwụkwọ simulation files na mpio Library.

Ọgụgụ 9. ModelSim – Ohere ọbá akwụkwọ mbipụta Intel FPGAintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-9

Tinye akara na ịme anwansị

Akara ngosi CLOCK, WE, OFFSET, RESET_N na RD_DATA na-apụta ozugbo na windo Wave n'ihi na nhazi ọkwa dị elu na-akọwa I/O ndị a. Na mgbakwunye, ịnwere ike ịgbakwunye akara ime na ịme anwansị ahụ.

  1. Na mpio ihe, chọta modul UP_module, DOWN_module, PLL_module na RAM_module.
  2. Na mpio ihe, họrọ RAM_module. Ntinye na ntinye nke modul bụ
  3. ngosi.

Ọgụgụ 10. Tinye mgbama na windo ifegharịintel-UG-20093-ModelSim-FPGA-Ebipụta-Ntugharị-FIG-10

  1. Iji tinye akara n'ime n'etiti modul-counter na ọdụ ụgbọ mmiri abụọ, pịa rdaddress aka nri wee pịa Tinye Wave.
  2. Ka ịgbakwunye akara dị n'ime n'etiti modul RAM-counter na dual-port, pịa aka nri wraddress wee pịa Tinye Wave. N'aka nke ọzọ, ịnwere ike ịdọrọ na dobe mgbaama ndị a site na mpio ihe na windo Wave.
  3. Iji mepụta ụdị ebili mmiri maka akara ọhụrụ ị gbakwunyere, pịa Simulate ➤ Gbaa ➤ Gaa n'ihu.

Malitegharịa Simulation

Ị ga-emerịrị simulation ahụ ma ọ bụrụ na ịmee mgbanwe na ntọala simulation, dị ka ịgbakwunye akara na windo Wave, ma ọ bụ gbanwee testbench_1.v file. Soro usoro ndị a iji megharịa simulation:

  1. Na ModelSim – Intel FPGA Edition simulator, pịa Simulate ➤ Malitegharịa ekwentị. Jido ndabara nhọrọ wee pịa OK. Nhọrọ ndị a na-ekpochapụ ụdị ebili mmiri ma malitegharịa oge ịme anwansị, ka ị na-ejigide akara na ntọala ndị dị mkpa.
    Mara: N'aka nke ọzọ, ị nwere ike megharịa /PLL_RAM/mentor/mentor_example.do script iji megharịa simulation na ahịrị iwu.
  2. Pịa Simulate ➤ Gbaa ọsọ ➤ Gbaa ọsọ - niile. The testbench_1.v file simulates dị ka testbench nkọwa. Iji gaa n'ihu ịme anwansị, pịa Simulate ➤ Gbaa ➤ Gaa n'ihu. Iwu a na-aga n'ihu na ịme anwansị ahụ ruo mgbe ịpịrị bọtịnụ Kwụsị.
Dezie Simulation Testbench

The testbench_1.v example testbench na-anwale naanị otu ọnọdụ na ikpe nnwale. Ị nwere ike iji aka dezie testbench_1.v file na ModelSim – Intel FPGA Edition simulator iji nwalee ikpe na ọnọdụ ndị ọzọ:

  1. Mepee testbench_1.v file na ModelSim – Intel FPGA Edition simulator.
  2. Pịa aka nri na testbench_1.v file iji gosi na file atọrọ ka ọ bụrụ naanị ịgụ.
  3. Tinye ma chekwaa paramita testbench ọ bụla na testbench_1.v file.
  4. Iji mepụta ụdị ebili mmiri maka testbench ị gbanwee, pịa Simulate ➤ Malitegharịa ekwentị.
  5. Pịa Simulate ➤ Gbaa ọsọ ➤ Gbaa ọsọ - niile.

ModelSim – Intel FPGA Edition Simulation Akụkọ Ndozigharị ngwa ngwa

Ụdị akwụkwọ Intel Quartus Prime Version Mgbanwe
2019.12.30 19.4 • Usoro emelitere na nseta ihuenyo maka ụdị Intel Quartus Prime Pro Edition 19.4.

• Nhazi emelitere example file njikọ na ọdịnaya.

2018.09.25 18.0 Njehie syntax emeziri na mentor_example.do Script.
2018.05.07 18.0 E wepụrụ nzọụkwụ na-enweghị isi na Gbaa Simulation na Command Line

usoro.

2017.07.15 17.1 Ntọhapụ mbụ.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ.

  • Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.

Akwụkwọ / akụrụngwa

intel UG-20093 ModelSim FPGA Edition Simulation [pdf] Ntuziaka onye ọrụ
UG-20093 ModelSim FPGA Edition Simulation, UG-20093, ModelSim FPGA Edition Simulation, FPGA Edition Simulation, Edition Simulation

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