Microchip UG0881 PolarFire SoC FPGA Booting Thiab Configuration
Warranty
Microsemi tsis muaj kev lav phib xaub, kev sawv cev, lossis kev lees paub txog cov ntaub ntawv muaj nyob hauv no lossis qhov tsim nyog ntawm nws cov khoom thiab cov kev pabcuam rau ib lub hom phiaj tshwj xeeb, thiab Microsemi tsis muaj kev lav phib xaub txhua yam uas tshwm sim los ntawm daim ntawv thov lossis siv cov khoom lossis cov khoom siv. Cov khoom muag hauv qab no thiab lwm yam khoom muag los ntawm Microsemi tau raug kuaj sim thiab yuav tsum tsis txhob siv nrog rau lub hom phiaj-cov cuab yeej tseem ceeb lossis kev siv. Txhua qhov kev ua tau zoo tshwj xeeb yog ntseeg tau tias muaj kev ntseeg siab tab sis tsis tau lees paub, thiab Cov Neeg Yuav Khoom yuav tsum ua thiab ua kom tiav tag nrho cov kev ua tau zoo thiab lwm yam kev sim ntawm cov khoom, ib leeg thiab ua ke nrog, lossis muab tso rau hauv, txhua yam khoom kawg. Cov neeg yuav khoom yuav tsum tsis txhob hais txog cov ntaub ntawv thiab kev ua haujlwm tshwj xeeb lossis cov kev txwv uas muab los ntawm Microsemi. Nws yog tus neeg yuav khoom lub luag haujlwm los txiav txim siab txog qhov tsim nyog ntawm txhua yam khoom thiab kuaj thiab txheeb xyuas qhov qub. Cov ntaub ntawv muab los ntawm Microsemi hereunder yog muab "raws li yog, qhov twg yog" thiab nrog rau tag nrho cov faults, thiab tag nrho cov kev pheej hmoo cuam tshuam nrog cov ntaub ntawv no yog tag nrho nrog tus neeg yuav khoom. Microsemi tsis tso cai, qhia meej lossis implicitly, rau ib tog twg muaj cai patent, ntawv tso cai, lossis lwm yam IP txoj cai, txawm hais txog cov ntaub ntawv no nws tus kheej lossis txhua yam uas tau piav qhia los ntawm cov ntaub ntawv no. Cov ntaub ntawv muab hauv daim ntawv no yog tus tswv rau Microsemi, thiab Microsemi muaj txoj cai los hloov cov ntaub ntawv hauv daim ntawv no lossis rau cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom.
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Booting thiab Configuration
PolarFire SoC FPGAs siv cov khoom siv hluav taws xob siab tshaj plaws kom ntseeg tau lub zog ntawm lub zog thiab rov pib dua. Thaum lub zog-up thiab rov pib dua, PolarFire SoC FPGA boot-up sequence ua raws li Power-on reset (POR), Ntaus khau raj, Tsim pib, Microcontroller Subsystem (MSS) ua ntej khau raj, thiab MSS neeg siv khau raj. Cov ntaub ntawv no piav txog MSS pre-boot thiab MSS User Boot. Rau cov ntaub ntawv hais txog POR, Ntaus khau raj thiab tsim qauv pib, saib UG0890: PolarFire SoC FPGA Power-Up thiab Resets User Guide.
Yog xav paub ntxiv txog MSS nta, saib UG0880: PolarFire SoC MSS Tus Neeg Siv Qhia.
Boot-up Sequence
Qhov kev sib tw khau raj pib thaum PolarFire SoC FPGA yog powered-up lossis rov pib dua. Nws xaus thaum lub processor npaj txhij los ua ib qho kev thov kev pab cuam. Qhov booting sequence no khiav los ntawm ob peb stages ua ntej nws pib ua cov kev pab cuam.
Ib txheej ntawm kev ua haujlwm tau ua thaum lub sijhawm Boot-up txheej txheem uas suav nrog kev rov pib dua lub zog ntawm cov khoom siv, peripheral initialization, cim xeeb pib, thiab thauj cov neeg siv daim ntawv thov los ntawm lub cim xeeb tsis hloov pauv mus rau lub cim xeeb tsis zoo rau kev ua tiav.
Cov duab hauv qab no qhia cov theem sib txawv ntawm Boot-up sequence.
Daim duab 1 Boot-up Sequence
MSS Pre-Boot
Thaum ua tiav ntawm Tsim Kev Tsim Nyog tiav, MSS Pre-boot pib nws qhov kev ua tiav. MSS raug tso tawm los ntawm kev rov pib dua tom qab ua tiav tag nrho cov txheej txheem pib pib. Tus tswj system tswj cov programming, pib, thiab teeb tsa ntawm cov khoom siv. MSS Pre-boot tsis tshwm sim yog hais tias lub programmed ntaus ntawv yog configured rau qhov system maub los suspend hom.
MSS pre-boot theem ntawm kev pib yog kev sib koom tes los ntawm kev tswj hwm lub cev firmware, txawm hais tias nws yuav ua rau siv E51 hauv MSS Core Complex los ua qee qhov ntawm qhov ua ntej khau raj.
Cov xwm txheej hauv qab no tshwm sim thaum lub sijhawm MSS pre-boot stage:
- Power-up ntawm MSS embedded Non-Volatile Memory (eNVM)
- Kev pib ntawm kev kho redundancy txuam nrog MSS Core Complex L2 cache
- Authentication ntawm User boot code (yog tias User Secure boot xaiv tau qhib)
- Muab kev ua haujlwm MSS rau User Boot code
MSS Core Complex tuaj yeem raug booted hauv ib qho ntawm plaub hom. Cov lus hauv qab no teev cov MSS pre-boot xaiv, uas tuaj yeem teeb tsa thiab programmed rau hauv sNVM. Hom khau raj yog txhais los ntawm tus neeg siv parameter U_MSS_BOOTMODE[1:0]. Ntxiv cov ntaub ntawv kev teeb tsa khau raj yog hom-nyob thiab tau txhais los ntawm tus neeg siv qhov ntsuas U_MSS_BOOTCFG (saib Table 3, nplooj 4 thiab Table 5, nplooj 6).
Table 1 • MSS Core Complex khau raj hom
| U_MSS_BOOTMODE[1:0] | Hom | Kev piav qhia |
| 0 | Idle khau raj | MSS Core Complex khau raj los ntawm khau raj ROM yog MSS tsis teeb tsa |
| 1 | Tsis ruaj ntseg khau raj | MSS Core Complex khau raj ncaj qha los ntawm qhov chaw nyob uas tau teev tseg los ntawm U_MSS_BOOTADDR |
| 2 | Tus neeg siv kev ruaj ntseg khau raj | MSS Core Complex khau raj los ntawm sNVM |
| 3 | Factory ruaj ntseg khau raj | MSS Core Complex khau raj siv lub Hoobkas ruaj ntseg khau raj raws tu qauv |
Kev xaiv khau raj raug xaiv los ua ib feem ntawm Libero tsim ntws. Hloov hom tuaj yeem ua tiav los ntawm tiam tshiab FPGA programming file.
Daim duab 2 • MSS Pre-boot Flow 
Idle Boot
Yog tias MSS tsis tau teeb tsa (example, cov khoom siv dawb paug), tom qab ntawd MSS Core Complex ua rau khau raj ROM program uas tuav tag nrho cov txheej txheem hauv lub voj tsis kawg kom txog rau thaum lub debugger txuas rau lub hom phiaj. Lub khau raj vector sau npe tswj hwm lawv cov nqi kom txog thaum lub cuab yeej rov pib dua lossis kev teeb tsa hom khau raj tshiab yog programmed. Rau cov khoom siv tau teeb tsa, hom no tuaj yeem siv tau los ntawm
U_MSS_BOOTMODE=0 kev xaiv khau raj hauv Libero configurator.
Nco tseg: Hauv hom no, U_MSS_BOOTCFG tsis siv.
Cov duab hauv qab no qhia txog Idle khau raj ntws.
Daim duab 3 • Idle Boot Flow
Tsis ruaj ntseg khau raj
Hauv hom no, MSS Core Complex ua tiav los ntawm qhov chaw nyob eNVM tsis muaj kev lees paub. Nws muab cov kev xaiv khau raj ceev tshaj plaws, tab sis tsis muaj kev lees paub ntawm tus lej duab. Qhov chaw nyob tuaj yeem raug teev los ntawm kev teeb tsa U_MSS_BOOTADDR hauv Libero Configurator. Hom no kuj tseem siv tau los khau raj los ntawm ib qho FPGA Fabric nco qhov chaw los ntawm FIC. Hom no yog siv los ntawm cov
U_MSS_BOOTMODE=1 kev xaiv khau raj.
MSS Core Complex raug tso tawm los ntawm kev rov pib dua nrog boot vectors txhais los ntawm U_MSS_BOOTCFG (raws li teev nyob rau hauv cov lus hauv qab no).
Table 2 • U_MSS_BOOTCFG Kev siv nyob rau hauv Tsis-Secure khau raj hom 1
| Offset (bytes) |
Loj (bytes) |
Lub npe |
Kev piav qhia |
| 0 | 4 | BOOTVEC 0 | Boot vector rau E51 |
| 4 | 4 | BOOTVEC 1 | Boot vector rau U540 |
| 8 | 4 | BOOTVEC 2 | Boot vector rau U541 |
| 16 | 4 | BOOTVEC 3 | Boot vector rau U542 |
| 20 | 4 | BOOTVEC 4 | Boot vector rau U543 |
Cov duab hauv qab no qhia txog qhov tsis muaj kev ruaj ntseg khau raj ntws.
Daim duab 4 • Tsis ruaj ntseg Boot Flow
Tus neeg siv Secure Boot
Hom no tso cai rau cov neeg siv los siv lawv tus kheej kev cai ruaj ntseg khau raj thiab cov neeg siv kev ruaj ntseg khau raj tau muab tso rau hauv sNVM. sNVM yog 56 KB tsis-volatile nco uas tuaj yeem tiv thaiv los ntawm lub cev ua haujlwm tsis muaj zog (PUF). Txoj kev khau raj no yog suav tias yog kev ruaj ntseg vim sNVM nplooj ntawv cim raws li ROM yog qhov hloov tsis tau. Thaum lub zog nce, tus tswj hwm lub kaw lus luam theej tus neeg siv kev ruaj ntseg khau raj los ntawm sNVM rau Cov Ntaub Ntawv Tightly Integrated Memory (DTIM) ntawm E51 Monitor core. E51 pib executing tus neeg siv kev ruaj ntseg khau raj code.
Yog hais tias qhov loj ntawm tus neeg siv kev ruaj ntseg khau raj code yog ntau tshaj qhov loj ntawm DTIM ces tus neeg siv yuav tsum tau faib cov khau raj code rau hauv ob s.tages. sNVM tuaj yeem muaj cov s tom ntejtage ntawm tus neeg siv khau raj ib ntus, uas tuaj yeem ua pov thawj ntawm cov khau raj tom ntejtage siv tus neeg siv authentication/decryption algorithm.
Yog tias siv cov nplooj ntawv pov thawj lossis encrypted, ces tus yuam sij USK tib yam (uas yog,
U_MSS_BOOT_SNVM_USK) yuav tsum tau siv rau tag nrho cov nplooj ntawv pov thawj / encrypted.
Yog tias kev lees paub tsis ua tiav, MSS Core Complex tuaj yeem muab tso rau hauv rov pib dua thiab BOOT_FAIL tamper chij tuaj yeem tsa. Hom no yog siv los ntawm U_MSS_BOOTMODE=2 kev xaiv khau raj.
Table 3 • U_MSS_BOOTCFG Kev siv hauv Cov Neeg Siv Kev Ruaj Ntseg
| Offset (bytes) | Loj (bytes) | Lub npe | Kev piav qhia |
| 0 | 1 | U_MSS_BOOT_SNVM_PAGE | Pib nplooj ntawv hauv SNVM |
| 1 | 3 | TSEV | Rau kev sib tw |
| 4 | 12 | U_MSS_BOOT_SNVM_USK | Rau authenticated/encrypted nplooj ntawv |
Cov duab hauv qab no qhia txog cov neeg siv kev ruaj ntseg khau raj ntws.
Daim duab 5 • Tus neeg siv Secure Boot Flow
Factory Secure Boot
Hauv hom no, tus tswj hwm lub kaw lus tau nyeem daim ntawv pov thawj Secure Boot Image Certificate (SBIC) los ntawm eNVM thiab validates SBIC. Ntawm kev siv tau zoo, Tus Tswj Xyuas Txheej Txheem luam theej lub Hoobkas ruaj ntseg khau raj code los ntawm nws tus kheej, ruaj ntseg thaj chaw nco thiab thauj nws mus rau hauv DTIM ntawm E51 Monitor core. Lub neej ntawd kev ruaj ntseg khau raj ua qhov kos npe kos npe ntawm eNVM duab siv SBIC uas tau khaws cia hauv eNVM. Yog tias tsis muaj qhov yuam kev raug tshaj tawm, rov pib dua raug tso tawm rau MSS Core Complex. Yog tias qhov yuam kev raug tshaj tawm, MSS Core Complex tau muab tso rau hauv rov pib dua thiab BOOT_FAIL tamper chij yog tsa. Tom qab ntawd, qhov system maub los qhib rau ntawmamper chij uas lees paub lub teeb liab rau FPGA npuag rau cov neeg siv khoom. Hom no yog siv los ntawm U_MSS_BOOTMODE=3 kev xaiv khau raj.
SBIC muaj qhov chaw nyob, qhov loj me, hash, thiab Elliptic Curve Digital Signature Algorithm (ECDSA) kos npe ntawm kev tiv thaiv binary blob. ECDSA muaj qhov sib txawv ntawm Digital Signature Algorithm uas siv elliptic nkhaus cryptography. Nws kuj muaj qhov rov pib dua vector rau txhua Hardware
xov / core / processor core (Hart) hauv qhov system.
Table 4 • Secure Boot Image Certificate (SBIC)
| Offset | Loj (bytes) | Tus nqi | Kev piav qhia |
| 0 | 4 | IMAGEADDR | Chaw nyob ntawm UBL hauv MSS nco daim ntawv qhia |
| 4 | 4 | IMAGELEN | Qhov loj ntawm UBL hauv bytes |
| 8 | 4 | BOOTVEC 0 | Boot vector hauv UBL rau E51 |
| 12 | 4 | BOOTVEC 1 | Boot vector hauv UBL rau U540 |
| 16 | 4 | BOOTVEC 2 | Boot vector hauv UBL rau U541 |
| 20 | 4 | BOOTVEC 3 | Boot vector hauv UBL rau U542 |
| 24 | 4 | BOOTVEC 4 | Boot vector hauv UBL rau U543 |
| 28 | 1 | OPTIONS [7:0] | SBIC Options |
| 28 | 3 | TSEV | |
| 32 | 8 | VERSION | SBIC/Image version |
| 40 | 16 | DSN | Optional DSN binding |
| 56 | 48 | H | UBL duab SHA-384 hash |
| 104 | 104 | CODESIG | DER-encoded ECDSA kos npe |
| Tag nrho | 208 | Bytes |
DSN
Yog tias DSN teb tsis yog xoom, nws raug muab piv rau cov cuab yeej ntawm tus lej xov tooj. Yog tias qhov kev sib piv tsis ua tiav, ces boot_fail tamper chij yog teem thiab authentication yog rho tawm.
VERSION
Yog tias SBIC tshem tawm tau qhib los ntawm U_MSS_REVOCATION_ENABLE, SBIC raug tsis lees paub tshwj tsis yog tus nqi ntawm VERSION ntau dua lossis sib npaug ntawm qhov kev tshem tawm.
SBIC REVOCATION OPTION
Yog tias SBIC tshem tawm tau qhib los ntawm U_MSS_REVOCATION_ENABLE thiab OPTIONS[0] yog '1', tag nrho cov SBIC versions tsawg dua VERSION raug tshem tawm tom qab ua tiav authentication ntawm SBIC. Qhov kev tshem tawm tseem nyob ntawm tus nqi tshiab kom txog thaum nws nce ntxiv los ntawm SBIC yav tom ntej nrog OPTIONS[0] = '1' thiab ntau dua VERSION teb. Qhov kev tshem tawm qhov pib yuav tsuas yog nce ntxiv siv cov txheej txheem no thiab tsuas yog rov pib dua los ntawm me ntsis-kwj.
Thaum lub sijhawm tshem tawm qhov hloov pauv hloov pauv hloov pauv, qhov pib raug muab khaws cia siv cov txheej txheem khaws cia tsis tu ncua siv rau cov lej lej xws li lub zog tsis ua haujlwm thaum lub cuab yeej khau raj tsis ua rau cov khoom siv txuas ntxiv ua tsis tiav. Yog tias qhov hloov tshiab ntawm kev tshem tawm qhov pib ua tsis tiav, nws tau lees paub tias tus nqi pib yog tus nqi tshiab lossis tus nqi dhau los.
Table 5 • U_MSS_BOOTCFG Kev siv hauv Hoobkas khau raj Loader hom
| Offset (bytes) |
Loj (bytes) |
Lub npe |
Kev piav qhia |
| 0 | 4 | U_MSS_SBIC_ADDR | Chaw nyob ntawm SBIC hauv MSS chaw nyob |
| 4 | 4 | U_MSS_REVOCATION_ENABLE | Pab kom SBIC tshem tawm yog tias tsis yog xoom |
Cov duab hauv qab no qhia txog lub Hoobkas ruaj ntseg khau raj ntws.
Daim duab 6 • Factory Secure Boot Flow
MSS User Boot
MSS cov neeg siv khau raj siv qhov chaw thaum tswj tau los ntawm System Controller rau MSS Core Complex. Thaum ua tiav MSS ua ntej khau raj, tus tswj hwm qhov system tso tawm qhov rov pib dua rau MSS Core Complex. MSS tuaj yeem raug booted hauv ib qho ntawm cov hauv qab no:
- Bare Hlau Daim Ntawv Thov
- Linux Application
- AMP Daim ntawv thov
Bare Hlau Daim Ntawv Thov
Cov ntawv thov hlau liab qab rau PolarFire SoC tuaj yeem tsim los siv SoftConsole cov cuab yeej. Cov cuab yeej no muab cov zis files nyob rau hauv daim ntawv ntawm .hex uas yuav siv tau nyob rau hauv lub Libero ntws mus rau hauv lub programming bitstream file. Tib lub cuab yeej siv tau los debug cov ntawv thov Bare Metal siv JTAG
interface.
Th cov duab hauv qab no qhia tau hais tias SoftConsole Bare Metal daim ntawv thov uas muaj tsib harts (Cores) suav nrog E51 Saib Xyuas core.
Daim duab 7 • SoftConsole Project 
Linux Application
Tshooj lus no piav qhia txog cov kab ke khau raj rau Linux khiav ntawm tag nrho U54 cores.
Cov txheej txheem khau raj ib txwm muaj peb stages. Thawj stage khau raj loader (FSBL) tau raug tua los ntawm on-chip Boot flash (eNVM). Lub FSBL loads thib ob stage khau raj loader (SSBL) los ntawm khau raj ntaus ntawv mus rau sab nraud RAM lossis Cache. Cov khoom siv khau raj tuaj yeem yog eNVM lossis embedded nco microcontroller (eMMC) lossis sab nraud SPI Flash. Lub SSBL loads Linux operating system los ntawm khau raj ntaus ntawv mus rau sab nraud RAM. Hauv peb lub stage, Linux raug tua los ntawm RAM sab nraud.
Cov duab hauv qab no qhia txog Linux Boot Process ntws.
Daim duab 8 • Hom Linux Boot Process Flow
Cov ntsiab lus ntawm FSBL, Device tree, Linux, thiab YOCTO tsim, yuav tsim thiab teeb tsa Linux li cas yuav muab rau yav tom ntej tso tawm ntawm daim ntawv no.
AMP Daim ntawv thov
Cov lus piav qhia ntxaws ntxaws ntawm Libero MSS Configurator thiab yuav ua li cas rau kev debug ntau cov ntawv thov siv SoftConsole yuav muab rau yav tom ntej tso tawm ntawm daim ntawv no.
Txawv qhov chaw ntawm Booting
Txhawm rau hloov kho nyob rau yav tom ntej versions ntawm daim ntawv no.
Boot Configuration
Txhawm rau hloov kho nyob rau yav tom ntej versions ntawm daim ntawv no.
Cov ntsiab lus
Cov lus sau hauv qab no yog siv rau hauv daim ntawv no.
Table 1 • Daim ntawv teev npe
Lub ntsiab lus nthuav dav
- AMP Asymmetric Multi-processing
- DTIM Cov ntaub ntawv Tightly Integrated Nco (tseem hu ua SRAM)
- ECDSA Elliptic Curve Digital Signature Algorithm
- eNVM embedded Tsis-Volatile Memory
- FSBL Thawj Stage Boot Loader
- Hart Hardware thread / core / processor core
- MSS Microprocessor Subsystem
- POR Fais fab rau Reset
- PUF Lub cev Unclonable Function
- ROM Nyeem-tsuas nco
- SCB System Controller Choj
- sNVM Ruaj ntseg Tsis-volatile Nco
Kev kho keeb kwm
Cov ntaub ntawv kho dua tshiab piav qhia txog cov kev hloov pauv uas tau ua hauv daim ntawv. Cov kev hloov pauv tau teev tseg los ntawm kev kho dua tshiab, pib nrog kev tshaj tawm tam sim no.
Hloov kho 2.0
Cov hauv qab no yog cov ntsiab lus ntawm cov kev hloov pauv hauv qhov kev hloov kho no.
- Cov ntaub ntawv hais txog Factory Secure Boot tau hloov kho.
- Cov ntaub ntawv hais txog Bare Metal Application tau hloov kho.
Hloov kho 1.0
Thawj qhov kev tshaj tawm ntawm daim ntawv no.
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