Microchip UG0881 PolarFire SoC FPGA Booting Da Kanfigareshan
Garanti
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Game da Microsemi
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Booting Da Kanfigareshan
PolarFire SoC FPGAs suna amfani da na'urorin haɓaka wutar lantarki na ci gaba don tabbatar da ingantaccen ƙarfin kunnawa da sake saiti. A wutar lantarki da sake saiti, jerin taya na PolarFire SoC FPGA yana biye da sake saitin wutar lantarki (POR), boot ɗin na'ura, ƙaddamar da ƙira, Microcontroller Subsystem (MSS) pre-boot, da boot ɗin mai amfani na MSS. Wannan takaddar tana bayyana MSS pre-boot da Boot User MSS. Don bayani game da POR, Boot na Na'ura da ƙaddamar da ƙira, duba UG0890: PolarFire SoC FPGA Power-Up da Sake saitin Jagorar Mai Amfani.
Don ƙarin bayani game da fasalulluka na MSS, duba UG0880: PolarFire SoC Jagorar Mai Amfani.
Jerin Boot Up
Jerin taya yana farawa lokacin da aka kunna PolarFire SoC FPGA ko sake saiti. Yana ƙare lokacin da processor ya shirya don aiwatar da shirin aikace-aikacen. Wannan jerin booting yana gudana ta s da yawatages kafin ta fara aiwatar da shirye-shirye.
Ana yin saitin ayyuka yayin aiwatar da Boot-up wanda ya haɗa da sake saitin kayan aikin wuta, farawa na gefe, ƙaddamar da ƙwaƙwalwar ajiya, da loda ƙayyadaddun ƙayyadaddun aikace-aikacen mai amfani daga ƙwaƙwalwar mara mara ƙarfi zuwa ƙwaƙwalwar mara ƙarfi don aiwatarwa.
Hoto na gaba yana nuna matakai daban-daban na jerin Boot-up.
Hoto 1 Jerin Boot Up
MSS Pre-Boot
Bayan nasarar kammala Ƙaddamar da ƙira, MSS Pre-boot ta fara aiwatar da shi. Ana sakin MSS daga sake saiti bayan kammala duk hanyoyin farawa na yau da kullun. Mai sarrafa tsarin yana sarrafa shirye-shirye, farawa, da daidaita na'urorin. MSS Pre-boot baya faruwa idan an saita na'urar da aka tsara don yanayin dakatar da tsarin.
Tsarin farko na MSS na farawa yana daidaitawa ta hanyar firmware mai sarrafa tsarin, kodayake yana iya yin amfani da E51 a cikin MSS Core Complex don aiwatar da wasu sassan jerin pre-boot.
Abubuwan da ke biyo baya suna faruwa a lokacin MSS pre-boot stage:
- Ƙarfafa Ƙwararrun Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar MSS (eNVM)
- Farkon gyaran gyare-gyaren da ke da alaƙa da MSS Core Complex L2 cache
- Tabbatar da lambar taya mai amfani (idan an kunna zaɓi mai amintaccen mai amfani)
- Miƙa MSS mai aiki zuwa lambar Boot mai amfani
Ana iya yin booting Complex MSS Core a ɗayan hanyoyi huɗu. Tebur mai zuwa yana lissafin zaɓuɓɓukan pre-boot na MSS, waɗanda za'a iya daidaita su kuma a tsara su cikin sNVM. An bayyana yanayin taya ta hanyar sigar mai amfani U_MSS_BOOTMODE[1:0]. Ƙarin bayanan saitin taya ya dogara da yanayin kuma an ayyana shi ta hanyar sigar mai amfani U_MSS_BOOTCFG (duba Tebu 3, shafi na 4 da Tebura 5, shafi na 6).
Table 1 • MSS Core Complex Boot Yanayin
| U_MSS_BOOTMODE[1:0] | Yanayin | Bayani |
| 0 | Boot mara aiki | MSS Core Complex takalma daga taya ROM idan ba a daidaita MSS ba |
| 1 | Boot mara tsaro | MSS Core Complex takalma kai tsaye daga adireshin da U_MSS_BOOTADDR ya ayyana |
| 2 | Amintaccen taya mai amfani | MSS Core Complex takalma daga sNVM |
| 3 | Factory amintaccen taya | Takalma na MSS Core Complex ta amfani da amintacciyar yarjejeniya ta masana'anta |
An zaɓi zaɓin taya a matsayin ɓangare na kwararar ƙirar Libero. Canza yanayin za'a iya samun nasara ta hanyar ƙirƙirar sabon shirye-shiryen FPGA file.
Hoto 2 • MSS Pre-boot Flow 
Boot mara aiki
Idan ba a saita MSS ba (misaliample, blank na'ura), sannan MSS Core Complex yana aiwatar da shirin boot ROM wanda ke riƙe dukkan na'urori a cikin madauki marar iyaka har sai mai gyara ya haɗu da manufa. Rijista vector na boot yana kiyaye ƙimar su har sai an sake saita na'urar ko kuma an tsara sabon tsarin yanayin taya. Don na'urorin da aka saita, ana iya aiwatar da wannan yanayin ta amfani da
U_MSS_BOOTMODE=0 zaɓin taya a cikin mai daidaitawa na Libero.
Lura: A wannan yanayin, ba a amfani da U_MSS_BOOTCFG.
Hoto mai zuwa yana nuna kwararar boot ɗin Rago.
Hoto 3 • Gudun Boot Rago
Boot mara tsaro
A cikin wannan yanayin, MSS Core Complex yana aiwatarwa daga takamaiman adireshin eNVM ba tare da tantancewa ba. Yana ba da zaɓin taya mafi sauri, amma babu ingantaccen hoton lambar. Ana iya ƙayyade adireshin ta hanyar saita U_MSS_BOOTADDR a cikin Mai daidaitawa na Libero. Hakanan za'a iya amfani da wannan yanayin don yin taya daga kowane kayan ƙwaƙwalwar FPGA Fabric ta hanyar FIC. Ana aiwatar da wannan yanayin ta amfani da
U_MSS_BOOTMODE=1 zabin taya.
An saki MSS Core Complex daga sake saiti tare da ma'anar boot vector ta U_MSS_BOOTCFG (kamar yadda aka jera a tebur mai zuwa).
Table 2 • Amfanin U_MSS_BOOTCFG a cikin Yanayin Taka mara Tsaro 1
| Kashe (bytes) |
Girman (bytes) |
Suna |
Bayani |
| 0 | 4 | BOOTVEC0 | Saukewa: E51 |
| 4 | 4 | BOOTVEC1 | Boot vector don U540 |
| 8 | 4 | BOOTVEC2 | Boot vector don U541 |
| 16 | 4 | BOOTVEC3 | Boot vector don U542 |
| 20 | 4 | BOOTVEC4 | Boot vector don U543 |
Hoton da ke gaba yana nuna kwararar taya mara tsaro.
Hoto 4 • Gudun Boot mara tsaro
Tabbataccen Boot mai amfani
Wannan yanayin yana ba mai amfani damar aiwatar da nasu amintaccen taya na al'ada kuma an sanya amintaccen lambar taya mai amfani a cikin sNVM. sNVM shine 56 KB ƙwaƙwalwar da ba ta da ƙarfi wacce za a iya kiyaye ta ta ginanniyar Ayyukan Jiki mara ƙarfi (PUF). Ana ɗaukar wannan hanyar taya amintacce saboda shafukan sNVM masu alamar ROM ba su canzawa. A kan kunna wuta, mai sarrafa tsarin yana kwafin amintaccen lambar taya mai amfani daga sNVM zuwa Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙaddamarwa na E51 ) ya yi. E51 ya fara aiwatar da amintaccen lambar taya mai amfani.
Idan girman lambar amintaccen mai amfani ya fi girman girman DTIM to mai amfani yana buƙatar raba lambar taya zuwa s biyu.tage. sNVM na iya ƙunsar s na gabatage na jerin boot ɗin mai amfani, wanda zai iya tabbatar da ingantaccen boot s na gabatage ta amfani da ingantaccen mai amfani / decryption algorithm.
Idan an yi amfani da ingantattun shafuka ko rufaffiyar shafuka to maɓalli ɗaya na USK (wato,
U_MSS_BOOT_SNVM_USK) dole ne a yi amfani da shi don duk ingantattun shafukan da aka ɓoye.
Idan tabbaci ya gaza, ana iya sanya MSS Core Complex a sake saiti kuma BOOT_FAIL tamper tuta za a iya daga. Ana aiwatar da wannan yanayin ta amfani da zaɓin taya U_MSS_BOOTMODE=2.
Table 3 • Amfani da U_MSS_BOOTCFG a cikin Tabbataccen Boot mai amfani
| Kashe (bytes) | Girman (bytes) | Suna | Bayani |
| 0 | 1 | U_MSS_BOOT_SNVM_PAGE | Fara shafi a cikin SNVM |
| 1 | 3 | AJIYA | Don daidaitawa |
| 4 | 12 | U_MSS_BOOT_SNVM_USK | Don ingantattun shafuka/rufe-rufe |
Hoton da ke gaba yana nuna amintaccen guduwar takalmi mai amfani.
Hoto 5 • Amintaccen Mai amfani Boot Guda
Ma'aikata Amintaccen Boot
A cikin wannan yanayin, mai sarrafa tsarin yana karanta Secure Boot Image Certificate (SBIC) daga eNVM kuma yana inganta SBIC. A kan ingantaccen inganci, Mai sarrafa Tsarin yana kwafi amintaccen lambar taya masana'anta daga keɓaɓɓen wurin ƙwaƙwalwar ajiya mai aminci kuma yana loda shi cikin DTIM na E51 Monitor core. Tsohuwar kafaffen takalmin yana yin rajistan sa hannu akan hoton eNVM ta amfani da SBIC wanda aka adana a cikin eNVM. Idan ba a sami rahoton kurakurai ba, ana sake saiti zuwa MSS Core Complex. Idan an sami rahoton kurakurai, ana sanya MSS Core Complex a sake saiti kuma BOOT_FAIL tampko an daga tuta. Sannan, mai sarrafa tsarin yana kunna aamper flag wanda ke tabbatar da sigina zuwa masana'anta na FPGA don aikin mai amfani. Ana aiwatar da wannan yanayin ta amfani da zaɓin taya U_MSS_BOOTMODE=3.
SBIC ta ƙunshi adireshi, girman, zanta, da Elliptic Curve Digital Signature Algorithm (ECDSA) sa hannu na kariyar ɓoyayyen ɓoyayyen ɓoyayyiya. ECDSA yana ba da bambance-bambancen Algorithm na Sa hannu na Dijital wanda ke amfani da cryptography elliptical curve. Hakanan ya ƙunshi reset vector don kowane Hardware
thread/core/processor core (Hart) a cikin tsarin.
Table 4 • Takaddun Takaddar Hoto mai Tsaro (SBIC)
| Kashewa | Girman (bytes) | Daraja | Bayani |
| 0 | 4 | IMAGEADDR | Adireshin UBL a cikin taswirar ƙwaƙwalwar ajiyar MSS |
| 4 | 4 | IMAGELEN | Girman UBL a cikin bytes |
| 8 | 4 | BOOTVEC0 | Boot vector a cikin UBL don E51 |
| 12 | 4 | BOOTVEC1 | Boot vector a cikin UBL don U540 |
| 16 | 4 | BOOTVEC2 | Boot vector a cikin UBL don U541 |
| 20 | 4 | BOOTVEC3 | Boot vector a cikin UBL don U542 |
| 24 | 4 | BOOTVEC4 | Boot vector a cikin UBL don U543 |
| 28 | 1 | ZABI [7:0] | Zaɓuɓɓukan SBIC |
| 28 | 3 | AJIYA | |
| 32 | 8 | VERSION | SBIC/Siffar Hoto |
| 40 | 16 | DSN | Daurin DSN na zaɓi |
| 56 | 48 | H | Hoton UBL SHA-384 hash |
| 104 | 104 | CODESIG | Sa hannun ECDSA mai lamba DER |
| Jimlar | 208 | Bytes |
DSN
Idan filin DSN baya sifili, ana kwatanta shi da lambar serial ɗin na'urar. Idan kwatancen ya gaza, to boot_fail tampAn saita tuta kuma an soke tantancewa.
VERSION
Idan U_MSS_REVOCATION_ENABLE ya kunna SBIC, an ƙi SBIC sai dai idan darajar VERSION ta fi ko daidai da matakin sokewa.
ZABI NA CARUWA
Idan U_MSS_REVOCATION_ENABLE ta kunna sokewar SBIC kuma OPTIONS[0] shine '1', duk nau'ikan SBIC da basu kai VERSION ba ana soke su bayan an tabbatar da cikakken SBIC. Matsakaicin sokewa yana kasancewa a sabuwar ƙima har sai ya sake ƙaruwa ta SBIC na gaba tare da Zɓk[0] = '1' da filin VERSION mafi girma. Ƙimar sokewar za a iya ƙara kawai ta amfani da wannan tsarin kuma za a iya sake saita shi ta hanyar rafi kaɗan kawai.
Lokacin da aka sabunta ƙofar sokewa da ƙarfi, ana adana bakin kofa ta amfani da tsarin ma'ajiya mai yawa da ake amfani da shi don lambobin wucewa kamar gazawar wutar lantarki yayin taya na'urar baya haifar da gazawar na'urar ta gaba. Idan sabuntawar iyakar sokewa ta gaza, an tabbatar da cewa ƙimar kofa ita ce sabuwar ƙima ko ta baya.
Table 5 • Amfanin U_MSS_BOOTCFG a Yanayin Loading Boot na masana'anta
| Kashe (bytes) |
Girman (bytes) |
Suna |
Bayani |
| 0 | 4 | U_MSS_SBIC_ADDR | Adireshin SBIC a sararin adireshin MSS |
| 4 | 4 | U_MSS_REVOCATION_ENABLE | Kunna sokewar SBIC idan ba sifili ba |
Hoton da ke biyo baya yana nuna amintaccen kwararar taya na masana'anta.
Hoto 6 • Factory Secure Boot Flow
Boot mai amfani na MSS
Boot mai amfani na MSS yana faruwa lokacin da aka ba da iko daga Mai Kula da Tsari zuwa MSS Core Complex. Bayan nasarar MSS pre-boot, mai sarrafa tsarin yana fitar da sake saiti zuwa MSS Core Complex. Ana iya haɓaka MSS ta ɗayan hanyoyi masu zuwa:
- Bare Metal Application
- Linux Application
- AMP Aikace-aikace
Bare Metal Application
Ana iya haɓaka aikace-aikacen ƙarfe maras tushe don PolarFire SoC ta amfani da kayan aikin SoftConsole. Wannan kayan aiki yana ba da fitarwa files a cikin nau'i na .hex wanda za'a iya amfani dashi a cikin kwararar Libero don haɗawa cikin bitstream na shirye-shirye file. Ana iya amfani da kayan aiki iri ɗaya don gyara aikace-aikacen Bare Metal ta amfani da JTAG
dubawa.
Wannan adadi mai zuwa yana nuna aikace-aikacen ƙarfe na SoftConsole Bare wanda ke da harts biyar (Cores) gami da E51 Monitor core.
Hoto 7 • SoftConsole Project 
Linux Application
Wannan sashe yana bayyana jerin taya don Linux wanda ke gudana akan duk nau'ikan U54.
Tsarin taya na yau da kullun ya ƙunshi s ukutage. Na farko stage boot Loder (FSBL) ana kashe shi daga kan-chip Boot flash (eNVM). FSBL yana ɗaukar s na biyutage bootloader (SSBL) daga na'urar taya zuwa RAM na waje ko Cache. Na'urar taya za ta iya zama eNVM ko saka microcontroller (eMMC) ko Flash SPI na waje. SSBL yana ɗaukar tsarin aiki na Linux daga na'urar taya zuwa RAM na waje. A cikin stage, Linux ana kashe shi daga RAM na waje.
Hoto mai zuwa yana nuna kwararar Tsarin Boot na Linux.
Hoto 8 • Gudun Tsarin Boot na Linux Na Musamman
Cikakkun bayanai na FSBL, Bishiyar Na'ura, Linux, da ginin YOCTO, yadda ake ginawa da daidaita Linux za a bayar da su a cikin sakin wannan takaddar nan gaba.
AMP Aikace-aikace
Cikakken bayanin Configurator na Libero MSS da yadda ake zana aikace-aikacen masu sarrafawa da yawa ta amfani da SoftConsole za a samar da su a cikin sakin wannan takaddar nan gaba.
Daban-daban Sources na Booting
Don sabuntawa a cikin sigogin wannan takaddar nan gaba.
Kanfigareshi
Don sabuntawa a cikin sigogin wannan takaddar nan gaba.
Acronyms
Ana amfani da gajarce masu zuwa a cikin wannan takarda.
Table 1 • Jerin Gagarabadau
An Fadada Acronym
- AMP Asymmetric Multi-processing
- DTM Data Tightly Integrated Memory (wanda kuma ake kira SRAM)
- Farashin ECDSA Elliptic Curve Digital Sa hannu Algorithm
- eNVM Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa
- Farashin FSBL Farkon Stage Boot Loader
- Hart Hardware thread/core/processor core
- MSS Subsystem na Microprocessor
- BATSA Wutar Sake saiti
- PUF Aiki mara nauyi na jiki
- ROM Ƙwaƙwalwar Ƙwaƙwalwar Karatu kawai
- Rahoton da aka ƙayyade na SCB Gadar Mai Kula da Tsarin
- sNVM Amintaccen Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa
Tarihin Bita
Tarihin bita ya bayyana canje-canjen da aka aiwatar a cikin takaddar. Canje-canjen an jera su ta bita, farawa da ɗaba'ar yanzu.
Bita 2.0
Mai zuwa shine taƙaitaccen canje-canjen da aka yi a cikin wannan bita.
- An sabunta bayanai game da Factory Secure Boot.
- An sabunta bayanai game da Bare Metal Application.
Bita 1.0
Buga na farko na wannan takarda.
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Microchip UG0881 PolarFire SoC FPGA Booting Da Kanfigareshan [pdf] Jagorar mai amfani UG0881 PolarFire SoC FPGA Booting & Kanfigareshan, UG0881, PolarFire SoC FPGA Booting da Kanfigareshan, Booting da Kanfigareshan |
