intel FPGA Programmable Acceleration Card N3000 Board Management Controller
Intel FPGA Programmable Acceleration Card N3000 BMC Introduction
No keia Palapala
E kuhikuhi i ka Intel FPGA Programmable Acceleration Card N3000 Board Management User Guide e aʻo hou e pili ana i nā hana a me nā hiʻohiʻona o ka Intel® MAX® 10 BMC a e hoʻomaopopo i ka heluhelu ʻana i ka ʻikepili telemetry ma ka Intel FPGA PAC N3000 me ka hoʻohana ʻana iā PLDM ma luna o MCTP SMBus a me I2C SMBus. . Hoʻokomo ʻia kahi hoʻolauna i Intel MAX 10 kumu o ka hilinaʻi (RoT) a me ka hoʻonui ʻana i ka ʻōnaehana mamao.
Pauview
ʻO ka Intel MAX 10 BMC ke kuleana no ka mālama ʻana, ka nānā ʻana a me ka hāʻawi ʻana i ke komo i nā hiʻohiʻona papa. Hoʻopili ka Intel MAX 10 BMC me nā mea ʻike ma luna o ka papa, ka FPGA a me ka uila, a hoʻokele i nā kaʻina mana-on/power-off, hoʻonohonoho FPGA a me ke koho balota telemetry. Hiki iā ʻoe ke kamaʻilio me ka BMC me ka hoʻohana ʻana i ke kaʻina 1.1.1 protocol Platform Level Data Model (PLDM). Hiki ke hoʻonui ʻia ka BMC firmware ma luna o PCIe me ka hoʻohana ʻana i ka hiʻohiʻona ʻōnaehana mamao.
Nā hiʻohiʻona o BMC
- Hana ma ke ʻano he Root of Trust (RoT) a hiki i nā hiʻohiʻona hoʻoponopono palekana o ka Intel FPGA PAC N3000.
- Kāohi i ka firmware a me ka FPGA flash update ma luna o PCIe.
- Hoʻoponopono i ka hoʻonohonoho FPGA.
- Hoʻonohonoho i nā hoʻonohonoho pūnaewele no ka C827 Ethernet re-time device.
- Nā Mana Mana e hoʻonui a hoʻohaʻahaʻa i ke kaʻina hana a me ka ʻike hewa me ka pale pani ʻakomi.
- Hoʻomalu i ka mana a hoʻihoʻi hou i ka papa.
- Nā kikowaena me nā mea ʻike, FPGA flash a me QSFPs.
- Nānā i ka ʻikepili telemetry (ka wela o ka papa, voltage a me kēia manawa) a hāʻawi i ka hana pale i ka wā e heluhelu ai ma waho o ka paepae koʻikoʻi.
- Hōʻike i ka ʻikepili telemetry e hoʻokipa iā BMC ma o Platform Level Data Model (PLDM) ma luna o MCTP SMBus a i ʻole I2C.
- Kākoʻo iā PLDM ma luna o MCTP SMBus ma o PCIe SMBus. ʻO 0xCE kahi helu kauā 8-bit.
- Kākoʻo iā I2C SMBus. ʻO 0xBC ka helu kauā 8-bit.
- Loaʻa i nā leka uila Ethernet MAC ma EEPROM a me ka EEPROM hiki ke hoʻololi i ka ʻāpana (FRUID) EEPROM.
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
BMC Kiʻekiʻe-Kiʻekiʻe Block Kiʻi
Ke kumu o ka hilinaʻi (RoT)
Hana ʻia ka Intel MAX 10 BMC ma ke ʻano he Root of Trust (RoT) a hiki i ka hiʻohiʻona hoʻoponopono ʻōnaehana mamao palekana o ka Intel FPGA PAC N3000. Loaʻa i ka RoT nā hiʻohiʻona e hiki ke kōkua i ka pale ʻana i kēia:
- Hoʻouka a hoʻokō ʻana i nā code a i ʻole nā hoʻolālā ʻae ʻole
- Nā hana hoʻopilikia i hoʻāʻo ʻia e nā polokalamu pono ʻole, lako polokalamu pono, a i ʻole ka BMC host
- ʻO ka hoʻokō ʻole ʻia o nā code kahiko a i ʻole nā hoʻolālā me nā pōpoki i ʻike ʻia a i ʻole nā nāwaliwali ma o ka hiki ʻana i ka BMC ke hoʻopau i ka mana.
Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller alakaʻi hoʻohana
Hoʻoikaika pū ka Intel FPGA PAC N3000 BMC i kekahi mau kulekele palekana ʻē aʻe e pili ana i ke komo ʻana ma o nā ʻokoʻa like ʻole, a me ka pale ʻana i ka uila ma luna o ka papa ma o ka palena helu kākau. E ʻoluʻolu e nānā i ka Intel FPGA Programmable Acceleration Card N3000 Security User Guide no ka ʻike e pili ana i ka RoT a me nā hiʻohiʻona palekana o ka Intel FPGA PAC N3000.
ʻIke pili
Intel FPGA Programmable Acceleration Card N3000 Security User Guide
Hoʻohou Pūnaehana mamao palekana
Kākoʻo ka BMC iā Secure RSU no ka Intel MAX 10 BMC Nios® firmware a me RTL kiʻi a me Intel Arria® 10 FPGA kiʻi hou me ka hōʻoia a me ka nānā pono. ʻO ka firmware Nios ke kuleana o ka hōʻoia ʻana i ke kiʻi i ka wā o ka hana hou. Hoʻokomo ʻia nā mea hou ma luna o ka interface PCIe i ka Intel Arria 10 GT FPGA, a ʻo ia hoʻi e kākau iā ia ma luna o ka haku Intel Arria 10 FPGA SPI i ke kauā Intel MAX 10 FPGA SPI. ʻO kahi wahi uila pōkole i kapa ʻia ʻo staghale kūʻai kekahi ʻano o ka bitstream hōʻoia ma o ka interface SPI. Aia ka hoʻolālā BMC RoT i ka module cryptographic e hoʻokō ana i ka hana hōʻoia hash SHA2 256 bit a me ka hana hōʻoia hōʻailona ECDSA 256 P 256 e hōʻoia i nā kī a me ke kiʻi mea hoʻohana. Hoʻohana ʻo Nios firmware i ka module cryptographic e hōʻoia i ke kiʻi i kau inoa ʻia e ka mea hoʻohana ma ka stagʻāpana ʻāina. Inā hala ka hōʻoiaʻiʻo, e kope ka Nios firmware i ke kiʻi mea hoʻohana i ka wahi flash mea hoʻohana. Inā hāʻule ka hōʻoia, hōʻike ka Nios firmware i kahi hewa. E ʻoluʻolu e nānā i ka Intel FPGA Programmable Acceleration Card N3000 Security User Guide no ka ʻike e pili ana i ka RoT a me nā hiʻohiʻona palekana o ka Intel FPGA PAC N3000.
ʻIke pili
Intel FPGA Programmable Acceleration Card N3000 Security User Guide
Mana Mana Mana
Mālama ka mīkini mokuʻāina ʻo BMC Power sequencer i ka Intel FPGA PAC N3000 i ka mana a me ka mana hoʻopau no nā hihia kihi i ka wā o ka hana mana a i ʻole ka hana maʻamau. Hoʻopili ka mana o Intel MAX 10 i ke kaʻina holoʻokoʻa me ka Intel MAX 10 boot-up, Nios boot-up, a me ka hoʻokele mana o ka mana no ka hoʻonohonoho FPGA. Pono ka mea hoʻokipa e nānā i nā mana kūkulu o ka Intel MAX 10 a me ka FPGA, a me ke kūlana Nios ma hope o kēlā me kēia mana-pōkole, a e hana i nā hana like inā e holo ka Intel FPGA PAC N3000 i nā hihia kihi e like me ka Intel MAX 10 a i ʻole. Hoʻokumu ka hale hana FPGA i ka hāʻule ʻana o ka ukana a i ʻole Nios boot up hemahema. Mālama ka BMC i ka Intel FPGA PAC N3000 ma ka pani ʻana i ka mana i ke kāleka ma lalo o kēia mau kūlana:
- 12 V Auxiliary a i ʻole PCIe edge supply voltagaia ma lalo o 10.46 V
- ʻO ka wela kumu o FPGA a hiki i 100°C
- Hiki i ka mahana o ka papa ke 85 °C
Nānā Papa ma o nā mea ʻike
Ke nānā nei ka Intel MAX 10 BMC i ka voltage, ka manawa a me ka mahana o nā ʻāpana like ʻole ma ka Intel FPGA PAC N3000. Hiki i ka Host BMC ke komo i ka ʻikepili telemetry ma o PCIe SMBus. ʻO ka PCIe SMBus ma waena o ka host BMC a me Intel FPGA PAC N3000 Intel MAX 10 BMC e kaʻana like ʻia e ka PLDM ma luna o ka MCTP SMBus endpoint a me ke kauā I2C maʻamau i Avalon-MM interface (heluhelu-wale).
Nānā Papa ma o PLDM ma luna o MCTP SMBus
Ke kamaʻilio nei ka BMC ma Intel FPGA PAC N3000 me kahi kikowaena BMC ma luna o ka PCIe* SMBus. Kākoʻo ka mea hoʻoponopono MCTP i ka Platform Level Data Model (PLDM) ma luna o ka waihona Management Component Transport Protocol (MCTP). ʻO 0xCE ka helu wahi kauā hope MCTP ma ka paʻamau. Hiki ke hoʻonohonoho hou ʻia i loko o ka ʻāpana like o waho FPGA Quad SPI flash ma ke ala i-band inā pono. Kākoʻo ka Intel FPGA PAC N3000 BMC i kahi ʻāpana o nā kauoha PLDM a me MCTP e hiki ai i kahi server BMC ke kiʻi i ka ʻikepili sensor e like me vol.tage, kēia manawa a me ka mahana.
Nānā:
Kākoʻo ʻia ʻo Platform Level Data Model (PLDM) ma luna o MCTP SMBus endpoint. ʻAʻole kākoʻo ʻia ʻo PLDM ma luna o MCTP ma o PCIe maoli. Kākoʻo ʻia ʻo SMBus device category: "Fixed not Discoverable" i kākoʻo ʻia e ka paʻamau, akā kākoʻo ʻia nā ʻāpana ʻehā āpau a hiki ke hoʻonohonoho hou ʻia. Kākoʻo ʻia ʻo ACK-Poll
- Kākoʻo ʻia me ka helu kauā paʻamau SMBus 0xCE.
- Kākoʻo ʻia me kahi helu kauā paʻa a i hāʻawi ʻia.
Kākoʻo ka BMC i ka mana 1.3.0 o ka Management Component Transport Protocol (MCTP) Base Specification (DTMF specification DSP0236), version 1.1.1 o ka PLDM for Platform Monitoring and Control standard (DTMF specification DSP0248), a me ka version 1.0.0 o ka PLDM no ka Mana Manaʻo a me ka ʻIke (DTMF kikoʻī DSP0240).
ʻIke pili
Distributed Management Task Force (DMTF) Nā kikoʻī No ka loulou i nā kikoʻī DMTF kikoʻī
SMBus Interface Speed
Kākoʻo ka hoʻokō Intel FPGA PAC N3000 i nā kālepa SMBus ma 100 KHz ma ke ʻano maʻamau.
Kākoʻo MCTP Packetization
MCTP Wehewehe
- Hōʻike ke kino memo i ka uku o ka memo MCTP. Hiki i ke kino memo ke kau i nā ʻeke MCTP he nui.
- MCTP packet payload pili i ka hapa o ke kino memo o ka memo MCTP i laweia ma ka puolo MCTP hookahi.
- ʻO ka Unit Transmission e pili ana i ka nui o ka ʻāpana o ka ʻeke ʻeke MCTP.
Nui o ka Unite Hoʻouna
- He 64 paita ka nui o ka wae hoʻouna kumu (kahi liʻiliʻi liʻiliʻi) no MCTP.
- Pono nā leka hoʻomalu MCTP a pau e loaʻa i kahi ʻeke ʻeke ʻeke ʻaʻole i ʻoi aku ka nui ma mua o ka ʻāpana hoʻouna kumu me ka ʻole o ke kūkākūkā ʻana. (ʻO ke ʻano kūkākūkā no nā ʻāpana hoʻouna ʻoi aku ka nui ma waena o nā hopena he ʻano memo-specific a ʻaʻole i ʻōlelo ʻia ma ka kikoʻī MCTP Base)
- ʻO kēlā me kēia memo MCTP nona ka nui o ke kino memo i ʻoi aku ma mua o 64 paita e māhele ʻia i mau ʻeke no ka hoʻouna ʻana i hoʻokahi memo.
Nā Māhele Pakeke MCTP
Māhele Puke/Memo maʻamau
Kākoʻo ʻia nā kauoha kauoha
Kākoʻo ʻia nā kauoha MCTP
- E kiʻi i ke kākoʻo MCTP Version
- Base Spec Version Info
- ʻIkepili Mana Mana Mana
- PLDM ma luna o MCTP Version
- E hoʻopaʻa i ka ID helu hope
- E kiʻi i ka ID Endpoint
- E kiʻi i ka UUID Endpoint
- Loaʻa i ke kākoʻo ʻano memo
- E kiʻi i ke kākoʻo memo i wehewehe ʻia e ka mea kūʻai aku
Nānā:
No ka loaʻa ʻana o ke kauoha Kākoʻo Memo Kūʻai Kūʻai, pane ka BMC me ke code hoʻopau ERROR_INVALID_DATA(0x02).
Kākoʻo ʻia ʻo PLDM Base Specification Commands
- SetTID
- GetTID
- LoaʻaPLDMVersion
- Loaʻa i nā ʻano PLDMT
- E kiʻi i nā KauohaPLDM
Kākoʻo ʻia ʻo PLDM no ka nānā ʻana a me nā kauoha kikoʻī hoʻokele
- SetTID
- GetTID
- GetSensorReading
- GetSensorThresholds
- SetSensorThresholds
- Loaʻa iā PDRRepositoryInfo
- Loaʻa iā PDR
Nānā:
ʻO ka BMC Nios II koho nui no ka ʻikepili telemetry ʻokoʻa i kēlā me kēia 1 milliseconds, a ʻo ka lōʻihi o ke koho balota ʻana ma kahi o 500~800 milliseconds, no laila ka pane pane me ka memo noi e pili ana i ke kauoha GetSensorReading a i ʻole GetSensorThresholds e like me nā mea hou i kēlā me kēia 500~800 milliseconds.
Nānā:
ʻAʻole kākoʻo ʻia ʻo GetStateSensorReadings.
PLDM Topology and Hierarchy
ʻO nā moʻolelo wehewehe wehewehe papa
Hoʻohana ka Intel FPGA PAC N3000 i 20 Platform Descriptor Records (PDRs). Kākoʻo ʻo Intel MAX 10 BMC i nā PDR i hoʻohui ʻia kahi e hoʻohui ʻole ʻia ai nā PDR i ka wā i hoʻopili ʻia a wehe ʻia ai ka QSFP. Ke wehe ʻia ke kūlana hana sensor e hōʻike wale ʻia ʻaʻole i loaʻa.
Nā inoa sensor a me ka hoʻopaʻa lima
Hāʻawi ʻia nā PDR āpau i kahi waiwai helu opaque i kapa ʻia ʻo Record Handle. Hoʻohana ʻia kēia waiwai no ke komo ʻana i nā PDR pākahi i loko o ka PDR Repository ma o GetPDR (DTMF specification DSP0248). ʻO ka papa ma lalo nei kahi papa inoa o nā mea ʻike i nānā ʻia ma Intel FPGA PAC N3000.
PDRs Sensor Names and Record Handle
| Hana | Ka inoa ʻike | ʻIkepili Nani | PLDM | ||
| Punae Heluhelu (Hāhui) | PDR
Hoʻopaʻa moʻolelo |
Nā paepae ma PDR | Hoʻololi ka paepae ʻae ʻia ma o PLDM | ||
| Huina mana komo Intel FPGA PAC | Papa Mana | E helu mai nā manamana lima PCIe 12V i kēia manawa a me ka Voltage | 1 | 0 | ʻAʻole |
| Nā manamana lima PCIe 12 V i kēia manawa | 12 V Backplane i kēia manawa | PAC1932 SENSE1 | 2 | 0 | ʻAʻole |
| Nā manamana lima PCIe 12 V Voltage | 12 V Backplane Voltage | PAC1932 SENSE1 | 3 | 0 | ʻAʻole |
| 1.2 V Rail Voltage | 1.2 V Voltage | MAX10 ADC | 4 | 0 | ʻAʻole |
| 1.8 V Rail Voltage | 1.8 V Voltage | MAX 10 ADC | 6 | 0 | ʻAʻole |
| 3.3 V Rail Voltage | 3.3 V Voltage | MAX 10 ADC | 8 | 0 | ʻAʻole |
| FPGA Core Voltage | FPGA Core Voltage | LTC3884 (U44) | 10 | 0 | ʻAʻole |
| FPGA Core i kēia manawa | FPGA Core i kēia manawa | LTC3884 (U44) | 11 | 0 | ʻAʻole |
| FPGA Core Mahana | FPGA Core Mahana | FPGA temp diode ma o TMP411 | 12 | 'Ōlelo Aʻo luna: 90
ʻO luna make: 100 |
ʻAe |
| Ka Mahana Papa | Ka Mahana Papa | TMP411 (U65) | 13 | 'Ōlelo Aʻo luna: 75
ʻO luna make: 85 |
ʻAe |
| QSFP0 Puketage | QSFP0 Puketage | ʻĀpana QSFP waho (J4) | 14 | 0 | ʻAʻole |
| QSFP0 Mahana | QSFP0 Mahana | ʻĀpana QSFP waho (J4) | 15 | 'Ōlelo Aʻo Kiʻekiʻe: Ka waiwai i hoʻonoho ʻia e QSFP Vendor
ʻO ka make ma luna: ka waiwai i hoʻonoho ʻia e QSFP Vendor |
ʻAʻole |
| PCIe Auxiliary 12V i kēia manawa | 12 V AUX | PAC1932 SENSE2 | 24 | 0 | ʻAʻole |
| ʻO PCIe Auxiliary 12V Voltage | 12 V AUX Voltage | PAC1932 SENSE2 | 25 | 0 | ʻAʻole |
| QSFP1 Puketage | QSFP1 Puketage | ʻĀpana QSFP waho (J5) | 37 | 0 | ʻAʻole |
| QSFP1 Mahana | QSFP1 Mahana | ʻĀpana QSFP waho (J5) | 38 | 'Ōlelo Aʻo Kiʻekiʻe: Ka waiwai i hoʻonoho ʻia e QSFP Vendor
ʻO ka make ma luna: ka waiwai i hoʻonoho ʻia e QSFP Vendor |
ʻAʻole |
| PKVL He Mahana Koi | PKVL He Mahana Koi | Kipa PKVL (88EC055) (U18A) | 44 | 0 | ʻAʻole |
| hoʻomau… | |||||
| Hana | Ka inoa ʻike | ʻIkepili Nani | PLDM | ||
| Punae Heluhelu (Hāhui) | PDR
Hoʻopaʻa moʻolelo |
Nā paepae ma PDR | Hoʻololi ka paepae ʻae ʻia ma o PLDM | ||
| PKVL A Serdes Mahana | PKVL A Serdes Mahana | Kipa PKVL (88EC055) (U18A) | 45 | 0 | ʻAʻole |
| PKVL B kumu wela wela | PKVL B kumu wela wela | Kipa PKVL (88EC055) (U23A) | 46 | 0 | ʻAʻole |
| PKVL B Serdes Mahana | PKVL B Serdes Mahana | Kipa PKVL (88EC055) (U23A) | 47 | 0 | ʻAʻole |
Nānā:
ʻO ka Upper Warning a me Upper Fatal waiwai no QSFP i hoʻonohonoho ʻia e ka mea kūʻai aku QSFP. E nānā i ka ʻikepili mea kūʻai aku no nā waiwai. E heluhelu ka BMC i kēia mau waiwai paepae a hōʻike mai. ʻO ka fpgad kahi lawelawe e hiki ke kōkua iā ʻoe e pale i ke kikowaena mai ka hāʻule ʻana i ka wā e hiki ai ka hāmeʻa i kahi paepae sensor hiki ʻole ke hoʻihoʻi ʻia a haʻahaʻa paha (i kapa ʻia ʻo fatal threshold). Hiki iā fpgad ke nānā i kēlā me kēia o nā mea ʻike 20 i hōʻike ʻia e ka Board Management Controller. E ʻoluʻolu e nānā i ke kumuhana Graceful Shutdown mai Intel Acceleration Stack User Guide: Intel FPGA Programmable Acceleration Card N3000 no ka ʻike hou aku.
Nānā:
Pono nā ʻōnaehana kikowaena OEM kūpono e hāʻawi i ka hoʻoluʻu pono no kāu mau haʻahaʻa hana. Hiki iā ʻoe ke loaʻa nā waiwai o nā mea ʻike ma ka holo ʻana i kēia kauoha OPAE ma ke kumu a i ʻole sudo: $ sudo fpgainfo bmc
ʻIke pili
Ke alakaʻi hoʻohana o Intel Acceleration Stack: Intel FPGA Programmable Acceleration Card N3000
Nānā Papa ma o I2C SMBus
ʻO ke kauā I2C maʻamau i Avalon-MM interface (heluhelu-wale nō) kaʻana i ka PCIe SMBus ma waena o ka BMC host a me ka Intel MAX 10 RoT. Kākoʻo ka Intel FPGA PAC N3000 i ke kikowaena kauā I2C maʻamau a ʻo ka helu kauā ʻo 0xBC ma ka paʻamau no ke komo ʻana i waho o ka hui. ʻO ke ʻano hoʻopuka helu ʻana he 2-byte offset mode address. Eia ka palapala hoʻomanaʻo hoʻopaʻa inoa telemetry e hiki iā ʻoe ke hoʻohana i ka ʻike ma o nā kauoha I2C. Hōʻike ke kolamu wehewehe pehea e hoʻoponopono hou ʻia ai nā koina inoa i hoʻihoʻi ʻia no ka loaʻa ʻana o nā waiwai maoli. Hiki i nā ʻāpana ke Celsius (°C), mA, mV, mW ma muli o ka mea ʻike āu e heluhelu ai.
Palapala Hoʻomanaʻo ʻIkepili Telemetry
| Kakau inoa | Offset | Laulā | Komo | Kihapai | Waiwai Paʻamau | wehewehe |
| Ka Mahana Papa | 0x100 | 32 | RO | [31:0] | 32'h00000000 | TMP411(U65)
Hoʻopaʻa inoa ʻia ka helu integer Temperature = helu helu waiwai * 0.5 |
| Wela Kiekie Papa | 0x104 | 32 | RW | [31:0] | 32'h00000000 | TMP411(U65)
ʻO ka waiwai hoʻopaʻa inoa he helu helu |
| Ka palena kiʻekiʻe = helu helu waiwai
* 0.5 |
||||||
| Ka Mahana Papa Kiekie Make | 0x108 | 32 | RW | [31:0] | 32'h00000000 | TMP411(U65)
ʻO ka waiwai hoʻopaʻa inoa he helu helu |
| Kiʻekiʻe koʻikoʻi = helu helu waiwai
* 0.5 |
||||||
| FPGA Core Mahana | 0x110 | 32 | RO | [31:0] | 32'h00000000 | TMP411(U65)
ʻO ka waiwai hoʻopaʻa inoa he helu helu |
| Mahana = helu helu waiwai
* 0.5 |
||||||
| FPGA Make
Wela Kiekie |
0x114 | 32 | RW | [31:0] | 32'h00000000 | TMP411(U65)
ʻO ka waiwai hoʻopaʻa inoa he helu helu |
| Ka palena kiʻekiʻe = helu helu waiwai
* 0.5 |
||||||
| hoʻomau… | ||||||
| Kakau inoa | Offset | Laulā | Komo | Kihapai | Waiwai Paʻamau | wehewehe |
| FPGA Core Voltage | 0x13C. | 32 | RO | [31:0] | 32'h00000000 | LTC3884(U44)
Voltage(mV) = helu helu |
| FPGA Core i kēia manawa | 0x140 | 32 | RO | [31:0] | 32'h00000000 | LTC3884(U44)
ʻO kēia manawa(mA) = helu helu |
| 12v Backplane Voltage | 0x144 | 32 | RO | [31:0] | 32'h00000000 | Voltage(mV) = helu helu |
| 12v Backplane i kēia manawa | 0x148 | 32 | RO | [31:0] | 32'h00000000 | ʻO kēia manawa(mA) = helu helu |
| 1.2v Voltage | 0x14C. | 32 | RO | [31:0] | 32'h00000000 | Voltage(mV) = helu helu |
| 12v Aux Voltage | 0x150 | 32 | RO | [31:0] | 32'h00000000 | Voltage(mV) = helu helu |
| 12v Aux i kēia manawa | 0x154 | 32 | RO | [31:0] | 32'h00000000 | ʻO kēia manawa(mA) = helu helu |
| 1.8v Voltage | 0x158 | 32 | RO | [31:0] | 32'h00000000 | Voltage(mV) = helu helu |
| 3.3v Voltage | 0x15C. | 32 | RO | [31:0] | 32'h00000000 | Voltage(mV) = helu helu |
| Papa Mana | 0x160 | 32 | RO | [31:0] | 32'h00000000 | Mana(mW) = helu helu |
| PKVL He Mahana Koi | 0x168 | 32 | RO | [31:0] | 32'h00000000 | PKVL1(U18A)
ʻO ka waiwai hoʻopaʻa inoa he helu helu Mahana = helu helu waiwai * 0.5 |
| PKVL A Serdes Mahana | 0x16C. | 32 | RO | [31:0] | 32'h00000000 | PKVL1(U18A)
ʻO ka waiwai hoʻopaʻa inoa he helu helu Mahana = helu helu waiwai * 0.5 |
| PKVL B kumu wela wela | 0x170 | 32 | RO | [31:0] | 32'h00000000 | PKVL2(U23A)
ʻO ka waiwai hoʻopaʻa inoa he helu helu Mahana = helu helu waiwai * 0.5 |
| PKVL B Serdes Mahana | 0x174 | 32 | RO | [31:0] | 32'h00000000 | PKVL2(U23A)
ʻO ka waiwai hoʻopaʻa inoa he helu helu Mahana = helu helu waiwai * 0.5 |
Loaʻa nā waiwai QSFP ma ka heluhelu ʻana i ka module QSFP a me ka hōʻike ʻana i nā waiwai heluhelu ma ka papa inoa kūpono. Inā ʻaʻole kākoʻo ka module QSFP i ka Digital Diagnostics Monitoring a i ʻole i hoʻokomo ʻia ka module QSFP, a laila e haʻalele i nā waiwai i heluhelu ʻia mai nā papa inoa QSFP. E hoʻohana i ka mea hana Intelligent Platform Management Interface (IPMI) e heluhelu i ka ʻikepili telemetry ma o ka pahi I2C.
Kauoha I2C e heluhelu i ka wela o ka papa ma ka helu 0x100:
Ma ke kauoha ma lalo nei:
- ʻO 0x20 ka helu kaʻa kaʻa I2C o kāu kikowaena hiki ke komo pololei i nā slot PCIe. He ʻokoʻa kēia helu wahi me ke kikowaena. E ʻoluʻolu e nānā i kāu ʻikepili kikowaena no ka helu I2C pololei o kāu kikowaena.
- ʻO 0xBC ka helu kauā I2C o ka Intel MAX 10 BMC.
- ʻO 4 ka helu o nā bytes ʻikepili heluhelu
- ʻO 0x01 0x00 ka helu helu helu o ka mahana o ka papa i hōʻike ʻia ma ka papa.
Kauoha:
ipmitool i2c bus=0x20 0xBC 4 0x01 0x00
Puka:
01110010 00000000 00000000 00000000
ʻO ka waiwai hoʻopuka ma ka hexidecimal: 0x72000000 0x72 he 114 i ka decimal. No ka helu ʻana i ka mahana ma Celsius e hoʻonui i ka 0.5: 114 x 0.5 = 57 °C
Nānā:
ʻAʻole kākoʻo nā kikowaena āpau i ka pahi I2C i ke komo pololei ʻana i nā slot PCIe. E ʻoluʻolu e nānā i kāu ʻikepili kikowaena no ka ʻike kākoʻo a me ka helu wahi kaʻa kaʻa I2C.
Hōʻikeʻike EEPROM
Hōʻike kēia ʻāpana i ke ʻano ʻikepili o ka MAC Address EEPROM a me ka FRUID EEPROM a hiki ke kiʻi ʻia e ka mea hoʻokipa a me FPGA.
MAC EEPROM
I ka manawa o ka hana ʻana, hoʻolālā ʻo Intel i ka leka uila MAC EEPROM me nā leka uila Intel Ethernet Controller XL710-BM2 MAC. Loaʻa ka Intel MAX 10 i nā helu wahi ma ka helu MAC address EEPROM ma o ka pahi I2C. E ʻike i ka helu MAC me ka hoʻohana ʻana i kēia kauoha: $ sudo fpga mac
Aia i loko o ka MAC Address EEPROM ka helu MAC 6-byte hoʻomaka ma ka helu helu 0x00h a ukali ʻia e ka helu helu MAC o 08. Ua paʻi pū ʻia ka helu MAC hoʻomaka ma ka lepili ma ka ʻaoʻao hope o ka Printed Circuit Board (PCB). Hāʻawi ka mea hoʻokele OPAE i nā pūnana sysfs no ka loaʻa ʻana o ka helu MAC hoʻomaka mai kēia wahi: /sys/class/fpga/intel-fpga-dev.*/intel-fpga-fme.*/spi altera.*.auto/spi_master/ spi */spi*/mac_address Hoʻomaka MAC Address Example: 644C360F4430 Loaʻa i ka mea hoʻokele OPAE ka helu mai kēia wahi: /sys/class/fpga/ intel-fpga-dev.*/intel-fpga-fme.*/spi-altera.*.auto/spi_master/ spi*/ spi*/mac_count helu MAC Example: 08 Mai ka helu MAC hoʻomaka, loaʻa nā helu MAC ʻehiku i koe ma ka hoʻonui ʻana i ka Least Significant Byte (LSB) o ka ʻōlelo MAC hoʻomaka ma ka helu hoʻokahi no kēlā me kēia helu MAC ma hope. ʻO ka helu MAC hope example:
- 644C360F4431
- 644C360F4432
- 644C360F4433
- 644C360F4434
- 644C360F4435
- 644C360F4436
- 644C360F4437
Nānā: Inā ʻoe e hoʻohana nei i kahi ES Intel FPGA PAC N3000, ʻaʻole i hoʻolālā ʻia ka MAC EEPROM. Inā ʻaʻole i hoʻolālā ʻia ka MAC EEPROM a laila hoʻi ka helu helu MAC mua e like me FFFFFFFFFFFF.
Māhele Hiki ke hoʻololi i ka ʻike ʻana (FRUID) EEPROM Access
Hiki iā ʻoe ke heluhelu wale i ke kahua e hoʻololi ai i ka ʻāpana ʻike (FRUID) EEPROM (0xA0) mai ka BMC host ma o SMBus. Hoʻokumu ʻia ke ʻano o ka FRUID EEPROM ma ke kikoʻī IPMI, Platform Management FRU Information Storage Definition, v1.3, Malaki 24, 2015, kahi i loaʻa ai kahi ʻano ʻike papa. Hoʻopili ka FRUID EEPROM i ka hōʻano poʻomanaʻo maʻamau me ka Area Board a me ka Area Info Product. E nānā i ka papa ma lalo no nā kahua o ke poʻo maʻamau e pili ana i ka FRUID EEPROM.
Poʻomanaʻo maʻamau o FRUID EEPROM
Pono nā kahua āpau ma ke poʻo maʻamau.
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai EEPROM FRUID |
|
1 |
Manaʻo Poʻomanaʻo maʻamau Version 7:4 – mālama ʻia, kākau e like me 0000b
3:0 - ka helu helu helu = 1h no kēia kikoʻī |
01h (Hoʻonoho ʻia ma 00000001b) |
|
1 |
Hoʻomaka Hoʻomaka Offset i loko o ka hoʻohana ʻana i loko (ma ka nui o 8 bytes).
Hōʻike ka 00h ʻaʻole kēia wahi. |
00h (ʻaʻole i kēia manawa) |
|
1 |
ʻO Chassis Info Wahi Hoʻomaka Offset (ma ka nui o 8 bytes).
Hōʻike ka 00h ʻaʻole kēia wahi. |
00h (ʻaʻole i kēia manawa) |
|
1 |
ʻAha Papa Hoʻomaka Offset (ma nā pāpaʻi o 8 bytes).
Hōʻike ka 00h ʻaʻole kēia wahi. |
01h |
|
1 |
ʻIke Huahana Wahi Hoʻomaka Offset (ma nā paʻi o 8 bytes).
Hōʻike ka 00h ʻaʻole kēia wahi. |
0Ta |
|
1 |
ʻO ka hoʻomaka ʻana o ka ʻāpana MultiRecord (ma ka nui o 8 bytes).
Hōʻike ka 00h ʻaʻole kēia wahi. |
00h (ʻaʻole i kēia manawa) |
| 1 | PAD, kākau e like me 00h | 00h |
|
1 |
Nānā Poʻomanaʻo maʻamau (zero checksum) |
F2h |
Hoʻokomo ʻia nā byte poʻomanaʻo maʻamau mai ka helu mua o ka EEPROM. ʻO ka hoʻolālā e like me ke kiʻi ma lalo nei.
FRUID EEPROM Hoʻonohonoho Hoʻomanaʻo Paʻa Paʻa
Wahi Papa FRUID EEPROM
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 1 | Papa Hōʻano Papa Papa Manaʻo 7:4 – mālama ʻia, kākau e like me 0000b 3:0 – hōʻano helu helu | 0x01 | Hoʻonoho ʻia i ka hola 1 (0000 0001b) |
| 1 | Ka lōʻihi o ka ʻāpana o ka papa (ma nā pākēneka o 8 bytes) | 0x0B. | 88 bytes (me 2 pad 00 bytes) |
| 1 | Kāhea ʻōlelo | 0x00 | E hoʻonoho i ka 0 no ka ʻōlelo Pelekania
Nānā: ʻAʻohe ʻōlelo ʻē aʻe i kākoʻo ʻia i kēia manawa |
| 3 | Mfg. La / Wā: Ka helu o nā minuke mai 0:00 hola 1/1/96.
Paita liʻiliʻi liʻiliʻi loa (liʻi liʻiliʻi) 00_00_00h = ʻaʻole i hōʻike ʻia (Ke kahua paʻa) |
0x10
0x65 0xB7 |
ʻokoʻa ka manawa ma waena o 12:00 AM 1/1/96 a i 12 PM
ʻO 11/07/2018 ka 12018960 minuke = b76510h – mālama ʻia ma ke ʻano endian liʻiliʻi |
| 1 | Papa Mea Hana ʻAno/lōʻihi byte | 0x2 | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 010010b (18 bytes o ka ʻikepili) |
| P | Papa Mea Hana bytes | 0x49
0x6E 0x74 0x65 0x6C. 0xAE |
8-bit ASCII + LATIN1 i hoʻopaʻa ʻia ʻo Intel® Corporation |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 0x20
0x43 0x6F 0x72 0x70 0x6F 0x72 0x61 0x74 0x69 0x6F 0x6E |
|||
| 1 | Papa inoa inoa ʻano/paita lōʻihi | 0x5 | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 010101b (21 bytes o ka ʻikepili) |
| Q | Paita inoa Huahana Papa | 0X49
0X6E 0X74 0X65 0X6C 0XAE 0X20 0X46 0X50 0X47 0X41 0X20 0X50 0X41 0X43 0X20 0X4E 0X33 0X30 0X30 0X30 |
8-bit ASCII + LATIN1 helu ʻia ʻo Intel FPGA PAC N3000 |
| 1 | ʻAno Papa Serial Number/byte lōʻihi | 0xCC | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 001100b (12 bytes o ka ʻikepili) |
| N | Paina Helu Serial Papa (Kālana Dynamic) | 0x30
0x30 0x30 0x30 0x30 0x30 0x30 0x30 |
8-bit ASCII + LATIN1 helu ʻia
ʻO ka 1 o nā huahelu hex he OUI: 6 ʻO nā helu hex 2nd 6 he helu MAC: 000000 |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 0x30
0x30 0x30 0x30 |
Nānā: Hoʻopili ʻia kēia ma ke ʻano he example a pono e hoʻololi ʻia i kahi mea hana maoli
ʻO ka 1 o nā huahelu hex he OUI: 6C644 ʻO nā helu hex 2nd 6 he helu MAC: 00AB2E Nānā: E ʻike ʻole hoʻonohonoho ʻia ʻo FRUID, hoʻonohonoho i ka helu OUI a me MAC i "0000". |
||
| 1 | ʻAno ʻāpana ʻāpana papa / paita lōʻihi | 0xCE | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 001110b (14 bytes o ka ʻikepili) |
| M | Paina Helu Mahele o ka Papa | 0x4B.
0x38 0x32 0x34 0x31 0x37 0x20 0x30 0x30 0x32 0x20 0x20 0x20 0x20 |
8-bit ASCII + LATIN1 i hoʻopaʻa ʻia me BOM ID.
No ka 14 byte ka lōʻihi, ka helu ʻāpana papa helu exampʻO ka K82417-002 Nānā: Hoʻopili ʻia kēia ma ke ʻano he example a pono e hoʻololi ʻia i kahi mea hana maoli. He ʻokoʻa kēia waiwai kahua me ka helu PBA papa ʻokoʻa. Ua wehe ʻia ka PBA Revision ma FRUID. Hoʻihoʻi ʻole ʻia kēia mau paita hope ʻehā a mālama ʻia no ka hoʻohana ʻana i ka wā e hiki mai ana. |
| 1 | FRU File ʻAno ID/paita lōʻihi | 0x00 | 8-bit ASCII + LATIN1 helu 7:6 – 00b
5:0 – 000000b (0 bytes o ka ʻikepili) ʻO ka FRU File ʻAʻole i hoʻokomo ʻia ke kahua bytes ID e hahai i kēia no ka mea he 'null' ke kahua. Nānā: FRU File Paita ID. ʻO ka FRU File kahua kahua he kahua i wehewehe mua ʻia i hāʻawi ʻia ma ke ʻano he kōkua hana no ka hōʻoia ʻana i ka file i hoʻohana ʻia i ka wā o ka hana ʻana a i ʻole ka hoʻonui ʻana i ke kahua e hoʻouka i ka ʻike FRU. ʻO ka maʻiʻo no ka mea hana. Hāʻawi ʻia kēia kahua ma ka ʻāpana ʻIke Papa. He 'null' paha nā kahua ʻelua a i ʻole. |
| 1 | ʻAno MMID/paita lōʻihi | 0xC6 | 8-bit ASCII + LATIN1 helu ʻia |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 7:6 – 11b
5:0 – 000110b (6 bytes o ka ʻikepili) Nānā: Hoʻopili ʻia kēia ma ke ʻano he example a pono e hoʻololi ʻia i kahi mea hana maoli |
|||
| M | MMID paita | 0x39
0x39 0x39 0x44 0x58 0x46 |
Hoʻopili ʻia e like me 6 mau huahelu hex. Kūkākūkā exampi loko o ke kelepona me ka Intel FPGA PAC N3000 MMID = 999DXF.
ʻOkoʻa kēia waiwai kahua me nā kahua SKU like ʻole e like me MMID, OPN, PBN etc. |
| 1 | C1h (ʻano/lōʻihi byte i hoʻopaʻa ʻia e hōʻike i nā kahua ʻike hou aʻe). | 0xC1 | |
| Y | 00h - ke koena wahi i hoʻohana ʻole ʻia | 0x00 | |
| 1 | Ka helu helu ʻāina ʻo Papa (zero checksum) | 0xB9 | Nānā: ʻO ka checksum ma kēia pākaukau he zero checksum i helu ʻia no nā waiwai i hoʻohana ʻia ma ka pākaukau. Pono e helu hou ʻia no nā waiwai maoli o kahi Intel FPGA PAC N3000. |
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 1 | Hula Huahana Huahana Mana 7:4 – mālama ʻia, e kākau e like me 0000b
3:0 - ka helu helu helu = 1h no kēia kikoʻī |
0x01 | Hoʻonoho ʻia i ka hola 1 (0000 0001b) |
| 1 | Ka lōʻihi o ka ʻāpana huahana (ma nā pākēneka o 8 bytes) | 0x0A | Huina o 80 bytes |
| 1 | Kāhea ʻōlelo | 0x00 | E hoʻonoho i ka 0 no ka ʻōlelo Pelekania
Nānā: ʻAʻohe ʻōlelo ʻē aʻe i kākoʻo ʻia i kēia manawa |
| 1 | ʻAno inoa o ka mea hana/paita lōʻihi | 0x2 | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 010010b (18 bytes o ka ʻikepili) |
| N | Paita inoa o ka mea hana | 0x49
0x6E 0x74 0x65 0x6C. 0xAE 0x20 0x43 0x6F |
8-bit ASCII + LATIN1 i helu ʻia ʻo Intel Corporation |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 0x72
0x70 0x6F 0x72 0x61 0x74 0x69 0x6F 0x6E |
|||
| 1 | ʻAno inoa huahana/paita lōʻihi | 0x5 | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 010101b (21 bytes o ka ʻikepili) |
| M | Paita inoa huahana | 0x49
0x6E 0x74 0x65 0x6C. 0xAE 0x20 0x46 0x50 0x47 0x41 0x20 0x50 0x41 0x43 0x20 0x4E 0x33 0x30 0x30 0x30 |
8-bit ASCII + LATIN1 helu ʻia ʻo Intel FPGA PAC N3000 |
| 1 | ʻĀpana Huahana/Kōkohu helu ʻano/byte lōʻihi | 0xCE | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 001110b (14 bytes o ka ʻikepili) |
| O | ʻĀpana Huahana/Helu Hoʻohālike | 0x42
0x44 0x2D 0x4E 0x56 0x56 0x2D 0x4E 0x33 0x30 0x30 0x30 0x2D 0x31 |
8-bit ASCII + LATIN1 helu ʻia
OPN no ka papa BD-NVV- N3000-1 ʻOkoʻa kēia waiwai kahua me nā ʻokoʻa Intel FPGA PAC N3000 OPN. |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| 1 | ʻAno Huahana/paita lōʻihi | 0x01 | 8-bit binary 7:6 – 00b
5:0 – 000001b (1 byte o ka ʻikepili) |
| R | Hua hua paita | 0x00 | Hoʻopili ʻia kēia kahua ma ke ʻano he lālā ʻohana |
| 1 | ʻAno helu helu huahana/paita lōʻihi | 0xCC | 8-bit ASCII + LATIN1 helu 7:6 – 11b
5:0 – 001100b (12 bytes o ka ʻikepili) |
| P | Paina Helu Serial Huahana | 0x30
0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 |
8-bit ASCII + LATIN1 helu ʻia
ʻO ka 1 o nā huahelu hex he OUI: 6 ʻO nā helu hex 2nd 6 he helu MAC: 000000 Nānā: Hoʻopili ʻia kēia ma ke ʻano he example a pono e hoʻololi ʻia i kahi mea hana maoli. ʻO ka 1 o nā huahelu hex he OUI: 6C644 ʻO nā helu hex 2nd 6 he helu MAC: 00AB2E Nānā: E ʻike ʻole hoʻonohonoho ʻia ʻo FRUID, hoʻonohonoho i ka helu OUI a me MAC i "0000". |
| 1 | Waiwai Tag paita ʻano/lōʻihi | 0x01 | 8-bit binary 7:6 – 00b
5:0 – 000001b (1 byte o ka ʻikepili) |
| Q | Waiwai Tag | 0x00 | ʻAʻole i kākoʻo ʻia |
| 1 | FRU File ʻAno ID/paita lōʻihi | 0x00 | 8-bit ASCII + LATIN1 helu 7:6 – 00b
5:0 – 000000b (0 bytes o ka ʻikepili) ʻO ka FRU File ʻAʻole i hoʻokomo ʻia ke kahua bytes ID e hahai i kēia no ka mea he 'null' ke kahua. |
| hoʻomau… | |||
| Ka lōʻihi o ke kahua ma nā Bytes | Wehewehe kahua | Waiwai kahua | Hoʻopili kahua |
| Nānā: FRU file Paita ID.
ʻO ka FRU File kahua kahua he kahua i wehewehe mua ʻia i hāʻawi ʻia ma ke ʻano he kōkua hana no ka hōʻoia ʻana i ka file i hoʻohana ʻia i ka wā o ka hana ʻana a i ʻole ka hoʻonui ʻana i ke kahua e hoʻouka i ka ʻike FRU. ʻO ka maʻiʻo no ka mea hana. Hāʻawi ʻia kēia kahua ma ka ʻāpana ʻIke Papa. He 'null' paha nā kahua ʻelua a i ʻole. |
|||
| 1 | C1h (ʻano/lōʻihi byte i hoʻopaʻa ʻia e hōʻike i nā kahua ʻike hou aʻe). | 0xC1 | |
| Y | 00h - ke koena wahi i hoʻohana ʻole ʻia | 0x00 | |
| 1 | Nānā Huahana ʻIke Huahana (zero checksum)
(Kānana Paʻa) |
0x9D | Nānā: ʻO ka checksum i loko o kēia pākaukau he zero checksum i helu ʻia no nā waiwai i hoʻohana ʻia ma ka pākaukau. Pono e helu hou ʻia no nā waiwai maoli o kahi Intel FPGA PAC. |
Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller alakaʻi hoʻohana
Moolelo Hooponopono
Moʻolelo Hoʻoponopono no ka Intel FPGA Programmable Acceleration Card N3000 Board Management Controller Guide User Guide
| Palapala Palapala | Nā hoʻololi |
| 2019.11.25 | Hoʻokuʻu Hana Hoʻomaka. |
Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe.
* Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
Palapala / Punawai
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intel FPGA Programmable Acceleration Card N3000 Board Management Controller [pdf] Ke alakaʻi hoʻohana FPGA Programmable Acceleration Card N3000 Papa, Mana Mana Manaʻo, FPGA, Programmable Acceleration Card N3000 Papa, Mana Manaʻo, N3000 Papa Hoʻokele, Mana Mana Mana |
