Altera Cyclone V Hard Processor System Technical Reference Manual
Introduction
The Altera Cyclone V Hard Processor System (HPS) integrates a dual-core ARM® Cortex™-A9 processor with a rich set of peripherals and programmable logic on a single chip. Designed to combine the flexibility of FPGA fabric with the performance and ease-of-use of a hard processor core, it targets applications requiring low power, high efficiency, and cost-effectiveness. It’s commonly used in industrial control, automotive, communications, and embedded systems.
FAQs
What is the Cyclone V HPS?
The Cyclone V HPS is a system on chip SoC that combines ARM Cortex A9 dual-core processors with Altera FPGA fabric in a single chip.
What are the key components of the HPS?
It includes the dual core ARM Cortex A9 processor, SDRAM controller, NAND NOR flash controllers, USB, Ethernet, UART, I2C, SPI, and DMA controllers.
What memory interfaces are supported by Cyclone V HPS?
It supports DDR3 DDR2 LPDDR2 SDRAM via a hard memory controller integrated in the HPS subsystem.
How does the HPS communicate with the FPGA fabric?
Through high-bandwidth interconnects like AXI bridges HPS to FPGA, FPGA to HPS, lightweight bridges, and FPGA to HPS SDRAM access.
What operating systems are compatible with the HPS?
Popular OS options include Linux like Yocto or Debian, FreeRTOS, and bare-metal software via ARM DS 5 or GCC toolchains.
Can I program the FPGA and HPS independently?
Yes, the HPS and FPGA are independent subsystems but tightly integrated. You can boot Linux on the HPS while using the FPGA for real-time logic.
What tools are used to develop for the Cyclone V HPS?
Intel formerly Altera provides Quartus Prime for FPGA design and SoC EDS Embedded Design Suite for ARM development.
How is the Cyclone V HPS powered and clocked?
It uses multiple power rails and allows flexible clocking with PLLs and oscillators shared between FPGA and HPS.
Does it support secure boot or encryption?
Yes, with configuration options, the HPS supports secure boot via encrypted bitstreams and authentication.
What JTAG or debugging options are available?
You can debug via USB Blaster, JTAG, and Serial Wire Debug SWD, and ARM DS 5 debugger or GDB.