Intel FPGA Programmable Kuwedzera Kadhi D5005 Mushandisi Yekushandisa

Iri gwaro rinotsanangura yakananga ndangariro kuwana (DMA) Accelerator Functional Unit (AFU) kuita uye maitiro ekuvaka dhizaini kuti imhanye pane Hardware kana mukuenzanisa.

Vateereri Vanotarisirwa

Vateereri vanotarisirwa vanosanganisira hardware kana vagadziri vesoftware vanoda Accelerator Function (AF) kubhafa data munharaunda mundangariro yakabatana neIntel FPGA mudziyo.

Magungano

Gwaro Kokorodzano

Kokorodzano	Tsanangudzo
#	Inotangira murairo unoratidza kuti murairo unofanira kuiswa semudzi.
$	Inoratidza murairo unofanirwa kuiswa semushandisi.
font iyi	Filemazita, mirairo, uye mazwi makuru anodhindwa mune ino font. Mitsetse yakareba yekuraira inodhindwa mune iyi font. Kunyange zvazvo mitsara yakareba yemirairo inogona kuputira kumutsara unotevera, kudzoka hakusi chikamu chemurairo; usadzvanya Enter.
	Inoratidza mavara echibatiso anooneka pakati pemakona anofanira kutsiviwa neukoshi hwakakodzera. Usaise mabhaketi emakona.

Acronyms

Acronyms	Kuwedzera	Tsanangudzo
AF	Accelerator Basa	Yakasanganiswa Hardware Accelerator mufananidzo wakaiswa muFPGA logic inomhanyisa application.
AFU	Accelerator Inoshanda Chikamu	Hardware Accelerator inoshandiswa muFPGA logic iyo inoburitsa computational mashandiro ekushandisa kubva kuCPU kuti ivandudze mashandiro.
API	Application Programming Interface	Seti ye subroutine tsananguro, mapuroteni, uye maturusi ekuvaka masoftware maapplication.
CCI-P	Core Cache Interface	CCI-P ndiyo yakajairwa interface inoshandiswa neAFU kutaura nemugamuchiri.
DFH	Device Feature Header	Inogadzira rondedzero yakabatana yemusoro wenyaya kuti ipe nzira yakawedzera yekuwedzera maficha.
*akaenderera…*

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Acronyms	Kuwedzera	Tsanangudzo
FIM	FPGA Interface Maneja	Iyo FPGA Hardware ine iyo FPGA Interface Unit (FIU) uye yekunze interfaces yekuyeuka, networking, nezvimwe. Iyo Accelerator Basa (AF) inopindirana neFIM panguva yekumhanya.
FIU	FPGA Interface Unit	FIU ipuratifomu interface layer inoshanda sebhiriji pakati pepuratifomu nzvimbo sePCIe*, UPI neAFU-parutivi nzvimbo dzakaita seCCI-P.
MPF	Memory Properties Factory	MPF iBasic Building Block (BBB) inogona kushandiswa neAFU kupa CCI-P traffic shape operations for transactions neFIU.

Kuwedzeredza Tsanangudzo Yemashoko

Yekumhanyisa Stack yeIntel® Xeon® CPU ine FPGAs Glossary

Term	Kudimbudzira	Tsanangudzo
Intel® Kukwirisa Stack yeIntel Xeon® CPU ine maFPGAs	Acceleration Stack	Muunganidzwa wesoftware, firmware, uye maturusi anopa kuita- optimized kubatana pakati peIntel FPGA neIntel Xeon processor.
Intel FPGA Programmable Kuwedzera Kadhi	Intel FPGA PAC	PCIe FPGA accelerator kadhi. Iine FPGA Interface Manager (FIM) iyo inofamba neIntel Xeon processor pamusoro pePCIe bhazi.

DMA Accelerator Inoshanda Chikamu Chekushandisa Mushandisi: Intel FPGA Inorongeka Inowedzera Kadhi D5005

DMA AFU Tsanangudzo

Nhanganyaya

Iyo Direct Memory Access (DMA) AFU example inoratidza maitiro ekugadzirisa ndangariro kutamiswa pakati peiyo host processor neFPGA. Iwe unogona kubatanidza iyo DMA AFU mudhizaini yako yekufambisa data pakati peiyo host memory uye yeFPGA yemuno ndangariro.DMA AFU ine anotevera submodules:

Memory Properties Factory (MPF) Basic Building Block (BBB)

Core Cache Interface (CCI-P) kuenda kuAvalon® Memory-Mapped (Avalon-MM) Adapter
DMA Test System iyo ine iyo DMA BBB

Aya ma submodule anotsanangurwa zvakadzama muDMA AFU Hardware Components musoro pazasi.

Related Information

Iyo DMA AFU Hardware Zvikamu pane peji 6
Avalon Interface Specifications

Kuti uwane rumwe ruzivo nezve iyo Avalon-MM protocol, kusanganisira yenguva dhayagiramu yekuverenga nekunyora kutengeserana.

Iyo DMA AFU Software Package

Iyo Intel Acceleration Stack yeIntel Xeon CPU ine FPGAs package file (*.tar.gz), inosanganisira iyo DMA AFU example. Ex uyuample inopa mushandisi nzvimbo mutyairi. Iyo yekugamuchira application inoshandisa mutyairi uyu zvekuti DMA inofambisa data pakati pekugamuchira uye FPGA ndangariro. Iwo mabhanari emahara, masosi, uye mutyairi wenzvimbo yemushandisi anowanikwa mune inotevera dhairekitori: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu . Usati waedza neDMA AFU, unofanira kuisa Open Programmable Acceleration Engine (OPAE) software package. Revera Kuisa OPAE Software Package muIntel Kukwirisa Stack Kurumidza Kutanga Gwaro reIntel FPGA Programmable Acceleration Card D5005 yemirairo yekuisa. Iyi Yekukurumidza Kutanga Gwaro inosanganisirawo ruzivo rwekutanga nezve Open Programmable Acceleration Injini (OPAE) uye kugadzirisa AFU. Mushure mekuisa iyo Open Programmable Acceleration Engine (OPAE) software package, seample host application uye DMA AFU mushandisi nzvimbo mutyairi anowanikwa mune inotevera dhairekitori: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw. Kumhanya sample host application, fpga_dma_test pane yako Intel FPGA PAC D5005 hardware, tarisa kune matanho ari muchikamu Kumhanya iyo DMA AFU Ex.ample. Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Related Information

Intel Kukwidziridza Stack Kurumidza Kutanga Nhungamiro yeIntel FPGA Inorongeka Yekumhanyisa Kadhi D5005
Kuisa iyo OPAE Software Package

Iyo DMA AFU Hardware Zvikamu

Iyo DMA AFU inopindirana neFPGA Interface Unit (FIU) uye FPGA ndangariro. Tarisa kune iyo FPGA Interface Maneja Dhata Sheet yeIntel FPGA Programmable Kuwedzera Kadhi D5005 kune yakadzama zvirevo zveFPGA ndangariro. Iyo iripo parizvino hardware inoraira iyi ndangariro kumisikidzwa. Ramangwana Hardware inogona kutsigira ndangariro masisitimu akasiyana. Unogona kushandisa iyo DMA AFU kukopa data pakati peinotevera sosi nenzvimbo dzekuenda:

Iyo saiti kune mudziyo FPGA ndangariro
Mudziyo FPGA ndangariro kumugamuchiri

A Platform Designer system, $OPAE_PLATFORM_ROOT/hw/samples/ dma_afu/hw/rtl/TEST_dma/ /dma_test_system.qsys inoshandisa yakawanda yeDMA

AFU. Chikamu cheDMA AFU chakaitwa muPlatform Designer system chinogona kuwanikwa mune zvinotevera

nzvimbo:$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/ Iwe unogona kuwana iyo DMA BBB munzvimbo inotevera:

$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/dma_bbb

DMA Accelerator Inoshanda Chikamu Chekushandisa Mushandisi: Intel FPGA Inorongeka Inowedzera Kadhi D5005

DMA AFU Hardware Block Diagram

Iyo DMA AFU inosanganisira anotevera emukati mamodule ekubatanidza neFPGA Interface Unit (FIU):

Memory-Mapped IO (MMIO) Decoder Logic: inoona MMIO kuverenga nekunyora kutengeserana uye inoaparadzanisa kubva kuCCI-P RX chiteshi 0 yavanosvika kubva. Izvi zvinova nechokwadi chekuti traffic yeMMIO haimbosviki iyo MPF BBB uye inoshandirwa neyakazvimirira yeMMIO yekuraira chiteshi.
Memory Properties Factory (MPF): module iyi inova nechokwadi chekuti mhinduro dzekuverenga kubva kuDMA inodzoka muhurongwa hwadzakapihwa. Iyo Avalon-MM protocol inoda kuverenga mhinduro kuti idzoke mune kwayo kurongeka.
CCI-P kuenda kuAvalon-MM Adapter: Iyi module inoshandura pakati peCCI-P neAvalon-MM kutengeserana, sezvinotevera:
CCI-P kuenda kuAvalon-MMIO Adapter: Iyi nzira inoshandura CCI-P MMIO transactions muAvalon-MM transactions.
Avalon kuenda kuCCI-P Host Adapter: Idzi nzira dzinogadzira yakaparadzana kuverenga-chete uye kunyora-chete nzira dzeDMA yekuwana ndangariro yekugamuchira.
DMA Test System: Iyi module inoshanda seyakaputira yakatenderedza iyo DMA BBB kufumura maDMA masters kune mamwe ese epfungwa muAFU. Inopa iyo interface pakati peDMA BBB neCCI-P kune Avalon Adapter. Iyo zvakare inopa iyo interface pakati peDMA BBB uye emuno FPGA SDRAM mabhangi.

Related Information
FPGA Interface Maneja Dhata Sheet yeIntel FPGA Programmable Kuwedzera Kadhi D5005

DMA Test System

Iyo DMA bvunzo sisitimu inobatanidza iyo DMA BBB kune yakasara yeFPGA dhizaini inosanganisira CCI-P adapta uye yemuno FPGA ndangariro.

DMA Test System Block Dhiagiramu
Iyi dhizaini dhizaini inoratidza vemukati veiyo DMA test system. Iyo DMA test system inoratidzwa se monolithic block muMufananidzo 1 papeji 7.

Iyo DMA test system inosanganisira anotevera emukati mamodule:

Kure Reach Bridge/Pipeline Bridge: Pombi bhiriji rine inogadziriswa latency inosanganisirwa kudzora topology uye kugadzirisa dhizaini Fmax.

DMA AFU Device Feature Header (DFH): Iyi iDFH yeDMA AFU. Iyi DFH inonongedza kune inotevera DFH iri pa offset 0x100 (DMA BBB DFH).
Null DFH: Ichi chikamu chinomisa iyo DFH yakabatana-rondedzero. Kana iwe ukawedzera mamwe maDMA BBB kudhizaini, ita shuwa kuti iyo null DFH base kero iri kumagumo kweDFH yakabatana-rondedzero.
MA Basic Building Block (BBB): Ichi chivharo chinofambisa data pakati pemugamuchiri uye yemuno FPGA ndangariro. Iyo zvakare inowana host memory kuti iwane descriptor cheni.

DMA BBB

Iyo DMA BBB subsystem inotamisa data kubva kunobva kune kwainoenda kero uchishandisa Avalon-MM transaction. Mutyairi weDMA anodzora iyo DMA BBB nekuwana kutonga uye mamiriro erejista yezvakasiyana zvikamu mukati mehurongwa. Mutyairi weDMA anodzorawo iyo DMA BBB nekushandisa ndangariro yakagovaniswa kutaurirana zvinotsanangurwa zvekufambisa. Iyo DMA BBB inowana data muFPGA ndangariro pakubvisa 0x0. Iyo DMA BBB inowana data uye tsananguro mundangariro yekugamuchira pa offset 0x1_0000_0000_0000.

DMA BBB Platform Designer Block Diagram
Iyi dhizaini dhizaini haisanganisi imwe yemukati Pipeline Bridge IP cores.

DMA Accelerator Inoshanda Chikamu Chekushandisa Mushandisi: Intel FPGA Inorongeka Inowedzera Kadhi D5005

DMA AFU Tsanangudzo

Izvo zvikamu muDMA BBB Platform Dhizaini inoita mabasa anotevera:

Kure Reach Bridge/Pipeline Bridge: Bhiriji repaipi ine inogadziriswa latency inosanganisirwa kudzora topology uye kugadzirisa dhizaini Fmax.
MA BBB DFH: Ichi chigadziriso chemusoro weiyo DMA BBB. Iyi DFH inonongedza kune inotevera DFH iri pa offset 0x100 (Null DFH).
Descriptor Frontend: Basa rekutora zvinotsanangura uye nekuendesa kune Dispatcher. Kana kuendeswa kweDMA kunopedza iyo yekumberi inogamuchira chimiro kubva kuDispatcher uye inonyora iyo descriptor mundangariro yekugamuchira.

Dispatcher: Iyi bhuroka inoronga DMA inotamisa zvikumbiro kuKuverenga uye Nyora Master.
Verenga Master: Iyi block ine basa rekuverenga data kubva kune host kana yemuno FPGA ndangariro uye kuitumira seyekutepfenyura data kuKunyora Master.
Nyora Mudzidzisi: Iyi block ine basa rekugamuchira yekufambisa data kubva kuRead Master uye kunyora zvirimo kugamuchira kana yemuno FPGA memory.

Nyoresa Mepu uye Kero Nzvimbo

Iyo DMA AFU inotsigira ndangariro mbiri views: Iyo DMA view uye muenzi view. Iye DMA view inotsigira 49-bit kero nzvimbo. Iyo yakaderera hafu yeDMA view mepu kune yemuno FPGA ndangariro. Iyo yepamusoro hafu yeDMA view mamepu ekugamuchira ndangariro. Mugamuchiri view inosanganisira ese marejista anosvikika kuburikidza neMMIO anowanikwa senge matafura eDFH, uye kutonga / chimiro chemazita akasiyana eIP cores anoshandiswa mukati meDMA AFU. Iyo MMIO inonyoresa muDMA BBB uye AFU inotsigira 32- uye 64-bit kuwana. Iyo DMA AFU haitsigire 512-bit MMIO inowanikwa. Kupinda kune Dispatcher marejista mukati meDMA BBB kunofanirwa kunge kuri makumi matatu nemaviri (Descriptor frontend zvishandiso 32-bit marejista).

DMA AFU Register Mepu

Mepu yeDMA AFU yerejista inopa kero dzakakwana dzenzvimbo dzese dziri mukati mechikamu. Marejista aya ari muhosi view nekuti ndiye mugamuchiri chete anogona kuzviwana.

DMA AFU Memory Mepu

Byte Kero Offsets	Zita	Span mumaBytes	Tsanangudzo
0x0	DMA AFU DFH	0x40	Chishandiso chine musoro weiyo DMA AFU. Iyo ID_L yakaiswa ku 0x9081f88b8f655caa uye ID_H yakaiswa ku 0x331db30c988541ea. Iyo DMA AFU DFH yakamisikidzwa kunongedza kumisa 0x100 kutsvaga inotevera DFH (DMA BBB DFH). Haufanire kushandura kero yekutanga yeDMA AFU DFH sezvo ichifanirwa kunge iri pakero 0x0 sekutsanangurwa kwazvinoitwa neCCIP.
0x100	DMA BBB	0x100	Inotsanangura DMA BBB kutonga uye chimiro chekunyoresa interface. Iwe unogona kutarisa kune iyo DMA BBB rejista mepu kuti uwane rumwe ruzivo. Mukati meDMA BBB pakubvisa 0 iyo DMA BBB inosanganisira yayo DFH. Iyi DFH yakaiswa kuti iwane inotevera DFH pakubvisa 0x100 (NULL DFH). Kana iwe ukawedzera mamwe maDMA BBB, sarudza iwo 0x100 ari kure uye ona kuti NULL DFH inotevera DMA yekupedzisira ne0x100.
0x200	NULL DFH	0x40	Inogumisa iyo DFH yakabatana-rondedzero. Iyo ID_L yakaiswa ku 0x90fe6aab12a0132f uye ID_H yakaiswa ku 0xda1182b1b3444e23. Iyo NULL DFH yakamisikidzwa kuti ive yekupedzisira DFH muhardware. Nechikonzero ichi iyo NULL DFH iri pakero 0x200. Kana iwe ukawedzera mamwe maDMA BBB kune sisitimu, iwe unofanirwa kuwedzera iyo NULL DFH base kero zvinoenderana kuitira kuti irambe iri pakero yepamusoro. Iyo DMA mutyairi uye test application haishandise iyi hardware.

Nyoresa Mepu uye Kero Nzvimbo

DMA BBB Memory Mepu
Aya anotevera mabheti kero ndeaya anobvisa kubva kuDMA BBB base kero muDMA AFU system (0x100).

Byte Kero Offsets	Zita	Span mumaBytes	Tsanangudzo
0x0	DMA BBB DFH	0x40	Musoro wemudziyo weiyo DMA AFU. Iyo ID_L yakaiswa ku 0xa9149a35bace01ea uye ID_H yakaiswa ku 0xef82def7f6ec40fc . Iyo DMA BBB DFH yakamisikidzwa kunongedza ku0x100 kune inotevera DFH yekubvisa. Ichi chinotevera chinobvisa chinogona kuva imwe DMA BBB, imwe DFH (isina kubatanidzwa mune iyi dhizaini), kana iyo NULL DFH.
0x40	Dispatcher	0x40	Dzora chiteshi che dispatcher. Mutyairi weDMA anoshandisa nzvimbo iyi kudzora DMA kana kubvunza mamiriro ayo.
0x80	Descriptor Frontend	0x40	Descriptor frontend chikamu chetsika chinoverenga tsananguro kubva mundangariro yekugamuchira uye inonyora tsananguro kana DMA yapera. Mutyairi anoraira kumberi uko mutsananguri wekutanga anogara mundangariro yevaenzi uyezve iyo yepamberi hardware inotaurirana nemutyairi zvakanyanya kunyangwe zvinotsanangurwa zvakachengetwa mundangariro yevaenzi.

DMA AFU Kero Nzvimbo

Muridzi anogona kuwana maregister akanyorwa muTable 4 papeji 12 uye Tafura 5 papeji 13. Iyo DMA BBB subsystem inokwanisa kuwana yakazara 49-bit kero nzvimbo. Iyo yepasi hafu yeiyi kero nzvimbo inosanganisira yemuno FPGA ndangariro. Iyo yekumusoro hafu yeiyi kero nzvimbo inosanganisira iyo 48-bit host kero memory. Nhamba inotevera inoratidza muiti uye DMA views yendangariro.

Iyo DMA AFU uye Host Views yeMemory

Device Feature Header Yakabatanidzwa-Rondedzero

Iyo DMA AFU dhizaini example ine matatu mudziyo wemhando misoro (DFH) inoumba runyorwa rwakabatana. Iyi rondedzero yakabatanidzwa inobvumira iyo sample application yekuziva iyo DMA AFU pamwe nemutyairi kuziva iyo DMA BBB. Rondedzero yeDFH inosanganisira NULL DFH kumagumo. Iko kusanganisirwa kweiyo null DFH kumagumo kweiyo yakabatanidzwa rondedzero inobvumidza iwe kuwedzera mamwe maDMA BBB kune dhizaini yako. Iwe unongoda kufambisa iyo NULL DFH kune kero mushure memamwe maBBB. Imwe neimwe DMA BBB inotarisira kuti inotevera DFH inowanikwa 0x100 bytes kubva pabhesi kero yeBBB. Iyi inotevera nhamba inoratidza yakabatana-rondedzero yeiyo DMA AFU dhizaini example.

Nyoresa Mepu uye Kero Nzvimbo

DMA AFU Device Feature Header (DFH) Chaining

Software Programming Model

Iyo DMA AFU inosanganisira mutyairi wesoftware waunogona kushandisa mune yako wega host application. The fpga_dma.cpp uye fpga_dma.h fileiri panzvimbo inotevera shandisa mutyairi wesoftware:$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw Mutyairi uyu anotsigira zvinotevera mabasa:

API	Tsanangudzo
fpgaCountDMChannels	Inotarisisa cheni yedhizaini yeDMA BBBs uye kuverenga ese aripo chiteshi.
fpgaDMAOpen	Inovhura mubato kuchiteshi cheDMA.
fpgaDMAClose	Inovhara mubato kuchiteshi cheDMA.
fpgaDMATransferInit	Inotanga chinhu chinomiririra kuendeswa kweDMA.
fpgaDMATransferReset	Inogadzirisa zvakare iyo DMA yekuchinjisa hunhu chinhu kune default kukosha.
fpgaDMATransferDestroy	Inoparadza iyo DMA yekufambisa hunhu chinhu.
fpgaDMATransferSetSrc	Inoseta kwabva kero yekutamisa. Kero iyi inofanirwa kuenderana ne64 byte.
fpgaDMATransferSetDst	Inoseta kero yekwainotumirwa. Kero iyi inofanirwa kuenderana ne64 byte.
fpgaDMATransferSetLen	Inoisa hurefu hwekutamisa mumabhaiti. Kune asiri-packet kutamiswa, unofanirwa kuseta kureba kwekutamisa kune akawanda e64 bytes. Pakutakura kwepaketi, izvi hazvisi izvo zvinodiwa.
fpgaDMATransferSetTransferType	Inoseta mhando yekufambisa. Mitemo yemutemo ndeiyi: • HOST_MM_TO_FPGA_MM = TX (Kugamuchira kuAFU) • FPGA_MM_TO_HOST_MM = RX (AFU to host)
fpgaDMATransferSetTransferCallback	Register callback yekuzivisa pane asynchronous kutamisa kupera. Kana iwe ukatsanangura callback, fpgaDMATransfer inodzoka nekukurumidza (asynchronous transfer). Kana iwe usingataure kufona, fpgaDMATransfer inodzoka mushure mekutamisa kwapera (synchronous/blocking transfer).
fpgaDMATransferSetLast	Inoratidza kuchinjisa kwekupedzisira kuitira kuti DMA itange kugadzirisa mafambiro ekutanga. Iko kukosha kweiyo 64 kuchinjirwa mupombi DMA isati yatanga kushanda pakuchinjisa.
fpgaDMATransfer	Inoita kutumira kweDMA.

Kuti uwane rumwe ruzivo nezve API, yekupinda, uye inobuda nharo, tarisa kune iyo musoro file inowanikwa $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw/fpga_dma.hIntel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.

Software Programming Model

Kuti uzive zvakawanda nezve software mutyairi kushandisa modhi, tarisa kune README file iri pa$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/README.md

Kumhanya DMA AFU Example

Usati watanga:

Iwe unofanirwa kujairana ne exampLes muIntel Kukwirisa Stack Kurumidza Kutanga Gwaro reIntel FPGA Programmable Kuwedzera Kadhi D5005.
Iwe unofanirwa kutsanangura shanduko yenzvimbo. Iyo nharaunda inoshanduka inoenderana neIntel Acceleration Stack vhezheni yauri kushandisa:
- Kune yazvino vhezheni, isa iyo nharaunda shanduko ku $OPAE_PLATFORM_ROOT
Iwe unofanirwa kuisa iyo Intel Threading Building Blocks (TBB) raibhurari sezvo mutyairi weDMA achivimba nayo.
Iwe unofanirwawo kuseta maviri 1 GB mapeji mahombe kuti umhanye sample application. $ sudo sh -c "echo 2 > /sys/kernel/mm/hugepages/hugepages-1048576kB/ nr_hugepages"

Ita matanho anotevera kurodha iyo DMA Accelerator Function (AF) bitstream, kuvaka application uye mutyairi, uye kumhanya dhizaini ex.ample:

Shandura kuDMA application uye dhairekitori remutyairi: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw
Vaka mutyairi uye application: make

Dhawunirodha iyo DMA AFU bitstream: sudo fpgasupdate ../bin/dma_afu_unsigned.gbs
Ita iyo host application yekunyora 100 MB mu1 MB zvikamu kubva kune host memory kuenda kuFPGA mudziyo memory uye uverenge zvakare: ./ fpga_dma_test -s 104857600 -p 1048576 -r mtom

Related Information
Intel Kukwidziridza Stack Kurumidza Kutanga Gwaro reIntel FPGA Programmable Kuwedzera Kadhi D5005 Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Kunyora iyo DMA AFU Example

Kugadzira iyo synthesis yekuvaka nharaunda kuunganidza AF, shandisa iyo afu_synth_setup murairo unotevera:

Shandura kuDMA AFU sample directory: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu
Gadzira iyo dhizaini yekuvaka dhairekitori: afu_synth_setup -source hw/rtl/filelist.txt build_synth

Kubva pane synthesis kuvaka dhairekitori rakagadzirwa neafu_synth_setup, isa mirairo inotevera kubva pahwindo rekupedzisira kuti ugadzire AF yepuratifomu yehardware inonangwa: cd build_synth run.sh The run.sh AF generation script inogadzira mufananidzo weAF une hwaro hwakafanana. filezita seAFU's platform kumisikidza file (.json) ine .gbs suffix panzvimbo iyi:$OPAE_PLATFORM_ROOT/hw/samples/build_synth/dma_afu_s10.gbs Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Kutevedzera iyo AFU Example

Intel inokurudzira kuti utaure kuIntel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start Guide kuti Intel FPGA PAC yako ijairane nekutevedzera zvakafanana ex.amples uye kuseta nharaunda yako. Usati waenderera nematanho anotevera, tarisa kuti OPAE_PLATFORM_ROOT nharaunda inosiyana yakaiswa kune OPAE SDK yekuisa dhairekitori. Pedzisa matanho anotevera kuseta iyo hardware simulator yeDMA AFU:

Shandura kuDMA AFU sample directory: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu

Gadzira nharaunda yeASE mune dhairekitori nyowani uye gadzirisa iyo yekufananidza iyo AFU: afu_sim_setup -source hw/rtl/filelist.txt build_ase_dir
Shandura kune ASE kuvaka dhairekitori: cd build_ase_dir
Vaka mutyairi uye application: make

Gadzira simulation: gadzira sim

Sampyakabuda kubva kune hardware simulator:

[SIM] ** ZVAKAITWA : USATI watanga kushandisa software ** [SIM] Seta env(ASE_WORKDIR) muterminal umo application ichashanda (copy-and-paste) => [SIM] $SHELL | Mhanyai:[SIM] ———+—————————————————— [SIM] bash/zsh | kunze ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] Kune chero $SHELL, bvunza Linux administrator [SIM] [SIM] Yagadzirira kuedzesera… [SIM] Dzvanya CTRL-C kuvhara simulator…

Pedzisa nhanho dzinotevera kuunganidza uye kuita iyo DMA AFU software munzvimbo yekufananidza:

Vhura hwindo idzva rekupedzisira.
Chinja dhairekitori kuti: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw

Kutevedzera iyo AFU Example

Kopa tambo yekuseta nharaunda (sarudza tambo inokodzera goko rako) kubva pamatanho ari pamusoro muiyo hardware simulation kune terminal hwindo. Ona mitsetse inotevera musample yakabuda kubva kune hardware simulator. [SIM] bash/zsh | kunze ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/work
Unganidza software: $ita USE_ASE=1

Ita iyo host application kunyora 4 KB mu1 KB zvikamu kubva kune iyo host memory kudzokera kuFPGA mudziyo memory mu loopback modhi: ./ fpga_dma_test -s 4096 -p 1024 -r mtom

Related Information
Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Kurumidza Kutanga Mushandisi Gwaro

Optimization yeKuvandudza DMA Performance

Kuitwa kweNUMA (isina-uniform memory yekuwana) optimization mufpga_dma_test.cpp inobvumira iyo processor kuti iwane yayo yega ndangariro nekukurumidza kupfuura kuwana isiri-yemunharaunda ndangariro (yekuyeuka yemunharaunda kune imwe processor). Yakajairika NUMA kumisikidzwa inoratidzwa mudhayagiramu pazasi. Kupinda kwenzvimbo kunomiririra kupinda kubva pakati kuenda kundangariro yenzvimbo kuenda kune imwechete core. Kusvika kure kunoratidza nzira inotorwa kana musimboti paNode 0 ichipinda ndangariro inogara mundangariro munharaunda kuNode 1.

Yakajairika NUMA Configuration

Shandisa kodhi inotevera kushandisa NUMA optimization mune yako bvunzo application:

// Misa hukama hwakakodzera kana ukakumbirwa kana (cpu_affinity || memory_affinity) {unsigned dom = 0, bhazi = 0, dev = 0, func = 0; fpga_properties props;int retval; #if(FPGA_DMA_DEBUG)char str[4096]; #endifres = fpgaGetProperties(afc_token, &props); ON_ERR_GOTO(res, out_destroy_tok, “fpgaGetProperties”); res = fpgaPropertiesGetBus(props, (uint8_t *) & bhazi); ON_ERR_GOTO(res, out_destroy_tok, “fpgaPropertiesGetBus”); res = fpgaPropertiesGetDevice(props, (uint8_t *) & dev); ON_ERR_GOTO(res, out_destroy_tok, “fpgaPropertiesGetDevice”) res = fpgaPropertiesGetFunction(props, (uint8_t *) & func); ON_ERtok_Gonga_Function); // Tsvaga mudziyo kubva kutopology hwloc_topology_t topology; hwloc_topology_init(&topology); hwloc_topology_set_flags(topology, HWLOC_TOPOLOGY_FLAG_IO_DEVICES);Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

Optimization yeKuvandudza DMA Performance

hwloc_topology_load(topology); hwloc_obj_t obj = hwloc_get_pcidev_by_busid(topology, dom, bhazi, dev, func); hwloc_obj_t obj2 = hwloc_get_non_io_ancestor_obj(topology, obj); #kana (FPGA_DMA_DEBUG) hwloc_obj_type_snprintf(str, 4096, obj2, 1); printf(“%s\n”, str);hwloc_obj_attr_snprintf(str, 4096, obj2, ” :: “, 1);printf(“%s\n”, str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2->cpuset); printf(“CPUSET iri %s\n”, str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2-> nodeset); printf(“NODESET is %s\n”, str);#endif if (memory_affinity) { #if HWLOC_API_VERSION > 0x00020000 retval = hwloc_set_membind(topology, obj2->nodeset,HWLOC_MEMB_MEMB_MEMB_GRAMEB_GRAMEH_MEMB,HWLOC_MEMB,HWLOC_MEMB,HWLOC_MEMB, #else retval =hwloc_set_membind_nodeset(topology, obj2->nodeset, HWLOC_MEMBIND_THREAD,HWLOC_MEMBIND_MIGRATE); #endifON_ERR_GOTO(retval, out_destroy_tok, “hwloc_set_membind”); } kana (cpu_affinity) {retval = hwloc_set_cpubind(topology, obj2->cpuset, HWLOC_CPUBIND_STRICT); ON_ERR_GOTO(retval, out_destroy_tok, “hwloc_set_cpubind”); }}

DMA Accelerator Functional Unit User Guide Archives

Intel Acceleration Stack Version	Bhuku reMushandisi (PDF)
2.0	DMA Accelerator Functional Unit (AFU) Mushandisi Wekushandisa

Document Revision History yeDMA Accelerator Functional Unit User Guide

Document Version

Intel Kuwedzera Stack Version

Kuchinja

2020.08.03

2.0.1 (inotsigirwa neIntel

Quartus® Prime Pro Edition Edition 19.2)

Akagadzirisa mufananidzo weAF file zita muchikamu Kunyora iyo DMA AFU Example.

2020.04.17

2.0.1 (inotsigirwa neIntel

Quartus Prime Pro Edition Edition 19.2)

Akagadzirisa chirevo mukati Vateereri Vanotarisirwa chikamu.

2020.02.20

2.0.1 (inotsigirwa neIntel

Quartus Prime Pro Edition Edition 19.2)

Fixed typo.

2019.11.04

2.0.1 (inotsigirwa neIntel

Quartus Prime Pro Edition Edition 19.2)

• Kutsiva fpgaconf nefpgasupdate pakumisikidza FPGA neAFU yakambovakwa muchikamu. Kumhanyisa iyo DMA AFU Example.

• Akawedzera subtitle Intel FPGA Programmable Acceleration Card D5005 kune zita regwaro.

• Yakawedzerwa nharaunda inosiyana $OPAE_PLATFORM_ROOT.

• Chikamu chakashandurwa Software Programming Model zvezvinyorwa zvidiki.

• Chikamu chitsva chakawedzerwa Kunyora iyo DMA AFU Example.

• Chikamu chakashandurwa Optimization yeKuvandudza DMA Performance zvezvinyorwa zvidiki.

2019.08.05

2.0 (inotsigirwa neIntel

Quartus Prime Pro Edition 18.1.2)

Kusunungurwa kwekutanga.

Mamwe mazita nemhando anogona kunzi zvinhu zvevamwe.

Zvinyorwa / Zvishandiso

Intel FPGA Programmable Acceleration Card D5005 [pdf] Bhuku reMushandisi
FPGA Programmable Acceleration Card, D5005, FPGA Programmable Acceleration Card D5005, DMA Accelerator Functional Unit

References

User Manual

Intel FPGA Programmable Acceleration Card D5005

Nezve Gwaro iri

DMA AFU Tsanangudzo

Nyoresa Mepu uye Kero Nzvimbo

DMA AFU Register Mepu

Nyoresa Mepu uye Kero Nzvimbo

Software Programming Model

Kumhanya DMA AFU Example

Kunyora iyo DMA AFU Example

Kutevedzera iyo AFU Example

Optimization yeKuvandudza DMA Performance

DMA Accelerator Functional Unit User Guide Archives

Document Revision History yeDMA Accelerator Functional Unit User Guide

Zvinyorwa / Zvishandiso

References

Siya mhinduro

Kanzura mhinduro