onsemi FQP4N90C, FQPF4N90C N-Channel QFET MOSFET

Product Description

This document details the onsemi FQP4N90C and FQPF4N90C, which are N-Channel enhancement mode power MOSFETs. They are manufactured using onsemi's proprietary planar stripe and DMOS technology, designed to reduce on-state resistance, provide superior switching performance, and offer high avalanche energy strength. These devices are suitable for applications such as switched-mode power supplies, active power factor correction (PFC), and electronic lamp ballasts.

Key Features

• 4.0 A continuous drain current, 900 V drain-source voltage.
• Low on-state resistance (RDS(on)) of 4.2 Ω (Max.) at VGS = 10 V, ID = 2.0 A.
• Low Gate Charge (Qg): Typically 17 nC.
• Low Crss (Reverse Transfer Capacitance): Typically 5.6 pF.
• 100% Avalanche Tested.

Key Specifications Summary

*Drain current limited by maximum junction temperature.

Marking Diagram

The marking diagram shows the typical markings on the device package. It includes a specific device code (e.g., FQP4N90C or FQPF4N90C), an assembly location code ('A'), a date code (Year & Week, 'YWW'), and an assembly lot code ('ZZ').

[Diagram showing package marking layout]

N-Channel MOSFET Symbol

The schematic symbol for an N-Channel MOSFET is shown, with terminals labeled Gate (G), Drain (D), and Source (S).

[Diagram showing N-Channel MOSFET symbol]

Ordering Information

Note 1: FQP4N90C is marked as DISCONTINUED. Please contact onsemi for availability information. The most current information may be available on www.onsemi.com.

Absolute Maximum Ratings

(Tc = 25 °C, unless otherwise noted)

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

Notes:

2. Repetitive rating: pulse-width limited by maximum junction temperature.

3. L = 67 mH, IAS = 4 A, VDD = 50 V, RG = 25 Ω, starting Tj = 25 °C.

4. ISD ≤ 4 A, di/dt ≤ 200 A/μs, VDD ≤ BVDSS, starting TJ = 25 °C.

Thermal Characteristics

Electrical Characteristics

(TC = 25 °C unless otherwise noted)

OFF CHARACTERISTICS

ON CHARACTERISTICS

DYNAMIC CHARACTERISTICS

SWITCHING CHARACTERISTICS

Note 5: Essentially independent of operating temperature.

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

Typical Characteristics

Figure 1. On-Region Characteristics

This graph shows the relationship between Drain Current (ID) and Drain-Source Voltage (VDS) for various Gate-Source Voltages (VGS) at a case temperature of 25°C. It illustrates the device's behavior in the saturation and linear regions.

[Graph showing ID vs. VDS for different VGS values]

Figure 2. Transfer Characteristics

This graph plots Drain Current (ID) against Gate-Source Voltage (VGS) at different temperatures (-55°C, 25°C, 150°C) with VDS = 50 V. It shows how the drain current changes with gate voltage and highlights the effect of temperature.

[Graph showing ID vs. VGS at different temperatures]

Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage

This plot illustrates the variation of Static Drain-Source On-Resistance (RDS(on)) as a function of Drain Current (ID) for different Gate-Source Voltages (VGS = 10 V and 20 V) at a junction temperature of 25°C.

[Graph showing RDS(on) vs. ID for different VGS values]

Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature

This graph displays the Body Diode Forward Voltage (VSD) versus Source Current (IS) at different temperatures (-55°C, 25°C, 150°C). It shows the forward voltage drop characteristics of the intrinsic body diode.

[Graph showing VSD vs. IS at different temperatures]

Figure 5. Capacitance Characteristics

This plot shows the input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss) as a function of Drain-Source Voltage (VDS) at a frequency of 1 MHz and VGS = 0 V.

[Graph showing Ciss, Coss, Crss vs. VDS]

Figure 6. Gate Charge Characteristics

This graph illustrates the Total Gate Charge (Qg), Gate-Source Charge (Qgs), and Gate-Drain Charge (Qgd) as a function of Gate-Source Voltage (VGS) for a Drain-Source Voltage (VDS) of 720 V and Drain Current (ID) of 4 A.

[Graph showing Qg, Qgs, Qgd vs. VGS]

Figure 7. Breakdown Voltage Variation vs. Temperature

This graph shows the normalized Drain-Source Breakdown Voltage (BVDSS) as a function of Junction Temperature (TJ) for VGS = 0 V and ID = 250 μA.

[Graph showing normalized BVDSS vs. TJ]

Figure 8. On-Resistance Variation vs. Temperature

This graph shows the normalized Drain-Source On-Resistance (RDS(on)) as a function of Junction Temperature (TJ) for VGS = 10 V and ID = 2.0 A.

[Graph showing normalized RDS(on) vs. TJ]

Figure 9 & 10. Maximum Safe Operating Area (SOA)

These graphs illustrate the Maximum Safe Operating Area (SOA) for FQP4N90C and FQPF4N90C, showing the relationship between Drain Current (ID) and Drain-Source Voltage (VDS) under various conditions (e.g., DC, pulsed operation) at specific case and junction temperatures.

[Graphs showing ID vs. VDS for SOA]

Figure 11. Maximum Drain Current vs. Case Temperature

This graph shows the maximum allowable Drain Current (ID) as a function of Case Temperature (TC).

[Graph showing ID vs. TC]

Figure 12 & 13. Transient Thermal Response Curves

These graphs show the Transient Thermal Response (ZθJC(t)) as a function of Square Wave Pulse Duration (t1) for FQP4N90C and FQPF4N90C, respectively. They are used to estimate junction temperature under pulsed operating conditions with varying duty factors.

[Graphs showing ZθJC(t) vs. t1]

Test Circuits and Waveforms

Figure 14. Gate Charge Test Circuit & Waveform

This section describes the test circuit used to measure gate charge characteristics. It includes a DUT (Device Under Test), a gate driver, capacitors, and resistors. The waveform shows the gate voltage (VGS) and drain current (ID) during the test, illustrating parameters like Qg, Qgs, and Qgd.

[Diagram of Gate Charge Test Circuit and Waveform]

Figure 15. Resistive Switching Test Circuit & Waveforms

This section details the test circuit for measuring switching characteristics under resistive load conditions. It includes the DUT, a gate resistor (RG), a load resistor (RL), and voltage sources. The waveforms display VGS and VDS over time, indicating switching times such as turn-on delay (td(on)), rise time (tr), turn-off delay (td(off)), and fall time (tf).

[Diagram of Resistive Switching Test Circuit and Waveforms]

Figure 16. Unclamped Inductive Switching Test Circuit & Waveforms

This section describes the test circuit for unclamped inductive switching (UIS), used to evaluate avalanche energy (EAS). It includes the DUT, an inductor (L), a voltage source (VDD), and a gate driver. The waveforms show the drain current (ID) and drain-source voltage (VDS) during the avalanche event, illustrating parameters like EAS and tp (pulse width).

[Diagram of Unclamped Inductive Switching Test Circuit and Waveforms]

Figure 17. Peak Diode Recovery dv/dt Test Circuit & Waveforms

This section outlines the test circuit for measuring the peak diode recovery dv/dt. It involves the DUT, a driver, a resistor (RG), an inductor (L), and a voltage source (VDD). The waveforms illustrate the body diode's forward current (IFM), reverse current (IRM), and the voltage across the drain-source (VDS) during the recovery process, showing parameters like VSD (forward voltage drop) and dv/dt.

[Diagram of Peak Diode Recovery dv/dt Test Circuit and Waveforms]

Package Outline Dimensions

TO-220 Fullpack, 3-Lead / TO-220F-3SG (CASE 221AT)

This section provides the mechanical dimensions for the TO-220 Fullpack package. The diagram shows the outline with key dimensions labeled (A, A1, A2, b, b2, C, D, D1, E, e, F, H1, L, L1, ØP, P1, Q). A table lists the minimum, nominal, and maximum values for each dimension in millimeters.

Notes:

• A. Dimension and Tolerance as ASME Y14.5-2009.
• B. Dimensions are exclusive of burrs, mold flash and tie bar protrusions.
• C. OPTION 1 - WITH SUPPORT PIN HOLE
• D. OPTION 2 - NO SUPPORT PIN HOLE

Document Number: 98AON67439E

[Diagram showing TO-220 Fullpack package dimensions with labels and a table of dimensions]

TO-220-3LD (CASE 340AT)

This section provides the mechanical dimensions for the TO-220-3LD package. The diagram shows the outline with key dimensions labeled (A, A1, A2, b, b2, b4, C, D, D1, D2, D3, E, E1, e, H1, L, L1, P, Q, Z, Z1, θ). A table lists the minimum, nominal, and maximum values for each dimension in millimeters.

Generic Marking Diagram: Shows placeholders for specific device code, assembly location, year, work week, and assembly lot code. Notes indicate that marking may vary and Pb-Free indicators may or may not be present.

Notes:

• A) REFERENCE JEDEC, TO-220, VARIATION AB
• B) ALL DIMENSIONS ARE IN MILLIMETERS.
• C) DIMENSIONS COMMON TO ALL PACKAGE SUPPLIERS EXCEPT WHERE NOTED (].
• D) LOCATION OF MOLDED FEATURE MAY VARY (LOWER LEFT CORNER, LOWER CENTER AND CENTER OF THE PACKAGE).
• E) DOES NOT COMPLY JEDEC STANDARD VALUE.
• F) "A1" DIMENSIONS AS BELOW: SINGLE GAUGE = 0.51 -0.61, DUAL GAUGE 1.10-1.45.
• G) PRESENCE IS SUPPLIER DEPENDENT.
• H) SUPPLIER DEPENDENT MOLD LOCKING HOLES IN HEATSINK.

Document Number: 98AON13818G

[Diagram showing TO-220-3LD package dimensions with labels and a table of dimensions]

Revision History

This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made on the noted approval dates.