UF4SC120012K4SH

Description

The UF4SC120012K4SH is a 1200 V, 12 milliohm G4 SiC FET. It is based on a unique 'cascode' circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device's standard gate-drive characteristics allow use of off-the-shelf gate drivers, hence requiring minimal redesign when replacing Si IGBTs, Si superjunction devices, or SiC MOSFETs. Available in the TO247-4LH package, this device exhibits ultra-low gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads and any application requiring standard gate drive.

Features

• On-resistance RDS(on): 12 milliohms (Typical)
• Operating Temperature: 175 degrees Celsius (Max)
• Excellent Reverse Recovery: Qrr = 482 nanocoulombs
• Low Body Diode VFSD: 1.18 Volts
• Low Gate Charge: QG = 75 nanocoulombs
• Threshold Voltage VG(th): 4.5 Volts (Typ) Allowing 0 to 15 V Drive
• Low Intrinsic Capacitance
• Kelvin Source Pin for Optimized Switching Performance
• TO247-4LH Package with 8 mm Drain-Source Creepage Distance
• ESD Protected: HBM Class 2 and CDM Class C3
• This Device is Pb-Free, Halogen Free and is RoHS Compliant

Typical Applications

• EV Charging
• PV Inverters
• Switch Mode Power Supplies
• Power Factor Correction Modules
• Motor Drives
• Induction Heating

Maximum Ratings

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Limited by bondwires.

2. Pulse width tp limited by TJ, max.

3. Starting TJ = 25 degrees Celsius.

Thermal Characteristics

Electrical Characteristics

Typical Performance - Static

Typical Performance - Reverse Diode

Typical Performance - Dynamic

Typical Performance - Dynamic (Continued)

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Measured with the switching test circuit in Figure 26.

5. In this datasheet, all the switching energies (turn-on energy, turn-off energy and total energy) presented in the tables and Figures include the device RC snubber energy losses.

Typical Performance Diagrams

Figure 1: Typical Output Characteristics at Tj = -55 °C, tp < 250 µs

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis. Multiple curves are shown, each representing a different Gate-Source Voltage (VGS), ranging from 6 V to 15 V. As VGS increases, the drain current increases significantly for a given VDS.

Figure 2: Typical Output Characteristics at Tj = 25 °C, tp < 250 µs

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis. Multiple curves are shown, each representing a different Gate-Source Voltage (VGS), ranging from 6 V to 15 V. As VGS increases, the drain current increases significantly for a given VDS.

Figure 3: Typical Output Characteristics at Tj = 175 °C, tp < 250 µs

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis. Multiple curves are shown, each representing a different Gate-Source Voltage (VGS), ranging from 5.5 V to 15 V. As VGS increases, the drain current increases significantly for a given VDS.

Figure 4: Normalized On-Resistance vs. Temperature at VGS = 12 V and ID = 70 A

This graph plots Normalized On-Resistance (RDS(on) P.U.) on the y-axis against Junction Temperature (TJ) on the x-axis, from -75 to 175 degrees Celsius. The normalized on-resistance increases with increasing temperature.

Figure 5: Typical Drain-Source On-Resistances at VGS = 12 V

This graph plots RDS(on) (milliohms) on the y-axis against Drain Current (ID) on the x-axis. Three curves are shown for different junction temperatures: -55 °C, 25 °C, and 175 °C. The on-resistance increases with drain current and is higher at elevated temperatures.

Figure 6: Typical Transfer Characteristics at VDS = 5 V

This graph plots Drain Current (ID) on the y-axis against Gate-Source Voltage (VGS) on the x-axis. Multiple curves are shown for different Drain-Source Voltages (VDS), ranging from -5 V to 8 V. The curves show the device's switching behavior as VGS changes.

Figure 7: Threshold Voltage vs. Junction Temperature at VDS = 5 V and ID = 10 mA

This graph plots Threshold Voltage (Vth) on the y-axis against Junction Temperature (TJ) on the x-axis, from -100 to 200 degrees Celsius. The threshold voltage decreases slightly as the junction temperature increases.

Figure 8: Typical Gate Charge at VDS = 800 V and ID = 70 A

This graph plots Gate-Source Voltage (VGS) on the y-axis against Gate Charge (QG) on the x-axis, from 0 to 100 nanocoulombs. The plot shows the voltage required to achieve specific gate charge levels.

Figure 9: 3rd Quadrant Characteristics at TJ = -55 °C

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis in the third quadrant. Curves are shown for VGS values of -5 V, 0 V, 5 V, and 8 V, illustrating the device's behavior under reverse bias conditions.

Figure 10: 3rd Quadrant Characteristics at TJ = 25 °C

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis in the third quadrant. Curves are shown for VGS values of -5 V, 0 V, 5 V, and 8 V, illustrating the device's behavior under reverse bias conditions.

Figure 11: 3rd Quadrant Characteristics at TJ = 175 °C

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis in the third quadrant. Curves are shown for VGS values of -5 V, 0 V, 5 V, and 8 V, illustrating the device's behavior under reverse bias conditions.

Figure 12: Typical Stored Energy in Coss at VGS = 0 V

This graph plots Stored Energy (Eoss) in microJoules on the y-axis against Drain-Source Voltage (VDS) on the x-axis, from 0 to 1200 Volts. It shows how energy stored in the output capacitance varies with VDS.

Figure 13: Typical Capacitances at f = 100 kHz and VGS = 0 V

This graph plots Capacitance (C) in picofarads on the y-axis against Drain-Source Voltage (VDS) on the x-axis, from 0 to 1200 Volts. It shows the behavior of input capacitance (Ciss), output capacitance (Coss), and reverse transfer capacitance (Crss) as a function of VDS.

Figure 14: DC Drain Current Derating

This graph plots DC Drain Current (ID) in Amperes on the y-axis against Case Temperature (TC) on the x-axis, from -75 to 175 degrees Celsius. It illustrates how the maximum continuous drain current decreases as the case temperature rises.

Figure 15: Total Power Dissipation

This graph plots Total Power Dissipation (Ptot) in Watts on the y-axis against Case Temperature (TC) on the x-axis, from -75 to 175 degrees Celsius. It shows the maximum power the device can dissipate at different case temperatures.

Figure 16: Maximum Transient Thermal Impedance

This graph plots Thermal Impedance (ZthJC) in degrees Celsius/Watt on the y-axis against Pulse Time (tp) in seconds on the x-axis, on a logarithmic scale. Curves are shown for various duty cycles (D) from 0.01 to 0.5, and a single pulse condition. Foster model parameters are also listed.

Figure 17: Safe Operation Area at TC = 25 °C, D = 0, Parameter tp

This graph plots Drain Current (ID) on the y-axis against Drain-Source Voltage (VDS) on the x-axis. It defines the safe operating area for different pulse times (tp), indicating the limits for reliable operation.

Figure 18: Reverse Recovery Charge Qrr vs. Junction Temperature at VDS = 800 V

This graph plots Reverse Recovery Charge (Qrr) in nanocoulombs on the y-axis against Junction Temperature (TJ) on the x-axis, from 0 to 175 degrees Celsius. It shows how Qrr changes with temperature under specific test conditions (IS = 70 A, di/dt = 1900 A/microsec, VGS = 0 V, RG = 50 Ohms).

Figure 19: Clamped Inductive Switching Energy vs. Drain Current at VDS = 800 V and TJ = 25 °C

This graph plots Switching Energy (Eon, Eoff, Etot) in microJoules on the y-axis against Drain Current (ID) on the x-axis. It shows how switching energies vary with drain current under specified conditions.

Figure 20: RC Snubber Energy Loss vs. Drain Current at VDS = 800 V and TJ = 25 °C

This graph plots RC Snubber Energy Loss (Rs_Eon, Rs_Eoff, Rs_Etot) in microJoules on the y-axis against Drain Current (ID) on the x-axis. It shows the energy losses associated with the snubber circuit as a function of drain current.

Figure 21: Clamped Inductive Switching Energies vs. RG, EXT at VDS = 800 V, ID = 70 A, and TJ = 25 °C

This graph plots Switching Energy (Eon, Eoff) in microJoules on the y-axis against External Gate Resistance (RG_EXT) in Ohms on the x-axis. It illustrates the impact of external gate resistance on switching performance.

Figure 22: RC Snubber Energy Losses vs. RG, EXT at VDS = 800 V, ID = 70 A, and TJ = 25 °C

This graph plots RC Snubber Energy Losses (Rs_Eon, Rs_Eoff) in microJoules on the y-axis against External Gate Resistance (RG_EXT) in Ohms on the x-axis. It shows how snubber energy losses are affected by external gate resistance.

Figure 23: Clamped Inductive Switching Energies vs. Snubber Capacitance CS at VDS = 800 V, ID = 70 A, and TJ = 25 °C

This graph plots Switching Energy (Eon, Eoff, Etot) in microJoules on the y-axis against Snubber Capacitance (CS) in picofarads on the x-axis. It demonstrates the effect of snubber capacitance on switching energy.

Figure 24: RC Snubber Energy Losses vs. Snubber Capacitance CS at VDS = 800 V, ID = 70 A, and TJ = 25 °C

This graph plots RC Snubber Energy Losses (Rs_Eon, Rs_Eoff, Rs_Etot) in microJoules on the y-axis against Snubber Capacitance (CS) in picofarads on the x-axis. It shows the impact of snubber capacitance on snubber energy losses.

Figure 25: Clamped Inductive Switching Energy vs. Junction Temperature at VDS = 800 V and ID = 70 A

This graph plots Switching Energy (Eon, Eoff, Etot) in microJoules on the y-axis against Junction Temperature (TJ) on the x-axis, from 0 to 175 degrees Celsius. It illustrates how switching energies vary with junction temperature.

Figure 26: Schematic of the Half-bridge Mode Switching Test Circuit

This diagram shows a schematic of a half-bridge mode switching test circuit. It includes the Device Under Test (DUT), external gate resistance (RG_EXT), snubber capacitance (CS), and a bus RC snubber (RBS = 5 Ohms, CBS = 100 nF) used to reduce power loop high frequency oscillations.

Applications Information

SiC FETs are enhancement-mode power switches formed by a high-voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability, eliminating the need for an external anti-parallel diode.

Like other high-performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, visit www.onsemi.com.

A snubber circuit with a small RG, or gate resistor, provides better EMI suppression with higher efficiency compared to using a high RG value. There is no extra gate delay time when using the snubber circuitry, and a small RG will better control both the turn-off V(DS) peak spike and ringing duration, while a high RG will damp the peak spike but result in a longer delay time. In addition, the total switching loss when using a snubber circuit is less than using a high RG, while greatly reducing E(OFF) from mid-to-full load range with only a small increase in E(ON). Efficiency will therefore improve with higher load current. For more information on how a snubber circuit will improve overall system performance, visit the onsemi website at www.onsemi.com.

Ordering Information

Revision History

This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made on the noted approval dates.

Mechanical Case Outline

Package Dimensions

TO247-4LH 15.94x23.45x5.02, 2.54P, CASE 340CV, ISSUE B

Date: 16 APR 2025

Notes:

• 1. Dimensioning and tolerancing as per ASME Y14.5 – 2018
• 2. Controlling Dimensions = Millimeters
• 3. Dimensions D and E does not include MOLD FLASH
• 4. Thermal pad contour optional within dimensions D1 and E1
• 5. Lead finish uncontrolled in L1
• 6. ØP to have a max draft angle of 1.5° to the top with MAX. hole diameter of 3.91mm

Document Number: 98AON80645G

Description: TO247-4LH 15.94x23.45x5.02, 2.54P

Page: 1 OF 2

Recommended PCB Through Hole

TO247-4LH 15.94x23.45x5.02, 2.54P, CASE 340CV, ISSUE B

Date: 16 APR 2025

This section provides recommendations for PCB land pattern and through hole dimensions. These are intended as an initial guide, and end-user PCB design rules and tolerances should always prevail.

Hole Pattern:

• Three holes are shown, with spacing of 2.54 mm between adjacent holes along the length and 5.08 mm between the outer holes.
• Hole diameters are specified as Ø1.70 mm and Ø2.24 mm.
• The spacing between the centers of the holes is 2.54 mm and 5.08 mm.

Document Number: 98AON80645G

Description: TO247-4LH 15.94x23.45x5.02, 2.54P

Page: 2 OF 2

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