onsemi NDT3055L Transistor - N-Channel, Logic Level, Enhancement Mode Field Effect
Part Number: NDT3055L
Package: SOT-223, CASE 318H-01
General Description
This Logic Level N-Channel enhancement mode power field effect transistor is produced using onsemi's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance, and withstand high energy pulse in the avalanche and commutation modes. This device is particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed.
Features
- 4 A, 60 V
- RDS(ON) = 0.100 Ω @ VGS = 10 V
- RDS(ON) = 0.120 Ω @ VGS = 4.5 V
- Low Drive Requirements Allowing Operation Directly from Logic Drivers. VGS(TH) < 2V.
- High Density Cell Design for Extremely Low RDS(ON)
- High Power and Current Handling Capability in a Widely Used Surface Mount Package.
- This is a Pb-Free Device
Absolute Maximum Ratings
(TA = 25°C, unless otherwise noted)
| Symbol | Parameter | Value | Unit |
|---|---|---|---|
| VDSS | Drain-Source Voltage | 60 | V |
| VGSS | Gate-Source Voltage - Continuous | ±20 | V |
| ID | Maximum Drain Current Continuous (Note 1a) | 4 | A |
| Pulsed | 25 | A | |
| PD | Maximum Power Dissipation (Note 1a) | 3 | W |
| (Note 1b) | 1.3 | W | |
| (Note 1c) | 1.1 | W | |
| TJ, TSTG | Operating and Storage Temperature Range | -65 to 150 | °C |
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
Thermal Characteristics
(TA = 25°C, unless otherwise noted)
| Symbol | Parameter | Max | Unit |
|---|---|---|---|
| ROJA | Thermal Resistance, Junction-to-Ambient (Note 1a) | 42 | °C/W |
| ReJC | Thermal Resistance, Junction-to-Case (Note 1) | 12 | °C/W |
Electrical Characteristics
(TA = 25°C unless otherwise noted)
| Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| OFF CHARACTERISTICS | ||||||
| BVDSS | Drain-Source Breakdown Voltage | VGS = 0 V, ID = 250 μA | 60 | V | ||
| ABVDSS/ATJ | Breakdown Voltage Temp. Coefficient | ID = 250 µA, Referenced to 25°C | 55 | mV/°C | ||
| IDSS | Zero Gate Voltage Drain Current | VDS = 60 V, VGS = 0 V | 1 | μA | ||
| VDS = 60 V, VGS = 0 V, TJ = 125°C | 50 | μA | ||||
| IGSSF | Gate - Body Leakage, Forward | VGS = 20 V, VDS = 0 V | 100 | nA | ||
| IGSSR | Gate - Body Leakage, Reverse | VGS = -20 V, VDS = 0 V | -100 | nA | ||
| ON CHARACTERISTICS (Note 2) | ||||||
| VGS(th) | Gate Threshold Voltage | VDS = VGS, ID = 250 μA | 1 | 1.6 | 2 | V |
| AVGS(th)/ATJ | Gate Threshold Voltage Temp. Coefficient | ID = 250 µA, Referenced to 25°C | -4 | mV/°C | ||
| RDS(ON) | Static Drain-Source On-Resistance | VGS = 10 V, ID = 4.0 A | 0.07 | 0.1 | Ω | |
| VGS = 10 V, ID = 4.0 A, TJ = 125°C | 0.125 | 0.18 | Ω | |||
| VGS = 4.5 V, ID = 3.7 A | 0.103 | 0.12 | Ω | |||
| ID(ON) | On-State Drain Current | VGS = 5 V, VDS = 10 V | 10 | A | ||
| gFS | Forward Transconductance | VDS = 5 V, ID = 4 A | 7 | S | ||
| DYNAMIC CHARACTERISTICS | ||||||
| Ciss | Input Capacitance | VDS = 25 V, VGS = 0 V, f = 1.0 MHz | 345 | pF | ||
| Coss | Output Capacitance | 110 | pF | |||
| Crss | Reverse Transfer Capacitance | 30 | pF | |||
| SWITCHING CHARACTERISTICS (Note 2) | ||||||
| tD(on) | Turn - On Delay Time | VDD = 25 V, ID = 1 A, VGS = 10 V, RGEN = 6 Ω | 5 | 20 | ns | |
| tr | Turn - On Rise Time | 7.5 | 20 | ns | ||
| tD(off) | Turn - Off Delay Time | 20 | 50 | ns | ||
| tf | Turn - Off Fall Time | 7 | 20 | ns | ||
| Qg | Total Gate Charge | VDS = 40 V, ID = 4 A, VGS = 10 V | 13 | 20 | nC | |
| Qgs | Gate-Source Charge | 1.7 | nC | |||
| Qgd | Gate-Drain Charge | 3.2 | nC | |||
| DRAIN-SOURCE DIODE CHARACTERISTICS | ||||||
| Is | Maximum Continuous Drain-Source Diode Forward Current | 2.5 | A | |||
| VSD | Drain-Source Diode Forward Voltage | VGS = 0 V, Is = 2.5 A (Note 2) | 0.8 | 1.2 | V | |
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. ROJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. Rejc is guaranteed by design while ROCA is determined by the user's board design.
Figure 1: On-Region Characteristics
Description: This graph shows the relationship between Drain-Source Voltage (VDS) and Drain Current (ID) for various Gate-Source Voltages (VGS) at a constant temperature.
Figure 2: On-Resistance Variation with Drain Current and Gate Voltage
Description: This graph illustrates how the normalized on-resistance (RDS(ON)) changes with Drain Current (ID) for different Gate-Source Voltages (VGS).
Figure 3: On-Resistance Variation with Temperature
Description: This graph displays the normalized on-resistance (RDS(ON)) as a function of Junction Temperature (TJ) for a specific Drain Current (ID) and Gate-Source Voltage (VGS).
Figure 4: On-Resistance Variation with Gate-to-Source Voltage
Description: This graph shows the on-resistance (RDS(ON)) variation with Gate-to-Source Voltage (VGS) at different ambient temperatures (TA) for a constant Drain Current (ID).
Figure 5: Transfer Characteristics
Description: This graph plots Drain Current (ID) against Gate-to-Source Voltage (VGS) at different Junction Temperatures (TJ) and a constant Drain-Source Voltage (VDS).
Figure 6: Body Diode Forward Voltage Variation with Current and Temperature
Description: This graph illustrates the Body Diode Forward Voltage (VSD) variation with Drain-Source Diode Forward Current (IS) and temperature.
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
Typical Electrical Characteristics (continued)
Figure 7: Gate Charge Characteristics
Description: This graph shows the relationship between Gate Charge (Qg) and Gate-Source Voltage (VGS) for a specific Drain Current (ID) and Drain-Source Voltage (VDS).
Figure 8: Capacitance Characteristics
Description: This graph displays various capacitances (Ciss, Coss, Crss) as a function of Drain-Source Voltage (VDS) at a specific frequency and Gate-Source Voltage (VGS).
Figure 9: Maximum Safe Operating Area
Description: This graph shows the maximum allowable Drain Current (ID) versus Drain-Source Voltage (VDS) for different pulse durations and conditions, indicating the safe operating region.
Figure 10: Single Pulse Maximum Power Dissipation
Description: This graph illustrates the maximum power dissipation (W) for a single pulse event, considering the ambient temperature (TA) and thermal resistance (ROJA).
Figure 11: Transient Thermal Response Curve
Description: This graph shows the normalized effective transient thermal resistance (r(t)) as a function of time (t1) for a single pulse event. It includes the formula for calculating junction temperature based on power, thermal resistance, and ambient temperature, considering duty cycle.
Thermal characterization performed using the conditions described in Note 1c. Transient thermal response will change depending on the circuit board design.
Mechanical Case Outline
Package Dimensions: SOT-223, CASE 318H, ISSUE B
Date: 13 MAY 2020
Notes:
- DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 2009.
- CONTROLLING DIMENSION: MILLIMETERS
- DIMENSIONS D & E1 ARE DETERMINED AT DATUM H. DIMENSIONS DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. SHALL NOT EXCEED 0.23mm PER SIDE.
- LEAD DIMENSIONS b AND b1 DO NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBBAR PROTRUSION IS 0.08mm PER SIDE.
- DATUMS A AND B ARE DETERMINED AT DATUM H.
- A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY.
- POSITIONAL TOLERANCE APPLIES TO DIMENSIONS b AND b1.
| DIM | MIN. | NOM. | MAX. |
|---|---|---|---|
| A | 1.80 | ||
| A1 | 0.02 | 0.06 | 0.11 |
| b | 0.60 | 0.74 | 0.88 |
| b1 | 2.90 | 3.00 | 3.10 |
| C | 0.24 | 0.35 | |
| D | 6.30 | 6.50 | 6.70 |
| E | 6.70 | 7.00 | 7.30 |
| E1 | 3.30 | 3.50 | 3.70 |
| e | 2.30 BSC | ||
| L | 0.25 | ||
| 0° | 10° | ||
| -3.80 |
Generic Marking Diagram:
- A = Assembly Location
- Y = Year
- W = Work Week
- XXXXX = Specific Device Code
- Pb-Free Package
- (Note: Microdot may be in either location)
- *This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "", may or may not be present. Some products may not follow the Generic Marking.
Recommended Mounting Footprint:
For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Document Information
Document Number: 98ASH70634A
Description: SOT-223
Page: 1 OF 1
Additional Information
Technical Publications:
Technical Library: www.onsemi.com/design/resources/technical-documentation
onsemi Website: www.onsemi.com
Online Support:
For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales
