Intel FPGA Programmable Acceleration Card D5005 Tus Neeg Siv Qhia

Cov ntaub ntawv no piav qhia txog kev siv lub cim xeeb ncaj qha (DMA) Accelerator Functional Unit (AFU) thiab yuav ua li cas los tsim cov qauv tsim los khiav ntawm hardware lossis hauv simulation.

Lub Hom Phiaj

Cov neeg tuaj saib npaj muaj xws li kho vajtse lossis software tsim tawm uas yuav tsum muaj Kev Ua Haujlwm nrawm (AF) kom tsis txhob muaj cov ntaub ntawv hauv zos hauv lub cim xeeb txuas nrog Intel FPGA ntaus ntawv.

Cov rooj sib txoos

Cov ntaub ntawv Conventions

Convention	Kev piav qhia
#	Precedes ib lo lus txib uas qhia tias cov lus txib yuav tsum tau nkag mus rau hauv paus.
$	Qhia tau hais tias yuav tsum tau nkag mus ua tus neeg siv.
Qhov no font	Filecov npe, cov lus txib, thiab cov lus tseem ceeb tau luam tawm hauv daim ntawv no. Cov kab hais kom ntev tau luam tawm hauv daim ntawv no. Txawm hais tias cov kab hais kom ntev yuav qhwv mus rau kab tom ntej, qhov rov qab tsis yog ib feem ntawm cov lus txib; tsis txhob nias nkag.
	Qhia qhov chaw cov ntawv nyeem uas tshwm ntawm lub kaum sab xis yuav tsum tau hloov nrog tus nqi tsim nyog. Tsis txhob nkag mus rau lub kaum sab xis.

Cov ntsiab lus

Cov ntsiab lus	Kev nthuav dav	Kev piav qhia
AF	Accelerator muaj nuj nqi	Compiled Hardware Accelerator duab siv nyob rau hauv FPGA logic uas accelerates ib daim ntawv thov.
AFU	Accelerator Functional Unit	Kho vajtse Accelerator siv nyob rau hauv FPGA logic uas offloads ib tug xam ua hauj lwm rau ib daim ntawv thov los ntawm CPU los txhim kho kev ua tau zoo.
API	Daim ntawv thov Programming Interface	Cov txheej txheem subroutine txhais, raws tu qauv, thiab cov cuab yeej rau kev tsim software siv.
CCI-P	Core Cache Interface	CCI-P yog tus qauv interface AFUs siv los sib txuas lus nrog tus tswv tsev.
DFH	Ntaus Feature Header	Tsim ib daim ntawv txuas ntawm cov ntawv headers los muab txoj hauv kev txuas ntxiv ntawm kev ntxiv cov yam ntxwv.
*txuas ntxiv…*

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntsiab lus	Kev nthuav dav	Kev piav qhia
FIM	FPGA Interface Manager	FPGA kho vajtse uas muaj FPGA Interface Unit (FIU) thiab sab nraud interfaces rau kev nco, kev sib txuas, thiab lwm yam. Lub Accelerator Function (AF) cuam tshuam nrog FIM thaum lub sijhawm ua haujlwm.
FIU	FPGA Interface Unit	FIU yog txheej txheej txheej txheej txheej txheej platform uas ua tus choj ntawm lub platform interfaces xws li PCIe *, UPI thiab AFU-sab interfaces xws li CCI-P.
MPF	Memory Properties Factory	MPF yog ib qho Kev Txhim Kho Hauv Tsev (BBB) uas AFUs tuaj yeem siv los muab CCI-P kev tsim kho tsheb khiav lag luam rau kev lag luam nrog FIU.

Acceleration Glossary

Acceleration Stack rau Intel® Xeon® CPU nrog FPGAs Glossary

Lub sij hawm	Cov ntawv luv	Kev piav qhia
Intel® Acceleration Stack rau Intel Xeon® CPU nrog FPGAs	Acceleration Stack	Ib qho kev sau ntawm software, firmware, thiab cov cuab yeej uas muab kev ua tau zoo- optimized txuas ntawm Intel FPGA thiab Intel Xeon processor.
Intel FPGA Programmable Acceleration Card	Intel FPGA PAC Cov	PCIe FPGA accelerator daim npav. Muaj FPGA Interface Manager (FIM) uas ua ke nrog Intel Xeon processor hla lub npav PCIe.

DMA Accelerator Functional Unit User Guide: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Description

Taw qhia

Direct Memory Access (DMA) AFU example qhia yuav ua li cas tswj kev hloov pauv kev nco ntawm tus tswv tsev processor thiab FPGA. Koj tuaj yeem ua ke DMA AFU rau hauv koj tus qauv tsim kom txav cov ntaub ntawv ntawm tus tswv nco thiab FPGA lub cim xeeb hauv zos.DMA AFU suav nrog cov hauv qab no:

Memory Properties Factory (MPF) Basic Building Block (BBB)

Core Cache Interface (CCI-P) rau Avalon® Memory-Mapped (Avalon-MM) Adapter
DMA Test System uas muaj DMA BBB

Cov submodules no tau piav qhia ntau ntxiv hauv DMA AFU Hardware Components cov ntsiab lus hauv qab no.

Cov ntaub ntawv ntsig txog

DMA AFU Hardware Cheebtsam ntawm nplooj 6
Avalon Interface Specifications

Yog xav paub ntxiv txog Avalon-MM raws tu qauv, suav nrog cov duab kos lub sijhawm rau kev nyeem thiab sau kev lag luam.

DMA AFU Software Pob

Intel Acceleration Stack rau Intel Xeon CPU nrog FPGAs pob file (*.tar.gz), suav nrog DMA AFU example. Qhov no example muab tus neeg siv qhov chaw tsav tsheb. Tus tswv tsev daim ntawv thov siv tus tsav tsheb no xws li DMA txav cov ntaub ntawv ntawm tus tswv tsev thiab FPGA nco. Lub hardware binaries, qhov chaw, thiab tus neeg siv qhov chaw tsav tsheb muaj nyob rau hauv cov npe hauv qab no: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu . Ua ntej sim nrog DMA AFU, koj yuav tsum nruab qhov Open Programmable Acceleration Engine (OPAE) software pob. Xa mus rau Kev Txhim Kho OPAE Software Package hauv Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005 rau cov lus qhia kev teeb tsa. Phau Ntawv Qhia Pib Ceev no kuj suav nrog cov ntaub ntawv yooj yim hais txog Open Programmable Acceleration Engine (OPAE) thiab teeb tsa AFU. Tom qab txhim kho Open Programmable Acceleration Engine (OPAE) software pob, xws liample host daim ntawv thov thiab DMA AFU tus neeg siv chaw tsav tsheb muaj nyob rau hauv cov npe hauv qab no: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw. Kom khiav sample host daim ntawv thov, fpga_dma_test ntawm koj Intel FPGA PAC D5005 kho vajtse, xa mus rau cov kauj ruam hauv ntu Khiav DMA AFU Example. Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Cov ntaub ntawv ntsig txog

Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005
Txhim kho OPAE Software Pob

DMA AFU Hardware Cheebtsam

Lub DMA AFU cuam tshuam nrog FPGA Interface Unit (FIU) thiab FPGA nco. Xa mus rau FPGA Interface Manager Data Sheet rau Intel FPGA Programmable Acceleration Card D5005 rau cov ncauj lus kom ntxaws ntawm FPGA nco. Cov cuab yeej muaj tam sim no dictates lub cim xeeb configuration. Cov khoom siv yav tom ntej tuaj yeem txhawb nqa cov cim xeeb sib txawv. Koj tuaj yeem siv DMA AFU los luam cov ntaub ntawv ntawm qhov chaw hauv qab no thiab qhov chaw nyob:

Tus tswv tsev rau ntaus ntawv FPGA nco
Ntaus FPGA nco rau tus tswv tsev

Lub Platform Designer system, $OPAE_PLATFORM_ROOT/hw/samples/ dma_afu/hw/rtl/TEST_dma/ /dma_test_system.qsys siv feem ntau ntawm DMA

AFU. Ib feem ntawm DMA AFU siv hauv Platform Designer system tuaj yeem pom hauv qab no

qhov chaw: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/ Koj tuaj yeem nrhiav DMA BBB hauv qhov chaw hauv qab no:

$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/dma_bb

DMA Accelerator Functional Unit User Guide: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Hardware Block Diagram

Lub DMA AFU suav nrog cov nram qab no sab hauv modules interface nrog FPGA Interface Unit (FIU):

Memory-Mapped IO (MMIO) Decoder Logic: ntes MMIO nyeem thiab sau kev lag luam thiab cais lawv los ntawm CCI-P RX channel 0 uas lawv tuaj txog. Qhov no ua kom ntseeg tau tias MMIO kev tsheb tsis tau mus txog MPF BBB thiab tau txais kev pabcuam los ntawm MMIO cov lus txib ywj pheej.
Memory Properties Factory (MPF): Cov qauv no ua kom ntseeg tau tias nyeem cov lus teb los ntawm DMA rov qab los ntawm qhov kev txiav txim uas lawv tau tshaj tawm. Avalon-MM raws tu qauv yuav tsum tau nyeem cov lus teb kom rov qab los ntawm qhov tseeb.
CCI-P rau Avalon-MM Adapter: Cov qauv no txhais ntawm CCI-P thiab Avalon-MM kev lag luam, raws li hauv qab no:
CCI-P rau Avalon-MMIO Adapter: Txoj kev no txhais CCI-P MMIO kev lag luam rau hauv Avalon-MM kev lag luam.
Avalon rau CCI-P Host Adapter: Cov kab no tsim cais kev nyeem nkaus xwb thiab sau nkaus xwb rau DMA kom nkag mus rau lub cim xeeb.
DMA Test System: Cov qauv no ua haujlwm raws li ib puag ncig ntawm DMA BBB kom nthuav tawm DMA tus tswv mus rau qhov seem ntawm cov logic hauv AFU. Nws muab qhov sib txuas ntawm DMA BBB thiab CCI-P rau Avalon Adapter. Nws kuj tseem muab qhov sib txuas ntawm DMA BBB thiab cov tsev txhab nyiaj FPGA SDRAM hauv zos.

Cov ntaub ntawv ntsig txog
FPGA Interface Manager Cov Ntawv Qhia rau Intel FPGA Programmable Acceleration Card D5005

DMA Test System

DMA xeem system txuas DMA BBB mus rau tus so ntawm FPGA tsim nrog rau CCI-P adaptation thiab lub zos FPGA nco.

DMA Test System Block Diagram
Daim duab thaiv no qhia tau hais tias lub internals ntawm DMA xeem system. DMA xeem system yog qhia raws li ib tug monolithic thaiv nyob rau hauv daim duab 1 ntawm nplooj 7.

Lub DMA xeem system suav nrog cov hauv qab no modules:

Far Reach Choj / Pipeline Choj: Lub kav dej txuas txuas nrog kev hloov kho latency suav nrog los tswj topology thiab txhim kho tus tsim Fmax.

DMA AFU Device Feature Header (DFH): Qhov no yog DFH rau DMA AFU. Qhov DFH no taw qhia rau DFH tom ntej nyob rau ntawm offset 0x100 (DMA BBB DFH).
Null DFH: Cov khoom no txiav tawm DFH txuas-cov npe. Yog tias koj ntxiv DMA BBBs ntxiv rau qhov tsim, xyuas kom meej tias qhov chaw nyob tsis muaj DFH nyob rau hauv qhov kawg ntawm DFH txuas-daim ntawv.
MA Basic Building Block (BBB): Qhov thaiv no txav cov ntaub ntawv ntawm tus tswv tsev thiab lub cim xeeb FPGA hauv zos. Nws kuj tseem nkag tau lub cim xeeb nkag mus rau cov kab lus piav qhia.

DMA BBB

DMA BBB subsystem hloov cov ntaub ntawv los ntawm qhov chaw mus rau qhov chaw nyob siv Avalon-MM kev hloov pauv. Tus tsav tsheb DMA tswj DMA BBB los ntawm kev nkag mus rau kev tswj hwm thiab kev sau npe ntawm ntau yam hauv lub cev. Tus neeg tsav tsheb DMA kuj tseem tswj hwm DMA BBB los ntawm kev siv lub cim xeeb sib koom los sib txuas lus hloov cov lus piav qhia. DMA BBB nkag mus rau cov ntaub ntawv hauv FPGA nco ntawm offset 0x0. DMA BBB nkag mus rau cov ntaub ntawv thiab cov lus piav qhia hauv lub cim xeeb ntawm tus tswv ntawm offset 0x1_0000_0000_0000.

DMA BBB Platform Designer Block Diagram
Daim duab thaiv no tsis suav nrog qee qhov hauv Pipeline Choj IP cores.

DMA Accelerator Functional Unit User Guide: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Description

Cov khoom hauv DMA BBB Platform Designer siv cov haujlwm hauv qab no:

Far Reach Choj / Pipeline Choj: Ib tug kav kav dej nrog adjustable latency nrog rau tswj topology thiab txhim kho tus tsim Fmax.
MA BBB DFH: Qhov no yog ib tug ntaus ntawv feature header rau DMA BBB. Qhov DFH no taw qhia rau DFH tom ntej nyob rau ntawm offset 0x100 (Null DFH).
Kev piav qhia Frontend: Lub luag haujlwm rau nqa cov lus piav qhia thiab xa mus rau Dispatcher. Thaum DMA hloov mus ua tiav lub frontend tau txais cov xwm txheej tsim los ntawm Dispatcher thiab overwrite tus piav qhia hauv lub cim xeeb tswv.

Dispatcher: Qhov thaiv no teem sijhawm DMA hloov pauv thov rau Nyeem thiab Sau Master.
Nyeem Master: Qhov thaiv no yog lub luag haujlwm rau kev nyeem cov ntaub ntawv los ntawm tus tswv tsev lossis hauv zos FPGA nco thiab xa nws ua cov ntaub ntawv streaming rau Sau Master.
Sau Master: Qhov thaiv no yog lub luag haujlwm kom tau txais cov ntaub ntawv streaming los ntawm Read Master thiab sau cov ntsiab lus rau tus tswv tsev lossis lub cim xeeb FPGA hauv zos.

Sau npe Daim Ntawv Qhia thiab Chaw Nyob

DMA AFU txhawb nqa ob lub cim xeeb views: DMA view thiab tus tswv tsev view. Lub DMA view txhawb qhov chaw nyob 49-ntsis. Qhov qis dua ib nrab ntawm DMA view maps rau lub zos FPGA nco. Sab saum toj ib nrab ntawm DMA view maps rau host nco. Tus tswv view suav nrog tag nrho cov ntawv sau npe nkag tau los ntawm MMIO nkag mus xws li DFH cov rooj, thiab kev tswj hwm / xwm txheej sau npe ntawm ntau tus IP cores siv hauv DMA AFU. MMIO sau npe hauv DMA BBB thiab AFU txhawb 32- thiab 64-ntsis nkag. DMA AFU tsis txhawb 512-ntsis MMIO nkag mus. Kev nkag mus rau Dispatcher sau npe hauv DMA BBB yuav tsum yog 32 khoom (Tus piav qhia frontend siv 64-ntsis sau npe).

DMA AFU Sau npe daim ntawv qhia

Daim ntawv qhia DMA AFU sau npe muab qhov chaw nyob ntawm txhua qhov chaw nyob hauv chav tsev. Cov ntawv sau npe no nyob hauv tus tswv tsev view vim nws tsuas yog tus tswv uas tuaj yeem nkag tau rau lawv.

DMA AFU Memory Map

Byte Chaw Nyob Offsets	Lub npe	Span hauv Bytes	Kev piav qhia
0 x 0	DMA UAS DFH	0 x 40	Ntaus feature header rau DMA AFU. ID_L yog teem rau 0x9081f88b8f655caa thiab ID_H yog teem rau 0x331db30c988541ea. Lub DMA AFU DFH tau raug parameterized los taw tes rau offset 0x100 mus nrhiav DFH tom ntej (DMA BBB DFH). Koj yuav tsum tsis txhob hloov lub hauv paus chaw nyob ntawm DMA AFU DFH vim nws yuav tsum nyob ntawm qhov chaw nyob 0x0 raws li tau hais los ntawm CCIP specification.
0 x 100	DMA BBB	0 x 100	Qhia meej DMA BBB tswj thiab xwm txheej sau npe interface. Koj tuaj yeem xa mus rau DMA BBB daim ntawv teev npe rau cov lus qhia ntxiv. Hauv DMA BBB ntawm offset 0 DMA BBB suav nrog nws tus kheej DFH. Qhov DFH no tau teeb tsa kom pom DFH tom ntej ntawm offset 0x100 (NULL DFH). Yog tias koj ntxiv DMA BBBs ntau dua, muab lawv 0x100 sib nrug thiab xyuas kom NULL DFH ua raws li DMA kawg los ntawm 0x100.
0 x 200	NULL DFH	0 x 40	Terminates DFH linked-lists. ID_L yog teem rau 0x90fe6aab12a0132f thiab ID_H yog teem rau 0xda1182b1b3444e23. NULL DFH tau raug ntsuas los ua DFH kawg hauv kev kho vajtse. Vim li no NULL DFH nyob ntawm qhov chaw nyob 0x200. Yog tias koj ntxiv DMA BBBs ntxiv rau lub kaw lus, koj yuav tsum tau nce NULL DFH qhov chaw nyob raws li nws nyob ntawm qhov chaw siab tshaj. Tus tsav tsheb DMA thiab daim ntawv thov xeem tsis siv cov khoom siv no.

Sau npe Daim Ntawv Qhia thiab Chaw Nyob

DMA BBB Memory Map
Cov chaw nyob hauv qab no yog cov txheeb ze offsets los ntawm DMA BBB qhov chaw nyob hauv DMA AFU system (0x100).

Byte Chaw Nyob Offsets	Lub npe	Span hauv Bytes	Kev piav qhia
0 x 0	DMA IB DFH	0 x 40	Ntaus feature header rau DMA AFU. ID_L yog teem rau 0xa9149a35bace01ea thiab ID_H yog teem rau 0xef82def7f6ec40fc . Lub DMA BBB DFH tau raug ntsuas los taw tes rau 0x100 rau DFH tom ntej offset. Qhov offset tom ntej no tuaj yeem yog lwm DMA BBB, lwm DFH (tsis suav nrog hauv qhov tsim), lossis NULL DFH.
0 x 40	Dispatcher	0 x 40	Tswj chaw nres nkoj rau dispatcher. Tus tsav tsheb DMA siv qhov chaw no los tswj DMA lossis nug nws cov xwm txheej.
0 x 80	Kev piav qhia Frontend	0 x 40	Tus piav qhia frontend yog ib qho kev cai tivthaiv uas nyeem cov lus piav qhia los ntawm tus tswv lub cim xeeb thiab sau cov lus piav qhia thaum hloov DMA ua tiav. Tus neeg tsav tsheb qhia qhov frontend qhov twg thawj tus piav qhia nyob hauv lub cim xeeb ntawm tus tswv thiab tom qab ntawd cov khoom siv sab hauv txuas lus nrog tus tsav tsheb feem ntau txawm tias cov lus piav qhia khaws cia hauv lub cim xeeb.

DMA AFU Chaw Nyob

Tus tswv tsev tuaj yeem nkag mus rau cov npe sau npe hauv Table 4 ntawm nplooj ntawv 12 thiab Table 5 ntawm nplooj 13. Lub DMA BBB subsystem tau nkag mus rau tag nrho 49-ntsis chaw nyob. Qhov qis dua ib nrab ntawm qhov chaw nyob no suav nrog FPGA cov cim hauv zos. Sab saum toj ib nrab ntawm qhov chaw nyob no suav nrog 48-ntsis host chaw nyob nco. Cov duab hauv qab no qhia txog tus tswv tsev thiab DMA views nco.

DMA AFU thiab Tus Tswv Views nco

Device Feature Header Linked List

DMA AFU tsim example muaj peb lub cuab yeej feature headers (DFH) uas tsim cov npe txuas. Cov npe txuas no tso cai rau sample daim ntawv thov txhawm rau txheeb xyuas DMA AFU nrog rau tus tsav tsheb txhawm rau txheeb xyuas DMA BBB. Cov npe DFH suav nrog NULL DFH thaum kawg. Kev suav nrog ntawm qhov tsis muaj DFH kawg ntawm cov npe txuas tso cai rau koj ntxiv DMA BBBs ntxiv rau koj tus qauv tsim. Koj tsuas yog yuav tsum txav NULL DFH mus rau qhov chaw nyob tom qab lwm BBBs. Txhua DMA BBB cia siab tias tom ntej no DFH yuav tsum nyob 0x100 bytes los ntawm lub hauv paus chaw nyob ntawm BBB. Cov duab hauv qab no qhia txog cov npe txuas rau DMA AFU tsim example.

Sau npe Daim Ntawv Qhia thiab Chaw Nyob

DMA AFU Device Feature Header (DFH) Chaining

Software Programming Model

DMA AFU suav nrog software tsav tsheb uas koj tuaj yeem siv hauv koj tus kheej daim ntawv thov. Lub fpga_dma.cpp thiab fpga_dma.h files nyob ntawm qhov chaw hauv qab no siv tus tsav tsheb software: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw Tus tsav tsheb no txhawb nqa cov haujlwm hauv qab no:

API	Kev piav qhia
fpgaCountDMAChannels	Tshawb xyuas cov cuab yeej feature saw rau DMA BBBs thiab suav tag nrho cov channel muaj.
fpgaDMAOpen	Qhib tus kov rau DMA channel.
fpgaDMAClose	Kaw ib tug kov rau DMA channel.
fpgaDMATransferInit	Initializes ib yam khoom uas sawv cev rau kev hloov DMA.
fpgaDMATransferReset	Resets DMA hloov tus cwj pwm khoom mus rau qhov tseem ceeb.
fpgaDMATransferDestroy	Ua kom DMA hloov tus cwj pwm khoom.
fpgaDMATransferSetSrc	Teem lub qhov chaw nyob ntawm kev hloov. Qhov chaw nyob no yuav tsum yog 64 byte dlhos.
fpgaDMATransferSetDst	Teem caij qhov chaw nyob ntawm qhov kev hloov mus. Qhov chaw nyob no yuav tsum yog 64 byte dlhos.
fpgaDMATransferSetLen	Teem lub sijhawm hloov mus rau hauv bytes. Rau kev hloov pauv tsis yog pob ntawv, koj yuav tsum teem sijhawm hloov mus rau ntau yam ntawm 64 bytes. Rau pob ntawv hloov tsheb, qhov no tsis yog qhov yuav tsum tau ua.
fpgaDMATransferSetTransferType	Teem hom hloov pauv. Cov nqi raug cai yog: • HOST_MM_TO_FPGA_MM = TX (Host to AFU) • FPGA_MM_TO_HOST_MM = RX (AFU to host)
fpgaDMATransferSetTransferCallback	Sau npe hu rov qab rau kev ceeb toom ntawm kev hloov pauv asynchronous tiav. Yog hais tias koj teev ib tug callback, fpgaDMATransfer rov qab tam sim ntawd (asynchronous hloov). Yog tias koj tsis qhia qhov hu rov qab, fpgaDMATransfer rov qab los tom qab kev hloov pauv tiav (synchronous / thaiv kev hloov pauv).
fpgaDMATransferSetLast	Qhia txog kev hloov pauv zaum kawg kom DMA tuaj yeem pib ua cov kev hloov pauv ua ntej. Tus nqi qub yog 64 kev hloov pauv hauv cov raj xa dej ua ntej DMA pib ua haujlwm ntawm kev hloov pauv.
fpgaDMATransfer	Ua qhov hloov pauv DMA.

Yog xav paub ntxiv txog API, kev tawm tswv yim, thiab cov lus tawm tswv yim, xa mus rau lub header file nyob $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw/fpga_dma.hIntel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. Lwm lub npe thiab cov npe yuav raug lees paub tias yog cov cuab yeej ntawm lwm tus.

Software Programming Model

Txhawm rau paub ntau ntxiv txog software siv tus qauv, xa mus rau README file nyob ntawm $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/README.md

Khiav DMA AFU Example

Ua ntej koj pib:

Koj yuav tsum paub txog tus examples hauv Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005.
Koj yuav tsum txhais ib puag ncig hloov pauv. Qhov kev hloov pauv ib puag ncig yog nyob ntawm Intel Acceleration Stack version koj siv:
- Rau tam sim no version, teem ib puag ncig hloov pauv mus rau $OPAE_PLATFORM_ROOT
Koj yuav tsum nruab lub tsev qiv ntawv Intel Threading Building Blocks (TBB) txij li tus tsav DMA tso siab rau nws.
Koj kuj yuav tsum teeb tsa ob 1 GB nplooj ntawv loj los khiav sampua application. $ sudo sh -c "echo 2 > /sys/kernel/mm/hugepages/hugepages-1048576kB/ nr_hugepages"

Ua cov kauj ruam hauv qab no txhawm rau rub tawm DMA Accelerator Function (AF) bitstream, tsim daim ntawv thov thiab tsav tsheb, thiab khiav tus tsim example:

Hloov mus rau DMA daim ntawv thov thiab cov ntawv tsav tsheb: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw
Tsim tus tsav tsheb thiab daim ntawv thov: ua

Rub tawm DMA AFU bitstream: sudo fpgasupdate ../bin/dma_afu_unsigned.gbs
Ua tus tswv daim ntawv thov sau 100 MB hauv 1 MB feem ntawm lub cim xeeb rau FPGA ntaus ntawv nco thiab nyeem nws rov qab: ./ fpga_dma_test -s 104857600 -p 1048576 -r mtom

Cov ntaub ntawv ntsig txog
Intel Acceleration Stack Quick Start Guide rau Intel FPGA Programmable Acceleration Card D5005 Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Compiling DMA AFU Example

Txhawm rau tsim kom muaj kev sib txuas tsim ib puag ncig los ua ke AF, siv afu_synth_setup hais kom ua raws li hauv qab no:

Hloov mus rau DMA AFU sample directory: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu
Tsim cov ntawv tsim tsim: afu_synth_setup –source hw/rtl/filelist.txt build_synth

Los ntawm cov synthesis tsim directory generated los ntawm afu_synth_setup, nkag mus rau cov lus txib hauv qab no los ntawm lub qhov rais davhlau ya nyob twg los tsim ib qho AF rau lub hom phiaj kho vajtse platform: cd build_synth run.sh Lub run.sh AF tiam ntawv tsim cov duab AF nrog tib lub hauv paus filenpe raws li AFU's platform configuration file (.json) nrog rau .gbs cov lus xaus ntawm qhov chaw: $ OPAE_PLATFORM_ROOT/hw/samples/build_synth/dma_afu_s10.gbs Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais cov khoom siv tshwj xeeb tshaj tawm ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Simulating AFU Example

Intel xav kom koj xa mus rau Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start Guide rau koj Intel FPGA PAC kom paub txog kev simulating zoo li qub.amples thiab teeb tsa koj ib puag ncig. Ua ntej koj mus dhau cov kauj ruam hauv qab no, xyuas kom meej tias OPAE_PLATFORM_ROOT ib puag ncig hloov pauv tau teeb tsa rau OPAE SDK daim ntawv teev npe. Ua kom tiav cov kauj ruam hauv qab no los teeb tsa lub hardware simulator rau DMA AFU:

Hloov mus rau DMA AFU sample directory: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu

Tsim ib qho chaw ASE hauv phau ntawv teev npe tshiab thiab teeb tsa nws rau simulating AFU: afu_sim_setup -source hw/rtl/filelist.txt build_ase_dir
Hloov mus rau ASE build directory: cd build_ase_dir
Tsim tus tsav tsheb thiab daim ntawv thov: ua

Ua simulation: ua sim

Sample tso zis los ntawm hardware simulator:

[SIM] ** CEEB TOOM : Ua ntej khiav lub software thov ** [SIM] Teem env(ASE_WORKDIR) hauv davhlau ya nyob twg uas daim ntawv thov yuav khiav (copy-and-paste) => [SIM] $SHELL | Khiav: [SIM] ———+—————————————————— [SIM] bash/zsh | export ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] Rau lwm yam $SHELL, sab laj nrog koj tus thawj coj Linux [SIM] [SIM] Npaj rau simulation… [SIM] Nias CTRL-C kom kaw simulator…

Ua kom tiav cov kauj ruam hauv qab no los sau thiab ua tiav DMA AFU software hauv qhov chaw simulation:

Qhib lub qhov rais davhlau ya nyob twg tshiab.
Hloov cov npe rau: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw

Simulating AFU Example

Luam cov kab teeb tsa ib puag ncig (xaiv txoj hlua tsim nyog rau koj lub plhaub) los ntawm cov kauj ruam saum toj no hauv kev sim kho vajtse mus rau lub qhov rais davhlau ya nyob twg. Saib cov kab hauv qab no hauv sample tso zis los ntawm hardware simulator. [SIM] bash/zsh | export ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/ ua
Sau cov software: $ ua USE_ASE=1

Ua tus tswv tsev daim ntawv thov sau 4 KB hauv 1 KB feem los ntawm tus tswv nco rov qab mus rau FPGA ntaus ntawv nco hauv lub voj rov qab hom: ./ fpga_dma_test -s 4096 -p 1024 -r mtom

Cov ntaub ntawv ntsig txog
Intel Accelerator Functional Unit (AFU) Simulation Ib puag ncig (ASE) Phau Ntawv Qhia Ceev Cov Neeg Siv

Kev ua kom zoo rau kev txhim kho DMA kev ua tau zoo

Kev nqis tes ua ntawm NUMA (non-uniform memory access) optimization hauv fpga_dma_test.cpp tso cai rau lub processor nkag mus rau nws lub cim xeeb hauv zos sai dua li kev nkag mus rau lub cim xeeb tsis nyob hauv zos (nco hauv zos rau lwm tus processor). Ib qho NUMA kev teeb tsa raug pom hauv daim duab hauv qab no. Cov kev nkag hauv zos sawv cev rau kev nkag los ntawm ib qho tseem ceeb rau lub cim xeeb hauv zos mus rau tib lub core. Kev nkag mus rau tej thaj chaw deb qhia txog txoj kev coj mus rau thaum lub hauv paus ntawm Node 0 nkag mus rau lub cim xeeb uas nyob hauv lub cim xeeb hauv zos rau Node 1.

Hom NUMA Configuration

Siv cov cai hauv qab no los siv NUMA optimization hauv koj daim ntawv thov xeem:

// Teeb tsa affinity kom raug yog thov yog (cpu_affinity || memory_affinity) {unsigned dom = 0, bus = 0, dev = 0, func = 0; fpga_properties cov khoom siv; int retval; #if(FPGA_DMA_DEBUG)char str[4096]; #endifres = fpgaGetProperties(afc_token, &props); ON_ERR_GOTO(res, out_destroy_tok, “fpgaGetProperties”); res = fpgaPropertiesGetBus(props, (uint8_t *) & bus);ON_ERR_GOTO(res, out_destroy_tok, "fpgaPropertiesGetBus"); res = fpgaPropertiesGetDevice(props, (uint8_t *) & dev);ON_ERR_GOTO(res, out_destroy_tok, "fpgaPropertiesGetDevice") res = fpgaPropertiesGetFunction(props, (uint8_t *) & func); ON_ERR_GOTO(fction, out_gat); // Nrhiav cov cuab yeej los ntawm topology hwloc_topology_t topology; hwloc_topology_init(&topology); hwloc_topology_set_flags(topology, HWLOC_TOPOLOGY_FLAG_IO_DEVICES); Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom siv semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Kev ua kom zoo rau kev txhim kho DMA kev ua tau zoo

hwloc_topology_load(topology); hwloc_obj_t obj = hwloc_get_pcidev_by_busid(topology, dom, bus, dev, func); hwloc_obj_t obj2 = hwloc_get_non_io_ancestor_obj(topology, obj); #if (FPGA_DMA_DEBUG) hwloc_obj_type_snprintf(str, 4096, obj2, 1); printf(“%s\n”, str);hwloc_obj_attr_snprintf(str, 4096, obj2, ” :: “, 1); printf(“%s\n”, str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2->cpuset); printf("CPUSET yog %s\n", str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2->nodeset); printf(“NODESET is %s\n”, str);#endif if (memory_affinity) { #if HWLOC_API_VERSION > 0x00020000 retval = hwloc_set_membind(topology, obj2->nodeset,HWLOC_MEMBATEMBWINDWCAD_HWLOC_MEMBATEMBWINDWCAD _BYNODESET); #else retval =hwloc_set_membind_nodeset(topology, obj2->nodeset, HWLOC_MEMBIND_THREAD,HWLOC_MEMBIND_MIGRATE); #endifON_ERR_GOTO(retval, out_destroy_tok, "hwloc_set_membind"); } if (cpu_affinity) { retval = hwloc_set_cpubind(topology, obj2->cpuset, HWLOC_CPUBIND_STRICT); ON_ERR_GOTO(retval, out_destroy_tok, "hwloc_set_cpubind"); }}

DMA Accelerator Functional Unit Cov neeg siv phau ntawv qhia Archives

Intel Acceleration Stack Version	Tus neeg siv phau ntawv (PDF)
2.0	DMA Accelerator Functional Unit (AFU) Phau Ntawv Qhia

Cov ntaub ntawv kho dua tshiab rau DMA Accelerator Functional Unit User Guide

Cov ntaub ntawv Version

Intel Acceleration Stack Version

Hloov

2020.08.03

2.0.1 (txhawb nrog Intel

Quartus® Prime Pro Tsab Ntawv 19.2)

Kho cov duab AF file npe nyob rau hauv seem Compiling DMA AFU Example.

2020.04.17

2.0.1 (txhawb nrog Intel

Quartus Prime Pro Tsab Ntawv 19.2)

Kho ib nqe lus hauv Lub Hom Phiaj ntu.

2020.02.20

2.0.1 (txhawb nrog Intel

Quartus Prime Pro Tsab Ntawv 19.2)

Tsau typo.

2019.11.04

2.0.1 (txhawb nrog Intel

Quartus Prime Pro Tsab Ntawv 19.2)

• Hloov cov fpgaconf nrog fpgasupdate thaum teeb tsa FPGA nrog prebuild AFU hauv ntu Khiav DMA AFU Example.

• Ntxiv subtitle Intel FPGA Programmable Acceleration Card D5005 mus rau lub npe ntaub ntawv.

• Ntxiv ib puag ncig hloov pauv $OPAE_PLATFORM_ROOT.

• Hloov kho ntu Software Programming Model rau kev kho me me.

• Ntxiv ntu tshiab Compiling DMA AFU Example.

• Hloov kho ntu Kev ua kom zoo rau kev txhim kho DMA kev ua tau zoo rau kev kho me me.

2019.08.05

2.0 (txhawb nrog Intel

Quartus Prime Pro tsab 18.1.2)

Kev tso tawm thawj zaug.

Lwm lub npe thiab cov npe yuav raug lees paub tias yog cov cuab yeej ntawm lwm tus.

Cov ntaub ntawv / Cov ntaub ntawv

Intel FPGA Programmable Acceleration Card D5005 [ua pdf] Cov neeg siv phau ntawv qhia
FPGA Programmable Acceleration Card, D5005, FPGA Programmable Acceleration Card D5005, DMA Accelerator Functional Unit

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Intel FPGA Programmable Acceleration Card D5005

Hais txog Cov Ntaub Ntawv no

DMA AFU Description

Sau npe Daim Ntawv Qhia thiab Chaw Nyob

DMA AFU Sau npe daim ntawv qhia

Sau npe Daim Ntawv Qhia thiab Chaw Nyob

Software Programming Model

Khiav DMA AFU Example

Compiling DMA AFU Example

Simulating AFU Example

Kev ua kom zoo rau kev txhim kho DMA kev ua tau zoo

DMA Accelerator Functional Unit Cov neeg siv phau ntawv qhia Archives

Cov ntaub ntawv kho dua tshiab rau DMA Accelerator Functional Unit User Guide

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