Intel FPGA Shirye-shiryen Hanzarta Katin D5005 Jagorar Mai Amfani

Wannan daftarin aiki yana bayyana aiwatar da damar ƙwaƙwalwar ajiya kai tsaye (DMA) Accelerator Functional Unit (AFU) aiwatarwa da yadda ake gina ƙira don aiki akan kayan aiki ko a simulation.

Masu Sauraron Niyya

Masu sauraro da aka nufa sun ƙunshi kayan aiki ko masu haɓaka software waɗanda ke buƙatar Accelerator Aiki (AF) don adana bayanai a cikin gida cikin ƙwaƙwalwar ajiya da aka haɗa da na'urar Intel FPGA.

Taro

Takardun Yarjejeniyar

Babban taro	Bayani
#	Gabatar da umarni wanda ke nuna umarnin shine a shigar dashi azaman tushen.
$	Yana nuna umarni da za a shigar da shi azaman mai amfani.
Wannan font	FileAna buga sunaye, umarni, da kalmomi masu mahimmanci a cikin wannan font. Ana buga dogayen layin umarni a cikin wannan font. Kodayake dogayen layukan umarni na iya naɗe zuwa layi na gaba, dawowar ba ta cikin umarnin; kar a danna shiga.
	Yana nuna rubutun maƙerin da ke bayyana tsakanin maƙallan kusurwa dole ne a maye gurbinsa da ƙimar da ta dace. Kada a shigar da maƙallan kusurwa.

Acronyms

Acronyms	Fadadawa	Bayani
AF	Aikin Hanzarta	Haɗaɗɗen Hoton Hanzarta Hardware wanda aka aiwatar a cikin dabaru na FPGA wanda ke hanzarta aikace-aikace.
AFU	Rukunin Aiki na Hanzarta	Hardware Accelerator wanda aka aiwatar a cikin ma'ana ta FPGA wanda ke sauke aikin lissafi don aikace-aikace daga CPU don haɓaka aiki.
API	Interface Programming Application	Saitin ma'anoni na ƙasa da ƙasa, ƙa'idodi, da kayan aikin gina aikace-aikacen software.
CCI-P	Core Cache Interface	CCI-P shine daidaitaccen ƙirar AFUs da ake amfani da su don sadarwa tare da mai watsa shiri.
DFH	Jigon Siffar Na'ura	Yana ƙirƙira jeri mai alaƙa na masu kan sifofi don samar da hanyar ƙara fasali mai iyawa.
*ci gaba…*

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Acronyms	Fadadawa	Bayani
FIM	FPGA Interface Manager	Kayan aikin FPGA mai ɗauke da FPGA Interface Unit (FIU) da musaya na waje don ƙwaƙwalwar ajiya, hanyar sadarwa, da sauransu. Ayyukan Accelerator (AF) suna mu'amala da FIM a lokacin gudu.
FIU	FPGA Interface Unit	FIU wani dandali ne wanda ke aiki a matsayin gada tsakanin musaya na dandamali kamar PCIe *, UPI da AFU-gefe musaya kamar CCI-P.
MPF	Ma'aikatar Kayayyakin Ƙwaƙwalwa	MPF shine Tushen Ginin Gine-gine (BBB) wanda AFUs za su iya amfani da su don samar da ayyukan siffanta zirga-zirgar CCI-P don ma'amaloli tare da FIU.

Gaggauta ƙamus

Tarin Haɗawa don Intel® Xeon® CPU tare da ƙamus na FPGAs

Lokaci	Gajarta	Bayani
Intel® Acceleration Stack don Intel Xeon® CPU tare da FPGAs	Hanzarta Tari	Tarin software, firmware, da kayan aikin da ke ba da ingantaccen haɗin kai tsakanin Intel FPGA da na'ura mai sarrafa Intel Xeon.
Katin Hanzarta Mai Shirye-shiryen Intel FPGA	Farashin Intel FPGA PAC	PCIe FPGA accelerator katin. Ya ƙunshi Manajan Interface na FPGA (FIM) wanda ke haɗe tare da na'ura mai sarrafa Intel Xeon akan bas ɗin PCIe.

Jagorar Mai Amfani na Aikin Sashen Aikin DMA: Intel FPGA Mai Shirye-shiryen Hanzarta Katin D5005

Bayanin DMA AFU

Gabatarwa

The Direct Memory Access (DMA) AFU example yana nuna yadda ake sarrafa canja wurin ƙwaƙwalwar ajiya tsakanin mai sarrafa mai watsa shiri da FPGA. Kuna iya haɗa DMA AFU a cikin ƙirar ku don matsar da bayanai tsakanin ƙwaƙwalwar ajiyar mai watsa shiri da ƙwaƙwalwar gida ta FPGA. DMA AFU ta ƙunshi ƙananan ƙananan abubuwa masu zuwa:

Ma'aikatar Kayayyakin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Ƙadda ) )

Core Cache Interface (CCI-P) zuwa Avalon® Memory-Mapped (Avalon-MM) Adaftar
Tsarin Gwajin DMA wanda ya ƙunshi DMA BBB

An siffanta waɗannan ƙananan ƙa'idodi dalla-dalla a cikin jigon Abubuwan Abubuwan Hardware na DMA AFU da ke ƙasa.

Bayanai masu alaƙa

Abubuwan Hardware na DMA AFU akan shafi na 6
Avalon Interface Takaddun Shaida

Don ƙarin bayani game da ƙa'idar Avalon-MM, gami da zane-zane na lokaci don karantawa da rubuta ma'amaloli.

Kunshin Software na DMA AFU

Tarin Haɗawar Intel don Intel Xeon CPU tare da fakitin FPGAs file (*.tar.gz), ya haɗa da DMA AFU example. Wannan example yana ba da direban sarari mai amfani. Aikace-aikacen mai watsa shiri yana amfani da wannan direba kamar yadda DMA ke motsa bayanai tsakanin mai watsa shiri da ƙwaƙwalwar FPGA. Ana samun binaries na kayan aikin, tushe, da direban sarari mai amfani a cikin jagorar mai zuwa: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu . Kafin gwaji tare da DMA AFU, dole ne ka shigar da kunshin software na Buɗe Programmable Acceleration Engine (OPAE). Koma zuwa Shigar da Kunshin Software na OPAE a cikin Intel Acceleration Stack Quick Start Guide for Intel FPGA Programmable Acceleration Card D5005 don umarnin shigarwa. Wannan Jagoran Farawa Mai Saurin kuma ya haɗa da ainihin bayanai game da Buɗewar Injin Haɓaka Matsala (OPAE) da daidaita AFU. Bayan shigar da kunshin software na Buɗe Programmable Acceleration Engine (OPAE), kamarample host aikace-aikace da kuma DMA AFU direban sarari mai amfani suna samuwa a cikin shugabanci mai zuwa: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw. Don gudanar da sampda aikace-aikacen runduna, fpga_dma_test akan kayan aikin Intel FPGA PAC D5005, koma zuwa matakan da ke cikin sashin Gudanar da DMA AFU Ex.ample. Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Bayanai masu alaƙa

Jagorar Farawa Mai Saurin Haɗawar Intel don Intel FPGA Mai Shirye-shiryen Haɗawa Katin D5005
Shigar da Kunshin Software na OPAE

Abubuwan Hardware na DMA AFU

DMA AFU tana mu'amala tare da FPGA Interface Unit (FIU) da ƙwaƙwalwar FPGA. Koma zuwa Fayil ɗin Bayanai na Manajan Interface na FPGA don Katin Haɗawa na Shirye-shiryen Intel FPGA D5005 don cikakkun bayanai na ƙwaƙwalwar FPGA. Kayan aikin da ake da su a halin yanzu yana sarrafa wannan tsarin ƙwaƙwalwar ajiya. Kayan aiki na gaba na iya goyan bayan saitunan ƙwaƙwalwar ajiya daban-daban. Kuna iya amfani da DMA AFU don kwafin bayanai tsakanin tushen masu zuwa da wuraren da aka nufa:

Mai watsa shiri zuwa na'urar FPGA ƙwaƙwalwar ajiya
Ƙwaƙwalwar FPGA na na'ura zuwa mai watsa shiri

Tsarin Tsarin Tsarin Platform, $ OPAE_PLATFORM_ROOT/hw/samples/ dma_afu/hw/rtl/TEST_dma/ /dma_test_system.qsys yana aiwatar da yawancin DMA

AFU. Wani ɓangare na DMA AFU da aka aiwatar a cikin tsarin Platform Designer za a iya samuwa a cikin masu zuwa

wuri: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/ Kuna iya samun DMA BBB a wuri mai zuwa:

$ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/dma_bbb

Jagorar Mai Amfani na Aikin Sashen Aikin DMA: Intel FPGA Mai Shirye-shiryen Hanzarta Katin D5005

DMA AFU Hardware Block zane

DMA AFU ya haɗa da abubuwan ciki na ciki masu zuwa don yin mu'amala tare da FPGA Interface Unit (FIU):

Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwar IO (MMIO): gano MMIO karantawa da rubuta ma'amaloli kuma ya raba su da tashar CCI-P RX 0 da suka zo daga. Wannan yana tabbatar da cewa zirga-zirgar MMIO ba ta taɓa kaiwa MPF BBB ba kuma tashar umarni MMIO mai zaman kanta ce ke ba da sabis.
Ma'aikatar Kayayyakin Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa ta Ƙaddamarwa ta Ƙaddamarwa ta Ƙaddamarwa ta Ƙaddamarwa ta Ƙaddamarwa ta Ƙaddamar da Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa ) tana tabbatar da karanta martani daga dawowar DMA a cikin tsari da aka ba su. Ka'idar Avalon-MM tana buƙatar karanta martani don dawowa cikin tsari daidai.
CCI-P zuwa Adaftar Avalon-MM: Wannan tsarin yana fassara tsakanin ma'amalolin CCI-P da Avalon-MM, kamar haka:
CCI-P zuwa Adaftar Avalon-MMIO: Wannan hanyar tana fassara ma'amalar CCI-P MMIO zuwa ma'amalar Avalon-MM.
Avalon zuwa Adafta Mai watsa shiri na CCI-P: Waɗannan hanyoyin suna ƙirƙirar keɓantattun hanyoyin karantawa-kawai da rubuta-kawai don DMA don samun damar ƙwaƙwalwar ajiya.
Tsarin Gwajin DMA: Wannan tsarin yana aiki azaman abin rufewa a kusa da DMA BBB don fallasa masters na DMA ga sauran dabaru a cikin AFU. Yana ba da haɗin kai tsakanin DMA BBB da CCI-P zuwa Adaftar Avalon. Hakanan yana ba da haɗin kai tsakanin DMA BBB da bankunan FPGA SDRAM na gida.

Bayanai masu alaƙa
Takardar bayanan Manajan Interface na FPGA don Intel FPGA Mai Shirye-shiryen Hanzarta Katin D5005

Tsarin Gwajin DMA

Tsarin gwajin DMA yana haɗa DMA BBB zuwa sauran ƙirar FPGA ciki har da daidaitawar CCI-P da ƙwaƙwalwar FPGA na gida.

Tsarin Tsarin Gwajin DMA
Wannan zanen toshe yana nuna abubuwan cikin tsarin gwajin DMA. Ana nuna tsarin gwajin DMA azaman toshe ɗaya a cikin hoto 1 a shafi na 7.

Tsarin gwajin DMA ya ƙunshi nau'ikan abubuwan ciki masu zuwa:

Gadar Far Reach/Pipeline Bridge: Gadar bututu tare da daidaitacce latency an haɗa don sarrafa topology da haɓaka ƙirar Fmax.

DMA AFU Na'urar Babban Jigo (DFH): Wannan DFH ne na DMA AFU. Wannan DFH yana nuna DFH na gaba wanda yake a kashe 0x100 (DMA BBB DFH).
Rashin DFH: Wannan bangaren yana ƙare jerin haɗin haɗin DFH. Idan kun ƙara ƙarin DMA BBBs zuwa ƙira, tabbatar da cewa adireshin tushe na DFH mara kyau yana nan a ƙarshen jerin haɗin DFH.
MA Basic Building Block (BBB): Wannan toshe yana motsa bayanai tsakanin mai watsa shiri da ƙwaƙwalwar FPGA na gida. Hakanan yana samun dama ga ƙwaƙwalwar ajiya don samun damar sarƙoƙin sifantawa.

DMA BBB

Tsarin DMA BBB yana canja wurin bayanai daga tushe zuwa adiresoshin da aka nufa ta amfani da mu'amalar Avalon-MM. Direban DMA yana sarrafa DMA BBB ta hanyar samun damar sarrafawa da rajistar matsayi na sassa daban-daban na cikin tsarin. Direban DMA kuma yana sarrafa DMA BBB ta amfani da ƙwaƙwalwar ajiyar ajiya don sadarwa masu bayanin canja wuri. DMA BBB yana samun damar bayanai a cikin ƙwaƙwalwar FPGA a kashe 0x0. DMA BBB na samun dama ga bayanai da masu siffantawa a cikin ƙwaƙwalwar ajiyar gida a kashe 0x1_0000_0000_0000.

DMA BBB Platform Designer Block zane
Wannan zanen toshe ya keɓance wasu na'urorin bututun gadar IP na ciki.

Jagorar Mai Amfani na Aikin Sashen Aikin DMA: Intel FPGA Mai Shirye-shiryen Hanzarta Katin D5005

Bayanin DMA AFU

Abubuwan da ke cikin DMA BBB Platform Designer suna aiwatar da ayyuka masu zuwa:

Gadar Far Reach/Pipeline Bridge: Gadar bututu mai daidaitacce wanda aka haɗa don sarrafa topology da haɓaka ƙirar Fmax.
MA BBB DFH: Wannan siffa ce ta na'ura don DMA BBB. Wannan DFH yana nuna DFH na gaba wanda yake a kashe 0x100 (Null DFH).
Bayanin Frontend: Mai alhakin ɗauko masu siffantawa da tura su zuwa Dispatcher. Lokacin da canja wurin DMA ya cika gaba yana karɓar samuwar matsayi daga Dispatcher kuma ya sake rubuta bayanin a cikin ƙwaƙwalwar ajiyar gida.

Mai aikawa: Wannan toshe yana tsara jadawalin canja wurin buƙatun DMA zuwa Jagoran Karatu da Rubutu.
Karanta Jagora: Wannan toshe yana da alhakin karanta bayanai daga ƙwaƙwalwar ajiyar FPGA na gida ko na gida da aika shi azaman bayanan yawo zuwa Rubuta Jagora.
Rubuta Jagora: Wannan toshe yana da alhakin karɓar bayanan yawo daga Jagoran Karatu da rubuta abubuwan da ke ciki don ɗaukar nauyin ƙwaƙwalwar FPGA ko na gida.

Yi Rajista taswira da Wuraren Adireshi

DMA AFU tana goyan bayan ƙwaƙwalwar ajiya guda biyu views: DMA view da mai gida view. Farashin DMA view yana goyan bayan sararin adireshi 49-bit. Ƙananan rabin DMA view taswirori zuwa ƙwaƙwalwar FPGA na gida. Babban rabin DMA view taswirori don ɗaukar nauyin ƙwaƙwalwar ajiya. Mai masaukin baki view ya haɗa da duk rajistar da ake samun dama ta hanyar shiga MMIO kamar tebur na DFH, da rajistar sarrafawa / matsayi na nau'ikan nau'ikan IP da aka yi amfani da su a cikin DMA AFU. MMIO tayi rijista a cikin DMA BBB da AFU suna goyan bayan samun damar 32- da 64-bit. DMA AFU baya goyan bayan isa ga MMIO 512-bit. Samun shiga rajistar Dispatcher a cikin DMA BBB dole ne ya zama rago 32 (Mai bayanin frontend yana aiwatar da rijistar 64-bit).

Taswirar Rijistar DMA AFU

Taswirar rijistar DMA AFU tana ba da cikakkun adireshi na duk wuraren da ke cikin rukunin. Waɗannan rijistar suna cikin rundunar view domin mai gida ne kawai zai iya shiga su.

Taswirar Ƙwaƙwalwar DMA AFU

Cire Adireshin Byte	Suna	Span a cikin Bytes	Bayani
0 x0	DMA AFU DFH	0 x40	Babban fasalin na'urar don DMA AFU. An saita ID_L zuwa 0x9081f88b8f655caa kuma an saita ID_H zuwa 0x331db30c988541ea. An daidaita DMA AFU DFH don nunawa don daidaitawa 0x100 don nemo DFH na gaba (DMA BBB DFH). Kada ku canza adireshin tushe na DMA AFU DFH tunda dole ne a kasance a adireshin 0x0 kamar yadda ƙayyadaddun CCIP suka ayyana.
0 x100	DMA BBB	0 x100	Yana ƙayyade ikon DMA BBB da haɗin rajistar matsayi. Kuna iya komawa zuwa taswirar rijistar DMA BBB don ƙarin bayani. A cikin DMA BBB a kashe 0 DMA BBB ya haɗa da nasa DFH. An saita wannan DFH don nemo DFH na gaba a 0x100 (NULL DFH). Idan kun ƙara ƙarin DMA BBBs, raba su 0x100 baya kuma tabbatar da NULL DFH yana bin DMA na ƙarshe ta 0x100.
0 x200	NULL DFH	0 x40	Yana ƙare jerin abubuwan haɗin DFH. An saita ID_L zuwa 0x90fe6aab12a0132f kuma an saita ID_H zuwa 0xda1182b1b3444e23. An tsara NULL DFH don zama DFH na ƙarshe a cikin kayan aiki. Don haka NULL DFH yana a adireshin 0x200. Idan kun ƙara ƙarin DMA BBBs zuwa tsarin, kuna buƙatar ƙara adireshin tushe na NULL DFH daidai yadda ya kasance a mafi girman adireshin. Direban DMA da aikace-aikacen gwaji ba sa amfani da wannan kayan aikin.

Yi Rajista taswira da Wuraren Adireshi

Taswirar Ƙwaƙwalwar DMA BBB
Adireshin byte masu zuwa ɓangarorin dangi ne daga adireshin tushe na DMA BBB a cikin tsarin DMA AFU (0x100).

Cire Adireshin Byte	Suna	Span a cikin Bytes	Bayani
0 x0	DMA BBB DFH	0 x40	Babban fasalin na'urar don DMA AFU. An saita ID_L zuwa 0xa9149a35bace01ea kuma an saita ID_H zuwa 0xef82def7f6ec40fc. DMA BBB DFH an daidaita shi don nunawa zuwa 0x100 don biya diyya na DFH na gaba. Wannan biya na gaba zai iya zama wani DMA BBB, wani DFH (ba a haɗa shi cikin wannan ƙira ba), ko NULL DFH.
0 x40	Mai aikawa	0 x40	Tashar tashar sarrafawa don mai aikawa. Direban DMA yana amfani da wannan wurin don sarrafa DMA ko tambayar matsayinta.
0 x80	Bayanin Frontend	0 x40	Gaban mai siffantawa wani yanki ne na al'ada wanda ke karanta masu siffantawa daga žwažwalwar ajiyar mai watsa shiri kuma ya sake rubuta bayanin lokacin da canja wurin DMA ya cika. Direban yana ba da umarni na gaba inda mai bayanin farko ke zaune a cikin ƙwaƙwalwar ajiyar gida sannan kuma kayan aikin gaba yana sadarwa tare da direba da farko kodayake bayanan da aka adana a cikin ƙwaƙwalwar ajiyar.

Space Adreshin DMA AFU

Mai watsa shiri na iya samun damar yin rajista da aka jera a cikin Tebura 4 a shafi na 12 da Tebura 5 a shafi na 13. Tsarin DMA BBB yana da damar zuwa cikakken sararin adireshi 49-bit. Ƙasashen rabin wannan fili na adireshin ya haɗa da tunanin FPGA na gida. Rabin babba na wannan sarari adreshin ya haɗa da ƙwaƙwalwar adreshin mai masaukin 48-bit. Hoto na gaba yana nuna mai watsa shiri da DMA views na memory.

DMA AFU da Mai watsa shiri Views na Memory

Lissafin Haɗe-haɗe-haɗe-haɗe-haɗe-haɗe-haɗen kai na na'ura

Tsarin DMA AFU example yana ƙunshe da na'ura mai mahimmanci guda uku (DFH) waɗanda ke samar da jerin abubuwan da aka haɗa. Wannan lissafin da aka haɗa yana ba da damar sampaikace-aikacen don gano DMA AFU da kuma direba don gano DMA BBB. Jerin DFH ya ƙunshi NULL DFH a ƙarshen. Haɗin DFH mara amfani a ƙarshen jerin abubuwan da aka haɗa yana ba ku damar ƙara ƙarin DMA BBBs zuwa ƙirar ku. Kuna buƙatar matsar da NULL DFH zuwa adireshin bayan sauran BBBs. Kowane DMA BBB yana tsammanin DFH na gaba zai kasance 0x100 bytes daga adireshin tushe na BBB. Hoto mai zuwa yana kwatanta jerin abubuwan da aka haɗa don ƙirar DMA AFU example.

Yi Rajista taswira da Wuraren Adireshi

DMA AFU Na'urar Siffar Header (DFH) Sarkar

Samfurin Shirye-shiryen Software

DMA AFU ya haɗa da direban software wanda zaku iya amfani da shi a cikin aikace-aikacen mai masaukinku. fpga_dma.cpp da fpga_dma.h files located a wuri mai zuwa aiwatar da direban software: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw Wannan direba yana goyan bayan ayyuka masu zuwa:

API	Bayani
fpgaCountDMAChannels	Yana bincika sarkar fasalin na'urar don DMA BBBs kuma yana ƙirga duk tashoshi da ke akwai.
fpgaDMABude	Yana buɗe hannu zuwa tashar DMA.
fpgaDMAC bace	Yana rufe hannu zuwa tashar DMA.
fpgaDMATransferInit	Fara wani abu da ke wakiltar canja wurin DMA.
fpgaDMATransferReset	Yana sake saita abun sifa na DMA zuwa tsoffin ƙima.
fpgaDMATransferRushewa	Yana lalata abin sifa canjin DMA.
fpgaDMATransferSetSrc	Yana saita adireshin tushen canja wuri. Dole ne wannan adireshi ya kasance yana daidaita 64 byte.
fpgaDMATransferSetDst	Yana saita adireshin wurin canja wuri. Dole ne wannan adireshi ya kasance yana daidaita 64 byte.
fpgaDMATransferSetLen	Yana saita tsayin canja wuri a cikin bytes. Don canja wurin fakiti ba, dole ne ka saita tsayin canja wuri zuwa mahara na 64 bytes. Don canja wurin fakiti, wannan ba buƙatu ba ne.
fpgaDMATransferSetTransferType	Yana saita nau'in canja wuri. Ƙimar shari'a sune: • HOST_MM_TO_FPGA_MM = TX (Mai watsa shiri zuwa AFU) • FPGA_MM_TO_HOST_MM = RX (AFU don karbar bakuncin)
fpgaDMATransferSetTransferCallback	Yayi rijistar sake kira don sanarwa akan kammala canja wuri asynchronous. Idan ka saka kiran dawowa, fpgaDMATransfer zai dawo nan da nan (canja wurin aiki tare). Idan baku saka kiran dawowa ba, fpgaDMATransfer zai dawo bayan an gama canja wurin (canja wurin aiki tare/ tarewa).
fpgaDMATransferSetLast	Yana nuna canja wuri na ƙarshe don DMA ta iya fara sarrafa canjin da aka riga aka yi. Matsakaicin ƙimar shine 64 canja wuri a cikin bututun kafin DMA ta fara aiki akan canja wuri.
fpgaDMATransfer	Yana yin canja wurin DMA.

Don ƙarin bayani game da API, shigarwa, da hujjar fitarwa, koma kan taken file akwai $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw/fpga_dma.hIntel Corporation. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Samfurin Shirye-shiryen Software

Don ƙarin sani game da samfurin amfani da direban software, koma zuwa README file wanda yake a $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/README.md

Gudun DMA AFU Example

Kafin ka fara:

Ya kamata ku saba da tsohonampLes a cikin Jagoran Farawa Mai Saurin Farawa na Intel Acceleration Stack don Intel FPGA Promable Acceleration Card D5005.
Dole ne ku ayyana canjin yanayi. Maɓallin mahalli ya dogara da sigar Intel Acceleration Stack da kuke amfani da shi:
- Don sigar yanzu, saita canjin yanayi zuwa $ OPAE_PLATFORM_ROOT
Dole ne ku shigar da ɗakin karatu na Intel Threading Building Blocks (TBB) tunda direban DMA ya dogara da shi.
Hakanan dole ne ku saita manyan shafuka 1 GB guda biyu don gudanar da sampda aikace-aikace. $ sudo sh -c "echo 2> /sys/kernel/mm/hugepages/hugepages-1048576kB/ nr_hugepages"

Yi matakai masu zuwa don zazzage bitstream DMA Accelerator Accelerator (AF), don gina aikace-aikacen da direba, da gudanar da ƙirar ƙira.ampda:

Canza zuwa aikace-aikacen DMA da kundin adireshin direba: cd $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw
Gina direba da aikace-aikacen: yi

Zazzage bitstream DMA AFU: sudo fpgasupdate ../bin/dma_afu_unsigned.gbs
Aiwatar da aikace-aikacen mai watsa shiri don rubuta 100 MB a cikin 1 MB daga ƙwaƙwalwar ajiya zuwa ƙwaƙwalwar na'urar FPGA kuma karanta shi baya: ./fpga_dma_test -s 104857600 -p 1048576 -r mtom

Bayanai masu alaƙa
Jagorar Farawa Mai Saurin Haɗawa ta Intel don Intel FPGA Mai Shirye-shiryen Hanzarta Katin D5005 Intel Corporation. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Haɗa DMA AFU Example

Don samar da yanayin ginin haɗin kai don haɗa AF, yi amfani da umarnin afu_synth_setup kamar haka:

Canza zuwa DMA AFU sampda directory: $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu
Ƙirƙirar tsarin ginin ƙira: afu_synth_setup –source hw/rtl/filelist.txt build_synth

Daga cikin kundin tsarin haɗin ginin da afu_synth_setup ya samar, shigar da umarni masu zuwa daga taga tasha don samar da AF don dandamalin kayan aikin da aka yi niyya: cd build_synth run.sh Rubutun tsararrun AF run.sh yana ƙirƙirar hoton AF tare da tushe iri ɗaya. filesuna a matsayin tsarin dandalin AFU file (.json) tare da kari na .gbs a wurin:$OPAE_PLATFORM_ROOT/hw/samples/build_synth/dma_afu_s10.gbs Intel Corporation. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Simulating da AFU Example

Intel yana ba da shawarar ku koma ga Sashin Accelerator Functional Unit (AFU) Simulation Environment (ASE) Jagoran Farawa Mai sauri don Intel FPGA PAC don ku saba da yin kwatancen tsohon.ampdon saita yanayin ku. Kafin ku ci gaba ta waɗannan matakai masu zuwa, tabbatar da cewa an saita canjin yanayi na OPAE_PLATFORM_ROOT zuwa tsarin shigarwa na OPAE SDK. Cika waɗannan matakai don saita na'urar kwaikwayo ta kayan aikin don DMA AFU:

Canza zuwa DMA AFU sampda directory: cd $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu

Ƙirƙiri yanayin ASE a cikin sabon kundin adireshi kuma saita shi don yin kwaikwayon AFU: afu_sim_setup -source hw/rtl/filelist.txt build_ase_dir
Canja zuwa kundin adireshin ginin ASE: cd build_ase_dir
Gina direba da aikace-aikacen: yi

Yi simulation: yin sim

Sampfitarwa daga na'urar kwaikwayo ta hardware:

[SIM] ** HANKALI : KAFIN gudanar da aikace-aikacen software ** [SIM] Saita env (ASE_WORKDIR) a cikin tashar inda aikace-aikacen zai gudana (copy-and-paste) => [SIM] $ SHELL | Gudu:[SIM] ———+————————————————— [SIM] bash/zsh | fitarwa ASE_WORKDIR=$ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/aiki [SIM] tcsh/csh | setenv ASE_WORKDIR $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/aiki [SIM] Don kowane $SHELL, tuntuɓi mai sarrafa Linux ɗin ku [SIM] [SIM] Shirye don simulation… [SIM] Danna CTRL-C don rufe na'urar kwaikwayo…

Cika waɗannan matakai don haɗawa da aiwatar da software na DMA AFU a cikin mahallin kwaikwayo:

Bude sabuwar taga tasha.
Canja shugabanci zuwa: cd $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw

Simulating da AFU Example

Kwafi kirtani saitin yanayi (zaɓi kirtani da ta dace da harsashi) daga matakan da ke sama a cikin simintin kayan masarufi zuwa taga tasha. Dubi layin masu zuwa a cikin sampfitarwa daga na'urar kwaikwayo ta hardware. [SIM] bash/zsh | fitarwa ASE_WORKDIR=$ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/aiki [SIM] tcsh/csh | setenv ASE_WORKDIR $ OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/aiki
Haɗa software: $ yi USE_ASE=1

Yi aikace-aikacen mai watsa shiri don rubuta 4 KB a cikin sassan 1 KB daga ƙwaƙwalwar ajiyar mai watsa shiri zuwa ƙwaƙwalwar na'urar FPGA a cikin yanayin madauki: ./ fpga_dma_test -s 4096 -p 1024 -r mtom

Bayanai masu alaƙa
Intel Accelerator Functional Unit (AFU) Simulations Environment (ASE) Jagoran Fara Mai Sauri

Haɓakawa don Inganta Ayyukan DMA

Aiwatar da ingantawa na NUMA (ba tare da yuwuwar ƙwaƙwalwar ajiya ba) ingantawa a cikin fpga_dma_test.cpp yana ba mai sarrafawa damar samun damar ƙwaƙwalwar ajiyar gida cikin sauri fiye da samun dama ga ƙwaƙwalwar da ba ta cikin gida ba (ƙwaƙwalwar ajiya na gida zuwa wani processor). Ana nuna daidaitaccen tsari na NUMA a cikin zanen da ke ƙasa. Samun shiga gida yana wakiltar samun dama daga ainihin tushe zuwa ƙwaƙwalwar ajiya na gida zuwa ainihin asali ɗaya. Samun nesa yana kwatanta hanyar da aka ɗauka lokacin da jijiya akan Node 0 ta sami dama ga ƙwaƙwalwar ajiyar da ke zaune a cikin ƙwaƙwalwar gida zuwa Node 1.

Kanfigareshan NUMA na al'ada

Yi amfani da lambar mai zuwa don aiwatar da haɓaka NUMA a cikin aikace-aikacen gwajin ku:

// Saita madaidaicin kusanci idan an buƙata idan (cpu_affinity || memory_affinity) {unsigned dom = 0, bas = 0, dev = 0, func = 0; fpga_properties props;int retval; #idan (FPGA_DMA_DEBUG) char str[4096]; #endifres = fpgaGetProperties(afc_token, & props); ON_ERR_GOTO(res, out_destroy_tok, "fpgaGetProperties"); res = fpgaPropertiesGetBus (props, (uint8_t *) & bas);ON_ERR_GOTO(res, out_destroy_tok, "fpgaPropertiesGetBus"); res = fpgaPropertiesGetDevice (props, (uint8_t *) & dev); ON_ERR_GOTO (res, out_destroy_tok, "fpgaPropertiesGetDevice") res = fpgaPropertiesGetFunction (props, (uint8_t *) & func);ON_ERR_GOTO (res, out_destroy_tok) // Nemo na'urar daga topology hwloc_topology_t topology; hwloc_topology_init(&topology); hwloc_topology_set_flags (topology, HWLOC_TOPOLOGY_FLAG_IO_DEVICES); Intel Corporation. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Haɓakawa don Inganta Ayyukan DMA

hwloc_topology_load(topology); hwloc_obj_t obj = hwloc_get_pcidev_by_busid (topology, dom, bas, dev, func); hwloc_obj_t obj2 = hwloc_get_non_io_ancestor_obj (topology, obj); #idan (FPGA_DMA_DEBUG) hwloc_obj_type_snprintf(str, 4096, obj2, 1); printf("%s\n", str);hwloc_obj_attr_snprintf(str, 4096, obj2, "::", 1);printf("%s\n", str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2-> cpuset); printf("CPUSET shine %s\n", str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2-> nodeset); printf ("NODESET shine %s \ n", str); # endif idan (memory_affinity) {#if HWLOC_API_VERSION> 0x00020000 retval = hwloc_set_membind(topology, obj2->nodeset,HWLOC_MEMBIND_THAD_TEMI) # sauran retval = hwloc_set_membind_nodeset (topology, obj2-> nodeset, HWLOC_MEMBIND_THREAD, HWLOC_MEMBIND_MIGRATE); #endifON_ERR_GOTO(retval, out_destroy_tok, "hwloc_set_membind"); } idan (cpu_affinity) {retval = hwloc_set_cpubind (topology, obj2-> cpuset, HWLOC_CPUBIND_STRICT); ON_ERR_GOTO(retval, out_destroy_tok, "hwloc_set_cpubind"); } }

Rukunin Rubutun Jagorar Mai Amfani na Ayyukan DMA

Intel Acceleration Stack Version	Jagorar Mai Amfani (PDF)
2.0	DMA Accelerator Aiki Unit (AFU) Jagorar mai amfani

Tarihin Bita na Daftarin aiki don Jagorar Mai Amfani da Sashen Ayyukan Aiki na DMA

Sigar Takardu

Intel Acceleration Sigar Tari

Canje-canje

2020.08.03

2.0.1 (ana goyan bayan Intel

Quartus® Prime Pro Edition 19.2)

An gyara hoton AF file suna a sashe Haɗa DMA AFU Example.

2020.04.17

2.0.1 (ana goyan bayan Intel

Buga na Quartus Prime Pro Edition 19.2)

Gyaran sanarwa a ciki Masu Sauraron Niyya sashe.

2020.02.20

2.0.1 (ana goyan bayan Intel

Buga na Quartus Prime Pro Edition 19.2)

Kafaffen typo.

2019.11.04

2.0.1 (ana goyan bayan Intel

Buga na Quartus Prime Pro Edition 19.2)

• Maye gurbin fpgaconf tare da fpgasupdate lokacin daidaita FPGA tare da prebuild AFU a cikin sashe. Gudun DMA AFU Example.

• Ƙara fassarar magana Katin Haɗawa na Intel FPGA D5005 zuwa taken daftarin aiki.

• Ƙara canjin yanayi $ OPAE_PLATFORM_ROOT.

Sashe da aka gyara Samfurin Shirye-shiryen Software don ƙananan gyare-gyare.

• Ƙara sabon sashe Haɗa DMA AFU Example.

Sashe da aka gyara Haɓakawa don Inganta Ayyukan DMA don ƙananan gyare-gyare.

2019.08.05

2.0 (ana goyan bayan Intel

Quartus Prime Pro Edition 18.1.2)

Sakin farko.

Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Takardu / Albarkatu

Katin Haɗawa na Intel FPGA D5005 [pdf] Jagorar mai amfani
Katin Haɗawa Mai Shirye-shiryen FPGA, D5005, Katin Haɗawa Mai Shirye-shiryen FPGA D5005, Sashen Accelerator Accelerator DMA

Magana

Manual mai amfani

Katin Haɗawa na Intel FPGA D5005

Game da wannan Takardun

Bayanin DMA AFU

Yi Rajista taswira da Wuraren Adireshi

Taswirar Rijistar DMA AFU

Yi Rajista taswira da Wuraren Adireshi

Samfurin Shirye-shiryen Software

Gudun DMA AFU Example

Haɗa DMA AFU Example

Simulating da AFU Example

Haɓakawa don Inganta Ayyukan DMA

Rukunin Rubutun Jagorar Mai Amfani na Ayyukan DMA

Tarihin Bita na Daftarin aiki don Jagorar Mai Amfani da Sashen Ayyukan Aiki na DMA

Takardu / Albarkatu

Magana

Bar sharhi

Soke amsa