Intel FPGA Programmable Acceleration Card D5005 User Guide

O lenei pepa o loʻo faʻamatalaina ai le faʻaogaina tuusaʻo (DMA) Accelerator Functional Unit (AFU) faʻatinoga ma le auala e fausia ai le mamanu e faʻaoga i luga o meafaigaluega poʻo le faʻataʻitaʻiga.

Tagata Fa'amoemoe

O le au fa'amoemoe e aofia ai masini po'o polokalama fa'apipi'i e mana'omia le Accelerator Function (AF) e fa'apolopolo fa'amaumauga i le lotoifale i manatua e feso'ota'i ma le masini Intel FPGA.

Fonotaga

Feagaiga Fa'amaumauga

Fonotaga	Fa'amatalaga
#	E muamua i se poloaiga e ta'u mai ai le poloaiga e tatau ona tu'u i totonu o le a'a.
$	Fa'ailoa mai o se fa'atonuga e tatau ona tu'uina o se fa'aoga.
Ole vai vai lea	Fileigoa, poloaiga, ma upu autu o loo lolomi i totonu o lenei vai papatisoga. O laina fa'atonuga uumi o lo'o lolomi i totonu o lenei vai papatisoga. E ui lava e mafai ona afifi laina laina uumi i le isi laina, o le toe foi mai e le o se vaega o le poloaiga; aua le fetaomi i totonu.
	Fa'ailoa mai ai le fa'ailoga o lo'o fa'aalia i le va o puipui fa'amau e tatau ona sui i se tau talafeagai. Aua le ulufale i puipui tulimanu.

Acronyms

Acronyms	Fa'alautele	Fa'amatalaga
AF	Galuega Fa'avave	Fa'apipi'i Fa'atonu Fa'atonu ata fa'atino i le FPGA logic e fa'atelevave ai se talosaga.
AFU	Vaega Fa'atino a le Accelerator	Meafaigaluega Accelerator faʻatinoina i le FPGA logic lea e faʻamutaina ai se faʻaogaina faʻaogaina mo se talosaga mai le PPU e faʻaleleia ai le faʻatinoga.
API	Fa'aoga Polokalama Fa'aoga	Se seti o fa'auigaga fa'apitoa, fa'asologa, ma mea faigaluega mo le fausiaina o polokalama faakomepiuta.
CCI-P	Autu Cache Interface	CCI-P o le faʻaoga masani a AFU e faʻaoga e fesoʻotaʻi ma le talimalo.
DFH	Ulutala o Mea Fa'atonu	Fausia se lisi feso'ota'i o ulutala fa'apitoa e maua ai se auala fa'alautele e fa'aopoopo ai foliga.
*faaauau…*

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Acronyms	Fa'alautele	Fa'amatalaga
FIM	FPGA Interface Manager	O meafaigaluega FPGA o loʻo i ai le FPGA Interface Unit (FIU) ma fesoʻotaʻiga fafo mo le manatua, networking, ma isi. O le Accelerator Function (AF) e feso'ota'i ma le FIM i le taimi e ta'avale ai.
FIU	FPGA Interface Unit	O le FIU o se faʻapipiʻi faʻapipiʻi faʻavae e fai ma alalaupapa i le va o fesoʻotaʻiga faʻavae e pei o PCIe *, UPI ma AFU-itu faʻafesoʻotaʻi e pei ole CCI-P.
MPF	Meatotino Manatu Falegaosimea	O le MPF o se Poloka Faufale Autu (BBB) e mafai ona fa'aogaina e AFU e tu'uina atu ai galuega fa'apena fe'avea'i CCI-P mo fefa'atauaiga ma le FIU.

Acceleration Glossary

Acceleration Stack mo Intel® Xeon® CPU ma FPGAs Glossary

Vaitaimi	Faapuupuuga	Fa'amatalaga
Intel® Acceleration Stack mo Intel Xeon® PPU ma FPGA	Fa'aputuga Fa'avave	O se fa'aputuga o polokalame, firmware, ma mea faigaluega e maua ai le fa'atinoina o le feso'ota'iga i le va o le Intel FPGA ma le Intel Xeon processor.
Intel FPGA Programmable Acceleration Card	Intel FPGA PAC	PCIe FPGA kata fa'avavevave. O lo'o iai le FPGA Interface Manager (FIM) e fa'atasi ma le Intel Xeon processor i luga ole pasi PCIe.

DMA Accelerator Unit Fa'atino Taiala mo Tagata: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Fa'amatalaga

Folasaga

Le Avanoa Fa'asa'o Fa'amanatu (DMA) AFU exampLe faʻaalia pe faʻafefea ona pulea le faʻafeiloaʻiga o mafaufauga i le va o le talimalo processor ma le FPGA. E mafai ona e tu'ufa'atasia le DMA AFU i lau mamanu e fa'anofo ai fa'amaumauga i le va o le fa'amanatuga o le talimalo ma le FPGA fa'alotoifale memory. O le DMA AFU e aofia ai submodules nei:

Falegaosimea Meatotino (MPF) Poloka Faufale Autu (BBB)

Fa'asinomaga Autu Cache (CCI-P) i le Avalon® Memory-Mapped (Avalon-MM) Adapter
DMA Test System lea e iai le DMA BBB

O nei submodules o loʻo faʻamatalaina atili auiliili ile DMA AFU Hardware Components autu o loʻo i lalo.

Fa'amatalaga Fa'atatau

Le DMA AFU Hardware Components i le itulau 6
Avalon Interface Specifications

Mo nisi faʻamatalaga e uiga i le Avalon-MM protocol, e aofia ai ata o taimi mo fefaʻatauaiga faitau ma tusitusi.

O le DMA AFU Software Package

Le Intel Acceleration Stack mo le Intel Xeon CPU fa'atasi ai ma FPGAs afifi file (*.tar.gz), e aofia ai le DMA AFU example. O lenei example tu'uina atu se aveta'avale avanoa fa'aoga. O lo'o fa'aogaina e le 'au'aunaga lenei aveta'avale ina ia fa'agasolo e le DMA fa'amaumauga i le va o le talimalo ma le FPGA manatua. O lo'o maua le fa'asologa o meafaigaluega, puna'oa, ma le aveta'avale avanoa i le lisi o lo'o i lalo: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu . A'o le'i fa'ata'ita'i i le DMA AFU, e tatau ona e fa'apipi'i le polokalame Open Programmable Acceleration Engine (OPAE). Va'ai i le Fa'apipi'iina o le OPAE Software Package i le Intel Acceleration Stack Quick Start Guide mo le Intel FPGA Programmable Acceleration Card D5005 mo faatonuga fa'apipi'i. O lenei Ta'iala Amata Fa'avave e aofia ai fo'i fa'amatalaga autu e uiga i le Open Programmable Acceleration Engine (OPAE) ma le fa'atulagaina o se AFU. A maeʻa ona faʻapipiʻi le polokalame Open Programmable Acceleration Engine (OPAE), pei oampO lo'o maua le talosaga a le talimalo ma le aveta'avale avanoa mo tagata fa'aoga DMA AFU i le lisi o lo'o i lalo: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw. E tamo'e le sample talosaga talimalo, fpga_dma_test i lau Intel FPGA PAC D5005 meafaigaluega, fa'asino i laasaga i le vaega Fa'agaoioi le DMA AFU Example. Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Fa'amatalaga Fa'atatau

Intel Acceleration Stack Quick Start Guide mo le Intel FPGA Programmable Acceleration Card D5005
Fa'apipi'i le OPAE Software Package

Le DMA AFU Mea Fa'apipi'i

O le DMA AFU e feso'ota'i ma le FPGA Interface Unit (FIU) ma le FPGA memory. Va'ai i le FPGA Interface Manager Data Pepa mo le Intel FPGA Programmable Acceleration Card D5005 mo fa'amatalaga auiliili o le FPGA memory. O meafaigaluega o lo'o avanoa nei e fa'atonuina le fa'atulagaina o manatuaga. E mafai e meafaigaluega i le lumana'i ona lagolagoina fa'atonuga manatua eseese. E mafai ona e fa'aogaina le DMA AFU e kopi ai fa'amaumauga i le va o fa'apogai ma nofoaga o lo'o i lalo:

Le talimalo ile masini FPGA manatua
Meafaigaluega FPGA manatua i le talimalo

O se faiga fa'avae, $OPAE_PLATFORM_ROOT/hw/samples/ dma_afu/hw/rtl/TEST_dma/ /dma_test_system.qsys fa'atinoina le tele o le DMA

AFU. O se vaega o le DMA AFU o loʻo faʻatinoina i le Platform Designer system e mafai ona maua i mea nei

nofoaga:$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/TEST_dma/ E mafai ona e mauaina le DMA BBB i le nofoaga nei:

$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/hw/rtl/dma_bbb

DMA Accelerator Unit Fa'atino Taiala mo Tagata: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Hardware Block Ata

O le DMA AFU o loʻo aofia ai faʻaoga i totonu e faʻafesoʻotaʻi ma le FPGA Interface Unit (FIU):

Memory-Mapped IO (MMIO) Decoder Logic: iloa MMIO faitau ma tusi fefaʻatauaiga ma vavae ese mai le CCI-P RX alalaupapa 0 latou te taunuu mai. O le mea lea e mautinoa ai e le o'o atu le MMIO i le MPF BBB ma o lo'o tautuaina e le MMIO fa'atonuga tuto'atasi.
Meatotino Meatotino (MPF): O lenei module e faʻamautinoa e faitau tali mai le DMA e toe foʻi i le faʻatonuga na tuʻuina atu. O le Avalon-MM protocol e manaʻomia le faitau tali e toe foʻi i le faasologa saʻo.
CCI-P i Avalon-MM Adapter: O lenei module e fa'aliliu i le va o fefa'atauaiga CCI-P ma Avalon-MM, e fa'apea:
CCI-P i Avalon-MMIO Adapter: O lenei ala e faʻaliliuina CCI-P MMIO fefaʻatauaiga i Avalon-MM fefaʻatauaiga.
Avalon i le CCI-P Host Adapter: O nei auala e fausia ai ni auala eseese na'o le faitau ma le tusitusi mo le DMA e maua ai le manatua o le talimalo.
Faiga Su'ega DMA: O lenei module e avea o se afifi faataamilo i le DMA BBB e faʻaalia ai matai DMA i le vaega o totoe o le manatu i le AFU. E maua ai le feso'ota'iga i le va o le DMA BBB ma le CCI-P i Avalon Adapter. E maua ai fo'i le feso'ota'iga i le va o le DMA BBB ma faletupe FPGA SDRAM i le lotoifale.

Fa'amatalaga Fa'atatau
FPGA Interface Manager Pepa Fa'amaumauga mo le Intel FPGA Programmable Acceleration Card D5005

Faiga Su'ega DMA

Ole faiga ole su'ega DMA e fa'afeso'ota'i le DMA BBB i le vaega o totoe o le FPGA mamanu e aofia ai le CCI-P fa'afetaui ma le FPGA i le lotoifale.

DMA Su'ega System Block Ata
O lenei poloka poloka o loʻo faʻaalia ai totonu ole faiga ole suʻega DMA. Ole faiga ole su'ega DMA o lo'o fa'aalia ole poloka monolithic ile Ata 1 ile itulau 7.

Ole faiga ole su'ega DMA e aofia ai vaega nei ile totonu:

Alalaupapa A'o Mamao/Pipeline Bridge: O se alalaupapa paipa ma fetuutuuna'i latency aofia ai e pulea topology ma faaleleia le mamanu Fmax.

DMA AFU Device Feature Header (DFH): Ole DFH lea mo le DMA AFU. Ole DFH lea e fa'asino ile isi DFH o lo'o iai ile offset 0x100 (DMA BBB DFH).
Null DFH: O lenei vaega e fa'amutaina le DFH feso'ota'iga-lisi. Afai e te fa'aopoopoina nisi DMA BBB i le mamanu, fa'amautinoa o lo'o iai le tuatusi fa'avae ole DFH ile pito ole lisi o feso'ota'iga DFH.
MA Basic Building Block (BBB): O lenei poloka e faʻanofo ai faʻamaumauga i le va o le talimalo ma le FPGA i le lotoifale. E maua ai fo'i le manatua o le talimalo e maua ai filifili fa'amatalaga.

DMA BBB

O le DMA BBB subsystem e fa'aliliuina fa'amatalaga mai fa'apogai i tuatusi fa'asinomaga e fa'aaoga ai fefa'atauaiga Avalon-MM. E pulea e le aveta'avale DMA le DMA BBB e ala i le mauaina o le fa'atonuga ma le resitalaina o tulaga o vaega eseese i totonu o le polokalama. E pulea foi e le aveta'avale DMA le DMA BBB e ala i le fa'aogaina o mafaufauga fa'asoa e feso'ota'i ai fa'amatalaga fa'aliliu. E maua e le DMA BBB fa'amaumauga ile FPGA manatua ile offset 0x0. E maua e le DMA BBB fa'amaumauga ma fa'amatalaga i le fa'amanatuina o le talimalo ile offset 0x1_0000_0000_0000.

DMA BBB Platform Designer Block Diagram
O lenei poloka poloka e le aofia ai nisi totonu ole Pipeline Bridge IP cores.

DMA Accelerator Unit Fa'atino Taiala mo Tagata: Intel FPGA Programmable Acceleration Card D5005

DMA AFU Fa'amatalaga

O vaega i le DMA BBB Platform Designer o loʻo faʻatinoina galuega nei:

Alalaupapa A'o Mamao/Vaula Paipa: O se alalaupapa paipa fa'atasi ai ma fetuutuuna'i latency aofia ai e pulea topology ma faaleleia le mamanu Fmax.
MA BBB DFH: Ole fa'aulutala lea ole masini mo le DMA BBB. Ole DFH lea e fa'asino ile isi DFH o lo'o iai ile offset 0x100 (Null DFH).
Fa'amatalaga pito i luma: E nafa ma le aumaia o faʻamatalaga ma tuʻuina atu i le Dispatcher. A mae'a le fesiitaiga o le DMA e maua e le pito i luma le fa'atulagaina o tulaga mai le Dispatcher ma toe fa'asolo le fa'amatalaga i le manatua o le talimalo.

avefe'au: O le poloka lea o lo'o fa'atulagaina le DMA e tu'uina atu talosaga i le Faitau ma Tusi le Matai.
Faitau le Matai: O lenei poloka e nafa ma le faitauina o faʻamatalaga mai le talimalo poʻo le faʻalotoifale FPGA manatua ma tuʻuina atu e pei o faʻasalalauga faʻamaumauga i le Tusia Master.
Tusi le Matai: O lenei poloka e nafa ma le mauaina o faʻamatalaga tafe mai le Read Master ma le tusiaina o mea e faʻafeiloaʻi poʻo le FPGA i le lotoifale.

Resitala Faafanua ma Avanoa tuatusi

E lagolagoina e le DMA AFU manatuaga e lua views: Le DMA view ma le talimalo view. Le DMA view lagolagoina se avanoa tuatusi 49-bit. Ole afa pito i lalo ole DMA view fa'afanua i le manatua FPGA i le lotoifale. Ole afa pito i luga ole DMA view fa'afanua e fa'afeiloa'i ai manatuaga. Le talimalo view e aofia ai resitara uma e mafai ona maua e ala i MMIO avanoa e pei o laulau DFH, ma le fa'atonuga/tulaga resitara o 'autu IP eseese o lo'o fa'aogaina i totonu ole DMA AFU. O le MMIO resitala i le DMA BBB ma le AFU e lagolagoina le 32- ma le 64-bit avanoa. E le lagolagoina e le DMA AFU le 512-bit MMIO avanoa. O avanoa i le Resitala a le Dispatcher i totonu o le DMA BBB e tatau ona 32 bits (Descriptor frontend e faʻaaogaina tusi resitala 64-bit).

DMA AFU Resitala Faafanua

O le fa'afanua o le resitala a le DMA AFU o lo'o tu'uina atu ai tuatusi atoatoa o nofoaga uma i totonu o le iunite. O nei resitala o loʻo i totonu o le talimalo view auā e na'o le 'au e mafai ona maua.

DMA AFU Fa'afanua Fa'amanatu

Fa'aituuga o le tuatusi Byte	Igoa	Span i Bytes	Fa'amatalaga
0x0	DMA AFU DFH	0x40	Ulutala fa'apitoa mo le DMA AFU. Ole ID_L ua seti ile 0x9081f88b8f655caa ma ID_H ua seti ile 0x331db30c988541ea. O le DMA AFU DFH ua fa'avasegaina e fa'asino e fa'asolo le 0x100 e su'e ai le isi DFH (DMA BBB DFH). E le tatau ona e suia le tuatusi autu o le DMA AFU DFH talu ai e tatau ona i ai i le tuatusi 0x0 e pei ona faʻamalamalamaina e le CCIP faʻamatalaga.
0x100	DMA BBB	0x100	Fa'ama'oti le DMA BBB fa'atonutonu ma le fa'auluuluga o le resitara tulaga. E mafai ona e va'ai ile fa'afanua DMA BBB resitala mo nisi fa'amatalaga. I totonu ole DMA BBB ile offset 0 ole DMA BBB e aofia ai lana lava DFH. O lenei DFH ua fa'atulaga e su'e le isi DFH ile offset 0x100 (NULL DFH). Afai e te fa'aopoopoina nisi DMA BBBs, fa'avatu 0x100 va ma fa'amautinoa ole NULL DFH e mulimuli ile DMA mulimuli ile 0x100.
0x200	Null DFH	0x40	Fa'amuta le lisi feso'ota'i DFH. Ua seti le ID_L ile 0x90fe6aab12a0132f ma le ID_H ua seti ile 0xda1182b1b3444e23. O le NULL DFH ua fa'avasegaina e avea ma DFH mulimuli i meafaigaluega. Mo lenei mafuaʻaga o le NULL DFH o loʻo i le tuatusi 0x200. Afai e te faʻaopoopoina DMA BBBs faaopoopo i le faiga, e tatau ona e faʻateleina le tuatusi faʻavae NULL DFH e tusa ai ina ia tumau i le tuatusi maualuga. E le fa'aogaina e le aveta'avale DMA ma le su'ega lenei meafaigaluega.

Resitala Faafanua ma Avanoa tuatusi

DMA BBB Fa'afanua Fa'amanatu
O tuatusi byte o lo'o mulimuli mai o fa'apena fa'atatau mai le tuatusi fa'avae DMA BBB i le DMA AFU system (0x100).

Fa'aituuga o le tuatusi Byte	Igoa	Span i Bytes	Fa'amatalaga
0x0	DMA BBB DFH	0x40	Ulutala fa'apitoa mo le DMA AFU. Ua seti le ID_L ile 0xa9149a35bace01ea ma le ID_H ua seti ile 0xef82def7f6ec40fc . O le DMA BBB DFH ua fa'avasegaina e fa'asino i le 0x100 mo le isi DFH offset. O le isi offset e mafai ona avea ma se isi DMA BBB, isi DFH (e le o aofia ai i lenei mamanu), poʻo le NULL DFH.
0x40	Avefe'au	0x40	Taupulega mo le avefe'au. E fa'aoga e le aveta'avale DMA lea nofoaga e pulea ai le DMA pe fesiligia lona tulaga.
0x80	Fa'amatalaga pito i luma	0x40	O le fa'amatalaga pito i luma o se vaega fa'ale-aganu'u e faitau fa'amatalaga mai le manatua o le talimalo ma fa'asolo le fa'amatalaga pe a mae'a le fa'aliliuga DMA. E fa'atonu e le aveta'avale le pito i luma o lo'o nofo ai le fa'amatalaga muamua i le fa'amanatuga o le talimalo ona feso'ota'i ai lea o meafaigaluega pito i luma ma le aveta'avale e ui lava o fa'amatalaga o lo'o teuina i le mafaufau talimalo.

DMA AFU Address Space

E mafai e le tagata talimalo ona maua tusi resitala o loʻo lisiina i le Laulau 4 i le itulau 12 ma le Laulau 5 i le itulau 13. O le DMA BBB subsystem e mafai ona maua le avanoa atoa o le tuatusi 49-bit. O le afa pito i lalo o lenei avanoa tuatusi e aofia ai manatuaga FPGA i le lotoifale. O le afa pito i luga o lenei avanoa tuatusi e aofia ai le 48-bit host address memory. O le ata o loʻo i lalo o loʻo faʻaalia ai le talimalo ma le DMA views o manatuaga.

O le DMA AFU ma le Host Views o Manatu

Ulutala Feso'ota'i Meafaitino-Lisi

Le DMA AFU mamanu exampO lo'o iai fa'aulutala fa'apitoa e tolu (DFH) o lo'o fausia ai se lisi feso'ota'i. Ole lisi feso'ota'i lea e fa'atagaina ai le sample talosaga e iloa ai le DMA AFU faapea foi ma le avetaavale e iloa ai le DMA BBB. O le lisi o le DFH e aofia ai se DFH NULL ile pito. O le fa'aofiina o le null DFH i le pito o le lisi feso'ota'i e mafai ai ona e fa'aopoopo atili DMA BBB i lau mamanu. Na'o lou mana'omia e si'i le NULL DFH i se tuatusi pe a uma isi BBB. O DMA BBB ta'itasi e fa'amoemoe le isi DFH e tu'u 0x100 paita mai le tuatusi fa'avae ole BBB. O le ata o lo'o i lalo o lo'o fa'aalia ai le feso'ota'iga-lisi mo le DMA AFU fa'ata'ita'igaample.

Resitala Faafanua ma Avanoa tuatusi

DMA AFU Device Feature Header (DFH) Chaining

Fa'ata'ita'iga Polokalame Polokalama

O le DMA AFU e aofia ai se aveta'avale faakomepiuta e mafai ona e fa'aogaina i lau lava talosaga fa'afeiloa'i. O le fpga_dma.cpp ma le fpga_dma.h files o lo'o i le nofoaga lea e fa'atino ai le aveta'avale polokalama:$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw E lagolagoina e lenei avetaavale galuega nei:

API	Fa'amatalaga
fpgaCountDMACchannels	Su'e le filifili o le masini mo DMA BBBs ma faitau uma auala avanoa.
fpgaDMATatala	Tatala se au i le ala DMA.
fpgaDMAClose	Tapuni se au i le ala DMA.
fpgaDMATransferInit	Fa'amataina se mea e fa'atusalia le fesiitaiga DMA.
fpgaDMATransferReset	Toe setiina le DMA fesiitaiga o mea e uiga i tau fa'aletonu.
fpgaDMATransferDestroy	Fa'aleaga le DMA fa'aliliuga mea faitino.
fpgaDMATransferSetSrc	Seti le tuatusi puna o le fesiitaiga. O lenei tuatusi e tatau ona 64 paita fa'aoga.
fpgaDMATransferSetDst	Seti le tuatusi o le fesiitaiga. O lenei tuatusi e tatau ona 64 paita fa'aoga.
fpgaDMATransferSetLen	Seti le umi fesiitaiga ile paita. Mo fesiitaiga e le o ni taga, e tatau ona e setiina le umi ole fesiitaiga ile tele ole 64 paita. Mo le fesiitaiga o pepa, e le o se mea e manaʻomia.
fpgaDMATransferSetTransferType	Seti le ituaiga fesiitaiga. O tulaga fa'aletulafono o: • HOST_MM_TO_FPGA_MM = TX (Host to AFU) • FPGA_MM_TO_HOST_MM = RX (AFU e talimalo)
fpgaDMATransferSetTransferCallback	Lesitala le toe fo'i mo fa'amatalaga i le mae'a fesiita'iga asynchronous. Afai e te faʻamaonia se toe foʻi mai, e toe foʻi vave mai le fpgaDMATransfer (asynchronous transfer). Afai e te le faʻamaonia se toe foʻi mai, e toe foʻi mai le fpgaDMATransfer pe a maeʻa le fesiitaiga (synchronous/blocking transfer).
fpgaDMATransferSetLast	Fa'ailoa le fesiitaiga mulimuli ina ia mafai ai e le DMA ona amata fa'agaoioi le fesiitaiga muamua. Ole tau fa'aletonu ole 64 fa'aliliuina ile paipa a'o le'i amata galue le DMA ile fesiitaiga.
fpgaDMATransfer	Faia se fesiitaiga DMA.

Mo nisi fa'amatalaga e uiga i le API, fa'aoga, ma fa'amatalaga fa'atino, va'ai i le ulutala file maua $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw/fpga_dma.hIntel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'atau a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Fa'ata'ita'iga Polokalame Polokalama

Mo nisi fa'amatalaga e uiga i le fa'aogaina o le aveta'avale polokalama fa'ata'ita'iga, fa'asino ile README file o lo'o maua ile $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/README.md

Tamomoe DMA AFU Example

Ae e te le'i amataina:

E tatau ona e masani i le examples i le Intel Acceleration Stack Quick Start Guide mo le Intel FPGA Programmable Acceleration Card D5005.
E tatau ona e fa'amalamalamaina se fesuiaiga o le siosiomaga. Ole suiga ole siosiomaga e fa'alagolago ile Intel Acceleration Stack version o lo'o e fa'aogaina:
- Mo le fa'asologa o lo'o iai nei, seti le fesuiaiga o le siosiomaga i le $OPAE_PLATFORM_ROOT
E tatau ona e fa'apipi'i le faletusi o le Intel Threading Building Blocks (TBB) talu ai e fa'alagolago i ai le aveta'avale DMA.
E tatau foi ona e setiina ni itulau tetele se lua 1 GB e faʻatautaia ai le sample talosaga. $ sudo sh -c "echo 2> /sys/kernel/mm/hugepages/hugepages-1048576kB/ nr_hugepages"

Faia laasaga nei e sii mai ai le DMA Accelerator Function (AF) bitstream, e fausia ai le talosaga ma le avetaʻavale, ma faʻatautaia le mamanu exampLe:

Suia i le DMA talosaga ma le aveta'avale: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw
Fausia le avetaavale ma le faʻaoga: fai

Sii mai le DMA AFU bitstream: sudo fpgasupdate ../bin/dma_afu_unsigned.gbs
Fa'atino le talosaga a le talimalo e tusi ai le 100 MB i le 1 MB vaega mai le fa'amanatuga i le FPGA masini manatua ma toe faitau i ai: ./ fpga_dma_test -s 104857600 -p 1048576 -r mtom

Fa'amatalaga Fa'atatau
Intel Acceleration Stack Quick Start Guide mo le Intel FPGA Programmable Acceleration Card D5005 Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Tuufaatasia o le DMA AFU Example

Mo le fa'atupuina o se si'osi'omaga fau fa'aopoopo e tu'ufa'atasia ai se AF, fa'aaoga le afu_synth_setup fa'atonu e pei ona taua i lalo:

Suiga ile DMA AFU sample lisi: $OPAE_PLATFORM_ROOT/hw/samples/dma_afu
Fausia le lisi o le fausiaina o mamanu: afu_synth_setup –source hw/rtl/filelist.txt build_synth

Mai le fa'asologa faufale fau fa'atupuina e afu_synth_setup, fa'aulu i lalo fa'atonuga mai le fa'amalama fa'amalama e fa'atupu ai se AF mo le fa'atūlaga meafaigaluega fa'amoemoe: cd build_synth run.sh O le run.sh AF generation script e fatuina ai le ata AF ma le fa'avae tutusa. fileigoa e pei o le faatulagaga faavae a le AFU file (.json) ma le .gbs suffix i le nofoaga:$OPAE_PLATFORM_ROOT/hw/samples/build_synth/dma_afu_s10.gbs Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Fa'ata'ita'i le AFU Example

Ua fautuaina e Intel e te va'ai ile Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start Guide mo lau Intel FPGA PAC e masani ai ile fa'ata'ita'iina o mea fa'apena.amples ma ia setiina lou siosiomaga. Ae e te le'i fa'agasolo i la'asaga o lo'o mulimuli mai, fa'amautinoa o lo'o tu'u le suiga ole si'osi'omaga OPAE_PLATFORM_ROOT ile lisi fa'apipi'i OPAE SDK. Fa'auma laasaga nei e fa'atulaga ai le masini simulator mo le DMA AFU:

Suiga ile DMA AFU sample lisi: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu

Fausia se siosiomaga ASE i se lisi fou ma faʻapipiʻi mo le faʻataʻitaʻiina o se AFU: afu_sim_setup –source hw/rtl/filelist.txt build_ase_dir
Suia i le ASE build directory: cd build_ase_dir
Fausia le avetaavale ma le faʻaoga: fai

Fai fa'atusa: fai sim

SampLe gaioiga mai le masini simulator:

[SIM] ** FAAMATALAGA : AO LEʻI faʻaogaina le polokalama faakomepiuta ** [SIM] Set env(ASE_WORKDIR) i totonu o le laina e faʻaoga ai le talosaga (kopi-ma-pasi) => [SIM] $SHELL | Tamomoe:[SIM] ———+————————————————— [SIM] bash/zsh | auina atu i fafo ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/ase_mkdir/work [SIM] Mo soʻo se isi $SHELL, faʻafesoʻotaʻi lau pule Linux [SIM] [SIM] Sauni mo faʻataʻitaʻiga… [SIM] Oomi le CTRL-C e tapuni ai le simulator...

Fa'auma laasaga nei e tu'ufa'atasia ma fa'atino le polokalama DMA AFU i le si'osi'omaga fa'ata'ita'i:

Tatala se faamalama fou.
Suia le lisi i le: cd $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/sw

Fa'ata'ita'i le AFU Example

Kopi le manoa seti o le siosiomaga (filifili le manoa e talafeagai mo lau atigi) mai laasaga o loʻo i luga i le faʻataʻitaʻiga meafaigaluega i le faʻamalama faʻamalama. Va'ai laina nei i le sample gaosiga mai le masini simulator. [SIM] bash/zsh | auina atu i fafo ASE_WORKDIR=$OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/work [SIM] tcsh/csh | setenv ASE_WORKDIR $OPAE_PLATFORM_ROOT/hw/samples/dma_afu/build_ase_dir/work
Fa'aopoopo le polokalame: $ fai USE_ASE=1

Fa'atino le talosaga a le talimalo e tusi ai le 4 KB i le 1 KB vaega mai le fa'amanatuina o le talimalo i tua i le FPGA masini manatua i le fa'aogaina o le loopback mode: ./ fpga_dma_test -s 4096 -p 1024 -r mtom

Fa'amatalaga Fa'atatau
Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) Quick Start User Guide

Fa'atonuga mo le Fa'aleleia o le Fa'atinoga o le DMA

O le fa'atinoina o le NUMA (non-uniform memory access) optimization i le fpga_dma_test.cpp e mafai ai e le processor ona fa'aoga vave lona lava manatua fa'apitonu'u nai lo le fa'aogaina o manatuaga fa'alenu'u (manatua i le lotoifale i le isi processor). Ole fa'asologa masani ole NUMA o lo'o fa'aalia ile ata i lalo. O le avanoa fa'apitonu'u o lo'o fa'atusalia ai le avanoa mai se fatu i le manatua fa'apitonu'u i le mea e tasi. O le avanoa mamao o loʻo faʻaalia ai le ala e uia pe a maua e le autu i luga o le Node 0 manatuaga o loʻo nofo i le mafaufau i le lotoifale ile Node 1.

Fa'asologa masani a le NUMA

Fa'aoga le code lea e fa'atino ai le NUMA optimization i lau su'ega talosaga:

// Seti se sootaga talafeagai pe a talosagaina pe afai (cpu_affinity || memory_affinity) {unsigned dom = 0, pasi = 0, dev = 0, func = 0; fpga_properties props;int retval; #afai(FPGA_DMA_DEBUG)char str[4096]; #endifres = fpgaGetProperties(afc_token, &props); ON_ERR_GOTO(res, out_destroy_tok, “fpgaGetProperties”); res = fpgaPropertiesGetBus(props, (uint8_t *) & pasi);ON_ERR_GOTO(res, out_destroy_tok, “fpgaPropertiesGetBus”); res = fpgaPropertiesGetDevice(props, (uint8_t *) & dev);ON_ERR_GOTO(res, out_destroy_tok, “fpgaPropertiesGetDevice”) res = fpgaPropertiesGetFunction(props, (uint8_t *) & func);ON_ERR_GOTO(ygaFunction), ON_ERR_GOTO(ygaFunction) ; // Su'e le masini mai le topology hwloc_topology_t topology; hwloc_topology_init(&topology); hwloc_topology_set_flags(topology, HWLOC_TOPOLOGY_FLAG_IO_DEVICES);Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Fa'atonuga mo le Fa'aleleia o le Fa'atinoga o le DMA

hwloc_topology_load(topology); hwloc_obj_t obj = hwloc_get_pcidev_by_busid(topology, dom, pasi, dev, func); hwloc_obj_t obj2 = hwloc_get_non_io_ancestor_obj(topology, obj); #afai (FPGA_DMA_DEBUG) hwloc_obj_type_snprintf(str, 4096, obj2, 1); printf(“%s\n”, str);hwloc_obj_attr_snprintf(str, 4096, obj2, ” :: “, 1);printf(“%s\n”, str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2->cpuset); printf(“CPUSET o le %s\n”, str); hwloc_bitmap_taskset_snprintf(str, 4096, obj2->nodeset); printf(“NODESET is %s\n”, str);#endif if (memory_affinity) { #if HWLOC_API_VERSION > 0x00020000 toe fa'afo'i = hwloc_set_membind(topology, obj2->nodeset,HWLOC_MEMBIND_THREMED_THREME, HWLOC_MEMBIND_THREME, HWLOC_MEMBIND_THREME, HWLOC_MEMBIND_THREME DESET); #else retval =hwloc_set_membind_nodeset(topology, obj2->nodeset, HWLOC_MEMBIND_THREAD,HWLOC_MEMBIND_MIGRATE); #endifON_ERR_GOTO(toe sui, out_destroy_tok, “hwloc_set_membind”); } pe afai (cpu_affinity) { retval = hwloc_set_cpubind(topology, obj2->cpuset, HWLOC_CPUBIND_STRICT); ON_ERR_GOTO(toe foi, out_destroy_tok, “hwloc_set_cpubind”); }}

DMA Accelerator Functional Unit Taiala Fa'amaumauga Fa'amaumauga

Intel Acceleration Stack Version	Fa'aoga Taiala (PDF)
2.0	DMA Accelerator Functional Unit (AFU) User Guide

Tala'aga Toe Iloiloga o Fa'amaumauga mo le Ta'iala mo Tagata Fa'aaogā Vaega Fa'atino a le DMA Accelerator

Fa'amatalaga Fa'amaumauga

Intel Acceleration Stack Version

Suiga

2020.08.03

2.0.1 (lagolagoina ma Intel

Quartus® Prime Pro Lomiga Lomiga 19.2)

Fa'asa'o le ata AF file igoa ile vaega Tuufaatasia o le DMA AFU Example.

2020.04.17

2.0.1 (lagolagoina ma Intel

Quartus Prime Pro Edition Lomiga 19.2)

Fa'asa'o se fa'amatalaga i Tagata Fa'amoemoe vaega.

2020.02.20

2.0.1 (lagolagoina ma Intel

Quartus Prime Pro Edition Lomiga 19.2)

Fa'atonu le fa'aoga.

2019.11.04

2.0.1 (lagolagoina ma Intel

Quartus Prime Pro Edition Lomiga 19.2)

• Suia le fpgaconf i le fpgasupdate pe a faʻapipiʻi le FPGA ma le AFU muamua fausia i le vaega Fa'aauau le DMA AFU Example.

• Fa'aopoopoina ulutala Intel FPGA Programmable Acceleration Card D5005 i le ulutala pepa.

• Fa'aopoopo le si'osi'omaga fesuiaiga $OPAE_PLATFORM_ROOT.

• Vaega ua suia Fa'ata'ita'iga Polokalame Polokalama mo teuteuga laiti.

• Faaopoopo vaega fou Tuufaatasia o le DMA AFU Example.

• Vaega ua suia Fa'atonuga mo le Fa'aleleia o le Fa'atinoga o le DMA mo teuteuga laiti.

2019.08.05

2.0 (lagolagoina ma Intel

Quartus Prime Pro Edition 18.1.2)

Fa'asalalauga muamua.

O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

Pepa / Punaoa

Intel FPGA Programmable Acceleration Card D5005 [pdf] Taiala mo Tagata Fa'aoga
FPGA Polokalama Fa'avave Fa'akomepiuta Card, D5005, FPGA Polokalama Fa'avave Fa'avave Card D5005, DMA Accelerator Fuafuaga Vaega

Fa'asinomaga

Tusi Taiala

Intel FPGA Programmable Acceleration Card D5005

E uiga i lenei Pepa

DMA AFU Fa'amatalaga

Resitala Faafanua ma Avanoa tuatusi

DMA AFU Resitala Faafanua

Resitala Faafanua ma Avanoa tuatusi

Fa'ata'ita'iga Polokalame Polokalama

Tamomoe DMA AFU Example

Tuufaatasia o le DMA AFU Example

Fa'ata'ita'i le AFU Example

Fa'atonuga mo le Fa'aleleia o le Fa'atinoga o le DMA

DMA Accelerator Functional Unit Taiala Fa'amaumauga Fa'amaumauga

Tala'aga Toe Iloiloga o Fa'amaumauga mo le Ta'iala mo Tagata Fa'aaogā Vaega Fa'atino a le DMA Accelerator

Pepa / Punaoa

Fa'asinomaga

Tuu se faamatalaga

Fa'aleaogaina le tali