Ho theha Heterogeneous Memory Systems ho FPGA SDK bakeng sa OpenCL Custom Platforms
Litaelo

Ho theha Heterogeneous Memory Systems ho Intel® FPGA SDK bakeng sa OpenCL Custom Platforms

Ho kengoa ts'ebetsong ha memori e fapaneng ho Sethala sa Tloaelo ho lumella hore ho be le bandwidth ea memori ea kantle (EMIF) hammoho le phihlello e kholo le e potlakileng ea memori. Motsoako oa phihlello ea memori e fapaneng le e ntlafalitsoeng
OpenCL ™(1)kernel e ka fella ka lintlafatso tse kholo tsa ts'ebetso ea sistimi ea hau ea OpenCL.
Molaetsa ona oa ts'ebeliso o fana ka tataiso mabapi le ho theha litsamaiso tsa memori tse fapaneng ka har'a Custom Platform hore e sebelisoe le Intel® FPGA SDK bakeng sa OpenCL(2). Intel e nka hore u moqapi oa FPGA ea nang le boiphihlelo ea ntseng a nts'etsapele Li-Platform tsa Tloaelo tse nang le litsamaiso tsa memori tse fapaneng.
Pele o theha lits'ebetso tsa memori tse fapaneng, itloaetse Intel FPGA SDK bakeng sa litokomane tsa OpenCL tse boletsoeng ka tlase.
Lintlha Tse Amanang

• Intel FPGA SDK bakeng sa OpenCL Programming Guide
• Intel FPGA SDK bakeng sa Tataiso ea Mekhoa e Metle ea OpenCL
• Intel FPGA SDK bakeng sa OpenCL Arria 10 GX FPGA Development Kit Reference Porting Guide

1.1. Ho netefatsa Ts'ebetso ea Boto ea FPGA le li-interface tsa EMIF

Netefatsa sehokelo se seng le se seng sa memori ka boikemelo, ebe o tiisa Platform ea hau ea Tloaelo u sebelisa mohopolo oa lefats'e.

1. Netefatsa segokanyimmediamentsi se seng le se seng sa memori o sebelisa meralo ea hardware e ka lekang lebelo le botsitso ba sebopeho ka seng.
2. Kenya Sethala sa hau sa Tloaelo u sebelisa mohopolo oa lefats'e.
   1. Bakeng sa mohlalaample, haeba u na le likhokahano tse tharo tsa DDR, e 'ngoe ea tsona e tlameha ho etsoa 'mapa e le mohopolo o fapaneng. Tabeng ena, netefatsa ts'ebetso ea "OpenCL stack" ka sebopeho se seng le se seng sa DDR ka boikemelo.
      OpenCL le logo ya OpenCL ke matshwao a kgwebo a Apple Inc. a sebediswang ka tumello ya Khronos Group™ .
   2.  Intel FPGA SDK bakeng sa OpenCL e ipapisitse le Tlhaloso ea Khronos e phatlalalitsoeng, 'me e fetile Ts'ebetso ea Teko ea Khronos Conformance. Boemo ba hona joale ba ho lumellana bo ka fumanoa ho www.khronos.org/conformance.

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.
ISO 9001:2015 E Ngolisitsoe
Ntle le moo, haeba u na le likhokahano tse peli tsa DDR le sehokelo se le seng sa quad data (QDR), netefatsa ts'ebetso ea "OpenCL stack" ea li-interface tse peli tsa DDR le sebopeho sa QDR ka boikemelo.
Intel e khothaletsa hore u sebelise PCI Express® - (PCIe® -) kapa meralo e ikhethileng ea EMIF ho leka likhokahano tsa memori ea hau. Kamora hore o netefatse hore sebopeho se seng le se seng sa memori se sebetsa le hore moralo oa OpenCL oa hau o sebetsa le karoloana ea likhokahano tsa memori, tsoela pele.
ho theha sistimi ea memori e fapaneng e sebetsang ka botlalo. 
1.2. Ho fetola board_spec.xml File
Fetola board_spec.xml file ho hlakisa mefuta ea li-memory system tse fapaneng tse fumanehang ho li-kernel tsa OpenCL.
Nakong ea ho kopanya kernel, Intel FPGA SDK ea OpenCL Offline Compiler e abela likhang tsa kernel mohopolong o ipapisitseng le khang ea sebaka sa buffer eo u e hlalosang.
1. Batla ho board_spec.xml file bukeng ea hardware ea Custom Platform ea hau.
2. Bula board_spec.xml file ho mohlophisi oa mongolo ebe u fetola XML ka nepo.
Bakeng sa mohlalaampLeha ho le joalo, haeba sesebelisoa sa hau sa hardware se na le mehopolo e 'meli ea DDR e le memori ea kamehla ea lefats'e le libanka tse peli tsa QDR tseo u li etsang e le memori e fapaneng, fetola likarolo tsa memori tsa board_spec.xml file ho tšoana le tse latelang:
















1.3. Ho theha Likarohano tse ngata tsa Memori ho Qsys
Hajoale, Karohano ea Banka ea Memori ea OpenCL moralong oa Qsys ha e tšehetse palo ea libanka tsa memori tse senang matla a 2, e seng moeli bakeng sa meralo e tloaelehileng. Leha ho le joalo, ho na le maemo ao ho seng matla-a-2 palo ea li-interfaces tsa memori li hlokahalang. Ho amohela li-non-power-of-2 palo ea li-memory interfaces, sebelisa li-multiple OpenCL Memory Bank Dividers ho theha mekhoa e mengata ea memori e nang le palo e se nang matla ea 2 ea libanka tsa memori. U tlameha ho theha li-Dividers tsa OpenCL Memory Bank tse ngata ha u na le sistimi ea 'nete e fapaneng ea memori. Nahana ka sistimi e nang le sebopeho se le seng sa memori sa DDR le sebopeho se le seng sa memori ea QDR. Hobane libanka tse peli li na le li-topology tse fapaneng tsa memori, u ke ke ua li kopanya tlas'a mohopolo o le mong oa lefats'e.
Setšoantšo sa 1. Setšoantšo sa Thibelo sa Memory Memory System ea Libanka tse tharo
Sistimi ena e fapaneng ea memori e na le likhokahano tse peli tsa memori ea DDR le sebopeho se le seng sa memori sa QDR.Haeba u sebelisa mofuta oa 16.0, 16.0.1, kapa 16.0.2 oa software ea Intel Quartus® Prime le Altera SDK bakeng sa OpenCL, OpenCL Memory Bank Divider e sebetsana le ho phatloha ha memori ka phoso ho tšela meeli ea liaterese. Ho rarolla bothata bona bo tsebahalang, eketsa borokho ba liphaephe tse phatlohileng ka boholo ba 1 'me u hokele master ea eona ea Avalon ®Memory-Mapped (Avalon-MM) boema-kepeng ba makhoba ba OpenCL Memory Bank Divider.
Hlokomela:
Taba ena e tsebahalang e hlophisitsoe ho Intel Quartus Prime software le Intel FPGA SDK bakeng sa mofuta oa OpenCL 16.1.
Setšoantšo sa 2. Sets'oants'o sa Thibelo ea Sistimi ea Memory ea Libanka tse Tharo e nang le Borokho ba Pipeline 1.4. Ho Fetola Lenaneo la Boardtest le Khoutu ea Host bakeng sa Tharollo ea Hao ea Memori e fapaneng
Sebelisa boardtest.cl kernel e tlang le Intel FPGA SDK bakeng sa OpenCL Custom Platform Toolkit ho lekola ts'ebetso le ts'ebetso ea Custom Platform ea hau.
Lenaneo la boardtest ke kernel ea OpenCL e u lumellang hore u leke bandwidth ea sesebediswa, bandwidth ea memori, le ts'ebetso e akaretsang ea Custom Platform.

1. Browse ho /board/ custom_platform_toolkit/test/boardtest directory.
2. Bula boardtest.cl file ho mohlophisi oa mongolo 'me u fane ka sebaka sa buffer ho ngangisano e' ngoe le e 'ngoe ea memori ea lefatše.
   Bakeng sa mohlalaampLe:
   __kernel ha e na letho
   mem_stream (__global__attribute__((buffer_location(“DDR”))) uint *src, __global __attribute__((buffer_location(“QDR”)))) uint *dst, uint arg, uint arg2)
   Mona, uint *src e abeloa memori ea DDR, 'me uint *dst e abeloa mohopolo oa QDR. The board_spec.xml file e hlalosa litšobotsi tsa tsamaiso ea memori ka bobeli.
3. Ho sebelisa tharollo ea memori e fapaneng ho sistimi ea hau ea OpenCL, fetola khoutu ea hau ka ho kenya folakha ea CL_MEM_HETEROGENEOUS_INTELFPGA mohala oa hau oa clCreateBuffer.
   Bakeng sa mohlalaampLe:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, boholo(bo sa saenwang) * vectorSize, NULL, &status);
   Intel e khothaletsa ka matla hore u behe sebaka sa buffer joalo ka khang ea kernel pele u ngola buffer. Ha o sebelisa mohopolo o le mong oa lefats'e, o ka ngola li-buffer pele kapa ka mor'a ho li abela khang ea kernel. Lits'ebetsong tse fapaneng tsa memori, moamoheli o beha sebaka sa buffer pele a ngola buffer. Ka mantsoe a mang, moamoheli o tla letsetsa ts'ebetso ea clSetKernelArgument pele a letsetsa ts'ebetso ea clEnqueueWriteBuffer.
   Khoutung ea hau ea moamoheli, kopa clCreateBuffer, clSetKernelArg, le clEnqueueWriteBuffer mehala ka tatellano e latelang:
   ddatain = clCreateBuffer(moteng, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, boholo(bo sa saenwang) * vectorSize, NULL, &status);
   … boemo = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (void*)&ddatain);
   … boemo = clEnqueueWriteBuffer(queue, ddatain, CL_FALSE, 0, sizeof(e sa saenang) * vectorSize,hdatain, 0, NULL, NULL);
   ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file e hlahisa tatelano e tshwanang ya di-call tsena tsa tshebetso.
4.  Ka mor'a hore u fetole boardtest.cl file le khoutu ea moamoheli, bokella moamoheli le khoutu ea kernel mme o netefatse ts'ebetso ea bona.
   Ha o hlophisa khoutu ea hau ea kernel, o tlameha ho tima ho phatloha ho hoholo ha lits'ebetso tsohle tsa memori ka ho kenyelletsa -no-interleaving. kgetho ka taelo ea aoc.

Lintlha Tse Amanang
Ho thibela Phallo ea Phallo ea Memori ea Lefatše (-ha ho-interleaving )

1.5. Ho netefatsa ho sebetsa ha memori ea hau e fapaneng Tsamaiso
Ho etsa bonnete ba hore sistimi ea memori e fapaneng e sebetsa hantle, hlakola folakha ea CL_CONTEXT_COMPILER_MODE_INTELFPGA khoutong ea hau.
Lits'ebetsong tsa OpenCL tse nang le mohopolo o tšoanang, u tlameha ho khetha ho seta folakha ea CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 khoutong ea hau ea moamoheli ho tima ho bala .aocx. file le ho hlophisoa bocha ha FPGA. Ho seta CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 folakha ho molemo ha o supisa boto ea hau ho netefatsa ts'ebetso ea Sethala sa hau sa Tloaelo ntle le ho rala moralo oa fatše le ho hlakisa libaka tsa LogicLock™.
Ka lisistimi tsa memori tse fapaneng, tikoloho ea nako ea ho sebetsa e tlameha ho bala libaka tsa buffer tsa buffer ka 'ngoe, tse hlalositsoeng ho .aocx file, ho netefatsa ts'ebetso ea litsamaiso tsa memori. Leha ho le joalo, o kanna oa batla ho netefatsa ts'ebetso ea Sethala sa hau sa Tloaelo ntle le ho kenya tšebetsong likarolo tsa ho qetela tsa moralo oa boto, joalo ka ho rala moralo oa fatše le ho hlakisa libaka tsa LogicLock.

1. Netefatsa hore folakha ea CL_CONTEXT_COMPILER_MODE_INTELFPGA ha e ea hlophisoa khoutong ea moamoheli.
2. Batla ho board/ /source/host/mmd directory ea Custom Platform ea hau.
3. Bula acl_pcie_device.cpp sesebediswa sa memori-mapped (MMD) file mohlophisi oa mongolo.
4.  Fetola tšebetso ea reprogram ho acl_pcie_device.cpp file ka ho eketsa kgutliso 0; line, joalokaha ho bontšitsoe ka tlase:
   int ACL_PCIE_DEVICE::reprogram(boid *data, size_t data_size)
   {
   khutla 0;
   // ho nka ho hloleha
   int reprogram_failed = 1;
   // nka hore ha ho rbf kapa hash ho fpga.bin
   int rbf_or_hash_not_provided = 1;
   // ho nka hore li-hashes tsa motheo le tsa tlhahiso ea kantle ha li lumellane
   int hash_mismatch = 1;
   …
   }
5. Hlahisa acl_pcie_device.cpp file.
6. Netefatsa hore folakha ea CL_CONTEXT_COMPILER_MODE_INTELFPGA e lula e sa hlophisoa.
   Tlhokomeliso: Ka mor'a hore u kenye khutlela 0; ho ts'ebetso ea reprogram le ho bokella MMD hape file, tikoloho ea nako ea ho sebetsa e tla bala .aocx file le ho abela libaka tsa buffer empa e ke ke ea hlophisa bocha FPGA. U tlameha ho bapisa setšoantšo sa FPGA le .aocx file. Ho fetola boitšoaro bona, tlosa kgutliso 0; ho tsoa tšebetsong ea reprogram le ho bokella MMD hape file.

1.6. Nalane ea Phetoho ea Litokomane

Letsatsi	Phetolelo	Liphetoho
Dec-17	2017.12.01	• E rehiloe bocha CL_MEM_HETEROGENEOUS_ALTERA ho CL_MEM_HETEROGENEOUS_INTELFPGA.
Dec-16	2016.12.13	• E rehiloe bocha CL_CONTEXT_COMPILER_MODE_ALTERA ho CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Ho theha Heterogeneous Memory Systems ho Intel® FPGA SDK bakeng sa OpenCL
Li-platform tsa tloaelo
Romella Maikutlo
Online Version
Romella Maikutlo
ID: 683654
Phetolelo: 2016.12.13

Litokomane / Lisebelisoa

intel Ho theha Memori Memory Systems ho FPGA SDK bakeng sa Lipolanete tsa Tloaelo tsa OpenCL [pdf] Litaelo Ho theha Heterogeneous Memory Systems ho FPGA SDK bakeng sa OpenCL Custom Platforms, Ho theha Heterogeneous Memory Systems, FPGA SDK bakeng sa OpenCL Custom Platforms

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