Ịmepụta Sistemụ ebe nchekwa dị iche iche na FPGA SDK maka OpenCL Custom Platform
Ntuziaka

Ịmepụta Sistemụ ebe nchekwa dị iche iche na Intel® FPGA SDK maka OpenCL Custom Platform

Mmejuputa ebe nchekwa dị iche iche na Platform Custom na-enye ohere maka bandwidth ebe nchekwa mpụga (EMIF) yana ịnweta ebe nchekwa buru ibu na ngwa ngwa. Ngwakọta ohere ebe nchekwa dị iche iche yana nke kachasị
OpenCL ™(1) kernel nwere ike rụpụta nkwalite arụmọrụ dị ukwuu maka sistemụ OpenCL gị.
Ihe ndetu ngwa a na-enye ntụzịaka maka ịmepụta sistemu ebe nchekwa dị iche iche na Platform omenala maka iji Intel® FPGA SDK maka OpenCL(2). Intel na-eche na ị bụ onye mmebe FPGA nwere ahụmahụ nke na-emepụta Platform Custom nwere sistemu ebe nchekwa dị iche iche.
Tupu ịmepụta sistemu ebe nchekwa dị iche iche, mara onwe gị nke ọma na Intel FPGA SDK maka akwụkwọ OpenCL akọwapụtara n'okpuru.
Ozi metụtara

• Intel FPGA SDK maka OpenCL Programming Guide
• Intel FPGA SDK maka OpenCL Ntuziaka kacha mma
• Intel FPGA SDK maka OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Ịkwado ọrụ nke Board FPGA na EMIF Interfaces

Nyochaa interface ebe nchekwa ọ bụla n'onwe ya wee were ebe nchekwa zuru ụwa ọnụ mee ngwa ngwa ngwa ngwa gị.

1. Nyochaa nhụta ebe nchekwa ọ bụla site na iji atụmatụ ngwaike nwere ike ịnwale ọsọ na nkwụsi ike nke interface ọ bụla.
2. Jiri ebe nchekwa zuru ụwa ọnụ malite ikpo okwu omenala gị ozugbo.
   1. Maka exampLe, ọ bụrụ na ị nwere atọ DDR interfaces, otu n'ime ha ga-mapped dị ka iche iche ebe nchekwa. N'okwu a, nyochaa ọrụ nke OpenCL stack na DDR interface ọ bụla n'adabereghị.
      OpenCL na akara OpenCL bụ ụghalaahịa nke Apple Inc. ejiri ikike nke Khronos Group™ .
   2.  Intel FPGA SDK maka OpenCL gbadoro ụkwụ na nkọwapụta Khronos ebipụtara, wee gafere Usoro Nleba anya nke Khronos. Enwere ike ịhụ ọkwa nkwenye ugbu a na www.khronos.org/conformance.

Ụlọ ọrụ Intel. Ikike niile echekwabara. Intel, akara Intel, na akara Intel ndị ọzọ bụ ụghalaahịa nke Intel Corporation ma ọ bụ ndị enyemaka ya. Intel nyere ikike ịrụ ọrụ nke FPGA na ngwaahịa semiconductor na nkọwapụta ugbu a dịka akwụkwọ ikike ọkọlọtọ Intel siri dị, mana nwere ikike ịme mgbanwe na ngwaahịa na ọrụ ọ bụla n'oge ọ bụla na-enweghị ọkwa. Intel anaghị ewere ọrụ ọ bụla ma ọ bụ ụgwọ sitere na ngwa ma ọ bụ iji ozi ọ bụla, ngwaahịa ma ọ bụ ọrụ akọwara n'ime ebe a belụsọ dị ka Intel kwetara na ederede. A dụrụ ndị ahịa Intel ọdụ ka ha nweta ụdị nkọwa ngwaọrụ kachasị ọhụrụ tupu ha adabere na ozi ọ bụla ebipụtara yana tupu ịnye iwu maka ngwaahịa ma ọ bụ ọrụ. * Enwere ike ịzọrọ aha na akara ndị ọzọ dị ka ihe onwunwe nke ndị ọzọ.
ISO 9001: 2015 edebanye aha
N'aka nke ọzọ, ọ bụrụ na ị nwere oghere DDR abụọ na otu ọnụọgụ data ọnụọgụ quad (QDR), nyochaa ọrụ nke OpenCL stack nke DDR abụọ yana interface QDR n'adabereghị.
Intel na-atụ aro ka ị jiri PCI Express® - (PCIe® -) ma ọ bụ EMIF-iche chepụta iji nwalee ebe nchekwa gị. Mgbe ị chọpụtachara na interface ebe nchekwa ọ bụla na-arụ ọrụ yana na imewe OpenCL gị na-arụ ọrụ na mpaghara ebe nchekwa, gaa n'ihu.
ka ịmepụta usoro ebe nchekwa dị iche iche na-arụ ọrụ zuru oke. 
1.2. Na-agbanwe ihe board_spec.xml File
Megharịa board_spec.xml file iji kọwapụta ụdị sistemụ ebe nchekwa dị iche iche dị na kernel OpenCL.
N'oge nchịkọta kernel, Intel FPGA SDK maka OpenCL Offline Compiler na-ekenye arụmụka kernel na ebe nchekwa dabere na arụmụka ọnọdụ nchekwa nke ị kọwapụtara.
1. Chọgharịa na board_spec.xml file na ndekọ ngwaike nke Platform omenala gị.
2. Mepee board_spec.xml file na editọ ederede wee gbanwee XML otu a.
Maka exampYabụ, ọ bụrụ na sistemụ ngwaike gị nwere ncheta DDR abụọ dị ka ihe nchekwa ụwa zuru oke na ụlọ akụ QDR abụọ nke ị na-egosipụta dị ka ebe nchekwa dị iche iche, gbanwee akụkụ ebe nchekwa nke board_spec.xml. file iji yie ihe ndia:
















1.3. Ịtọlite ​​ọtụtụ nkesa ebe nchekwa na Qsys
Ugbu a, OpenCL Memory Bank Divider na Qsys imewe anaghị akwado ọnụ ọgụgụ ebe nchekwa na-abụghị ike-2, nke na-abụghị njedebe maka nhazi nhazi. Agbanyeghị, enwere ọnọdụ ebe ọnụọgụ ebe nchekwa na-abụghị ike-2 dị mkpa. Iji nabata ọnụ ọgụgụ ebe nchekwa na-abụghị ike nke-2, jiri ọtụtụ OpenCL Memory Bank Dividers mepụta sistemu ebe nchekwa dị iche iche yana ọnụọgụ ebe nchekwa enweghị ike nke-2. Ị ga-emepụta ọtụtụ OpenCL Memory Bank Dividers mgbe ị nwere ezigbo usoro ebe nchekwa dị iche iche. Tụlee usoro nwere otu ebe nchekwa DDR yana otu interface ebe nchekwa QDR. N'ihi na ụlọ akụ abụọ ahụ nwere topologies ebe nchekwa dị iche iche, ị nweghị ike ijikọ ha n'okpuru otu ebe nchekwa ụwa.
Onyonyo 1. Ihe ngbochi nke sistemu ebe nchekwa dị iche iche nke ụlọ akụ atọ
Usoro ebe nchekwa dị iche iche nwere ebe nchekwa DDR abụọ yana otu interface ebe nchekwa QDR.Ọ bụrụ na ị na-eji ụdị 16.0, 16.0.1, ma ọ bụ 16.0.2 nke Intel Quartus® Prime software yana Altera SDK maka OpenCL, OpenCL Memory Bank Divider na-ejizi ebe nchekwa gbawara n'ofe oke adreesị. Iji rụọ ọrụ gburugburu okwu a amaara, gbakwunye akwa ọkpọkọ nwere oke gbawara agbawa nke 1 wee jikọọ nna ya ukwu Avalon ®Memory-Mapped (Avalon-MM) na ọdụ ụgbọ mmiri nke OpenCL Memory Bank Divider.
Mara:
Edere okwu a ama ama na sọftụwia Intel Quartus Prime yana Intel FPGA SDK maka ụdị OpenCL 16.1.
Onyonyo 2. Mgbochi eserese nke sistemu ebe nchekwa dị iche iche nke ụlọ akụ atọ nwere akwa pipeline 1.4. Ịgbanwe mmemme Boardtest na koodu nnabata maka ngwọta ebe nchekwa dị iche iche gị
Jiri boardtest.cl kernel nke na-abịa na Intel FPGA SDK maka OpenCL Custom Platform Toolkit iji nwalee arụmọrụ na arụmọrụ nke Platform omenala gị.
Ihe mmemme boardtest bụ kernel OpenCL na-enye gị ohere ịnwale bandwit nke ngwaọrụ-na-ngwaọrụ, bandwidth ebe nchekwa, yana ọrụ izugbe nke Platform omenala gị.

1. Chọgharịa gaa na /board/ custom_platform_toolkit/ tests/boardtest ndekọ.
2. Mepee boardtest.cl file na ndezi ederede ma kenye ebe nchekwa na arụmụka ebe nchekwa ụwa ọ bụla.
   Maka exampLe:
   __kernel efu
   mem_stream (__global__attribute__((buffer_location("DDR"))) uint *src, __global __attribute__((buffer_location("QDR"))) uint *dst, uint arg, uint arg2)
   N'ebe a, e kenyere uint * src na ebe nchekwa DDR, na uint * dst ka ekenye ya na ebe nchekwa QDR. The board_spec.xml file na-akọwapụta njirimara nke sistemụ nchekwa abụọ ahụ.
3. Iji tinye ihe ngwọta ebe nchekwa dị iche iche na sistemụ OpenCL gị, gbanwee koodu nnabata gị site na ịgbakwunye ọkọlọtọ CL_MEM_HETEROGENEOUS_INTELFPGA na oku clCreateBuffer gị.
   Maka exampLe:
   ddatain = clCreateBuffer (edemede, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, nha (anaghị edebanye aha) * vectorSize, NULL, & status);
   Intel na-akwadosi ike ka ịtọọ ebe nchekwa dị ka arụmụka kernel tupu ịde ihe nchekwa. Mgbe ị na-eji otu ebe nchekwa zuru ụwa ọnụ, ị nwere ike dee ihe nchekwa ahụ tupu ma ọ bụ mgbe ekenyechara ha na arụmụka kernel. N'ime sistemu ebe nchekwa dị iche iche, onye ọbịa na-edobe ebe nchekwa tupu ya edee ihe nchekwa. N'ikwu ya n'ụzọ ọzọ, onye ọbịa ga-akpọ ọrụ clSetKernelArgument tupu ịkpọ ọrụ clEnqueueWriteBuffer.
   Na koodu nnabata gị, kpọkuo clCreateBuffer, clSetKernelArg na clEnqueueWriteBuffer n'usoro a:
   ddatain = clCreateBuffer (okwu, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, nha (anaghị edebanye aha) * vectorSize, NULL, & status);
   … ọnọdụ = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (efu *)&ddatain);
   … ọnọdụ = clEnqueueWriteBuffer( kwụ n'ahịrị, ddatain, CL_FALSE, 0, sizeof (anaghị edebanye aha) * vectorSize,hdatain, 0, NULL, NULL);
   The ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file na-ewepụta usoro yiri nke oku ọrụ ndị a.
4.  Mgbe ị megharịrị boardtest.cl file na koodu nnabata, chịkọta koodu nnabata na kernel wee chọpụta ọrụ ha.
   Mgbe ị na-achịkọta koodu kernel gị, ị ga-agbanyụrịrị mwepu nke sistemu ebe nchekwa niile site na ịgụnye -no-interleaving. nhọrọ na iwu aoc.

Ozi metụtara
Ịkwụsị Burst-Interleaving of Global Memory (-enweghị nbanye )

1.5. Na-enyocha arụmọrụ nke ebe nchekwa dị iche iche gị Sistemu
Iji hụ na sistemu ebe nchekwa dị iche iche na-arụ ọrụ nke ọma, wepụ ọkọlọtọ CL_CONTEXT_COMPILER_MODE_INTELFPGA n'ime koodu nnabata gị.
Na sistemụ OpenCL nwere ebe nchekwa otu, ị ga-ahọrọ ịtọ ọkọlọtọ CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 n'ime koodu nnabata gị iji gbanyụọ ịgụ .aocx file na nhazigharị nke FPGA. Ịtọba ọkọlọtọ CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 bara uru mgbe ị na-etinye ngwa gị ozugbo iji nyochaa arụmọrụ nke Platform Custom gị na-enweghị imepụta atụmatụ ala yana ịkọwa mpaghara LogicLock™.
Site na sistemụ ebe nchekwa dị iche iche, gburugburu ebe a na-agba ọsọ ga-agụrịrị ebe nchekwa nchekwa nke ọ bụla, akọwara na .aocx file, iji nyochaa arụmọrụ nke sistemu ebe nchekwa. Agbanyeghị, ị nwere ike ịchọ ịchọpụta arụmọrụ nke Platform Custom gị na-emejuputaghị atụmatụ ikpeazụ nke nhazi bọọdụ, dị ka imepụta ala ala na ịkọwa mpaghara LogicLock.

1. Nyochaa na CL_CONTEXT_COMPILER_MODE_INTELFPGA emebibeghị ọkọlọtọ na koodu nnabata gị.
2. Chọgharịa na bọọdụ/ /source/host/mmd ndekọ nke Platform omenala gị.
3. Mepee ngwaọrụ acl_pcie_device.cpp ebe nchekwa (MMD) file na editọ ederede.
4.  Gbanwee ọrụ reprogram na acl_pcie_device.cpp file site n'ịgbakwunye nloghachi 0; ahịrị, dị ka egosiri n'okpuru:
   int ACL_PCIE_DEVICE :: reprogram(ihe efu *data, size_t data_size)
   {
   laghachi 0;
   // chere ọdịda
   int reprogram_failed = 1;
   // chere na ọ dịghị rbf ma ọ bụ hash na fpga.bin
   int rbf_or_hash_anaghị enye = 1;
   // were isi na mbubata hashes ngbanwe adabaghị
   int hash_mismatch = 1;
   …
   }
5. Tinyegharịa acl_pcie_device.cpp file.
6. Chọpụta na ọkọlọtọ CL_CONTEXT_COMPILER_MODE_INTELFPGA ka edobeghị ya.
   Nlebara anya: Mgbe ị gbakwunyere nloghachi 0; na ọrụ reprogram ma chịkọta MMD file, Oge ojiri gaa gburugburu ga-agụ .aocx file ma kenye ebe nchekwa mana agaghị ahazigharị FPGA. Ị ga-eji aka gị dakọọ foto FPGA na .aocx file. Iji tụgharịa omume a, wepụ nloghachi 0; site na ọrụ reprogram wee chịkọta MMD file.

1.6. Akụkọ Ndozigharị akwụkwọ

Ụbọchị	Ụdị	Mgbanwe
Dec-17	2017.12.01	• Kpọgharịrị aha CL_MEM_HETEROGENEOUS_ALTERA ka ọ bụrụ CL_MEM_HETEROGENEOUS_INTELFPGA.
Dec-16	2016.12.13	• Kpọgharịrị aha CL_CONTEXT_COMPILER_MODE_ALTERA ka ọ bụrụ CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Ịmepụta Sistemụ ebe nchekwa dị iche iche na Intel® FPGA SDK maka OpenCL
Platform omenala
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Version nke Ntanetị
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Nọmba ederede: 683654
Ụdị: 2016.12.13

Akwụkwọ / akụrụngwa

intel Mepụta Sistemụ ebe nchekwa dị iche iche na FPGA SDK maka OpenCL Custom Platform [pdf] Ntuziaka Ịmepụta Sistemụ ebe nchekwa dị iche iche na FPGA SDK maka OpenCL Custom Platform, Mepụta Sistemụ ebe nchekwa Heterogeneous, FPGA SDK maka OpenCL Custom Platform

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