Ke hana ʻana i nā Pūnaehana Hoʻomanaʻo Heterogeneous ma FPGA SDK no nā OpenCL Custom Platforms
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Ke hana ʻana i nā Pūnaehana Hoʻomanaʻo Heterogeneous ma Intel® FPGA SDK no nā OpenCL Custom Platforms

ʻO ka hoʻokō ʻana i ka hoʻomanaʻo heterogeneous i kahi Custom Platform e hiki ai i ka bandwidth hoʻomanaʻo waho waho (EMIF) a me ka nui a me ka wikiwiki o ka hoʻomanaʻo. ʻO ka hui pū ʻana o ka hoʻomanaʻo heterogenous me kahi optimized
Hiki i ka OpenCL ™ (1) kernel ke hopena i nā hoʻomaikaʻi hana nui no kāu ʻōnaehana OpenCL.
Hāʻawi kēia palapala noi i ke alakaʻi ʻana i ka hana ʻana i nā ʻōnaehana hoʻomanaʻo heterogeneous i kahi Papahana Kūʻai no ka hoʻohana ʻana me ka Intel® FPGA SDK no OpenCL(2). Manaʻo ʻo Intel he mea hoʻolālā FPGA akamai ʻoe e hoʻomohala nei i nā Papahana Kuʻuna i loaʻa nā ʻōnaehana hoʻomanaʻo heterogeneous.
Ma mua o ka hana ʻana i nā ʻōnaehana hoʻomanaʻo heterogeneous, e hoʻomaʻamaʻa iā ʻoe iho me ka Intel FPGA SDK no nā palapala OpenCL i kuhikuhi ʻia ma lalo nei.
ʻIke pili

• Intel FPGA SDK no ka OpenCL Programming Guide
• Intel FPGA SDK no ka OpenCL Best Practices Guide
• Intel FPGA SDK no OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Ke hōʻoia nei i ka hana o ka Papa FPGA a me nā Interfaces EMIF

E hōʻoia i kēlā me kēia memo hoʻomanaʻo kūʻokoʻa a laila e hoʻomaka koke i kāu Custom Platform me ka hoʻohana ʻana i ka hoʻomanaʻo honua.

1. E hōʻoia i kēlā me kēia mea hoʻomanaʻo me ka hoʻohana ʻana i nā hoʻolālā ʻenehana hiki ke hoʻāʻo i ka wikiwiki a me ka paʻa o kēlā me kēia interface.
2. E hoʻolalelale i kāu Pūnaewele Kūʻai me ka hoʻomanaʻo honua.
   1. No exampʻAe, inā loaʻa iā ʻoe ʻekolu mau kikowaena DDR, pono e hoʻopaʻa ʻia kekahi o lākou e like me ka hoʻomanaʻo heterogeneous. I kēia hihia, e hōʻoia i ka hana o ka waihona OpenCL me kēlā me kēia pānaehana DDR kūʻokoʻa.
      ʻO OpenCL a me ka hōʻailona OpenCL nā hōʻailona o Apple Inc. i hoʻohana ʻia ma ka ʻae ʻia e ka Khronos Group™.
   2.  Hoʻokumu ʻia ka Intel FPGA SDK no OpenCL ma kahi Khronos Specification i paʻi ʻia, a ua hala i ka Khronos Conformance Testing Process. Hiki ke loaʻa ke kūlana conformance o kēia manawa ma www.khronos.org/conformance.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.
ISO 9001:2015 Kakau
ʻO kahi ʻē aʻe, inā loaʻa iā ʻoe ʻelua mau kikowaena DDR a me hoʻokahi pānaehana helu quad data rate (QDR), e hōʻoia i ka hana o ka pūʻulu OpenCL o nā pānaehana DDR ʻelua a me ka interface QDR kūʻokoʻa.
Manaʻo ʻo Intel e hoʻohana ʻoe i ka PCI Express® - (PCIe® -) a i ʻole nā ​​hoʻolālā EMIF-kūʻokoʻa e hoʻāʻo ai i kāu mau pilina hoʻomanaʻo. Ma hope o kou hōʻoia ʻana i ka hana o kēlā me kēia hoʻomanaʻo hoʻomanaʻo a e hana ana kāu hoʻolālā OpenCL me kahi ʻāpana o nā pilina hoʻomanaʻo, e hoʻomau.
e hana i kahi ʻōnaehana hoʻomanaʻo heterogeneous holoʻokoʻa. 
1.2. Hoʻololi i ka board_spec.xml File
Hoʻololi i ka board_spec.xml file e kuhikuhi i nā ʻano o nā ʻōnaehana hoʻomanaʻo heterogeneous i loaʻa i nā kernels OpenCL.
I ka wā o ka hōʻuluʻulu ʻana, hāʻawi ka Intel FPGA SDK no OpenCL Offline Compiler i nā hoʻopaʻapaʻa kernel i kahi hoʻomanaʻo e pili ana i ka hoʻopaʻapaʻa wahi buffer āu i kuhikuhi ai.
1. E nānā i ka board_spec.xml file i loko o ka papa kuhikuhi lako o kāu Custom Platform.
2. E wehe i ka board_spec.xml file i loko o kahi hoʻoponopono kikokikona a hoʻololi i ka XML e like me ia.
No exampʻAe, inā ʻelua mau hoʻomanaʻo DDR i kāu ʻōnaehana lako ma ke ʻano he globalmemory paʻamau a me ʻelua mau panakō QDR āu e hoʻohālike ai me he hoʻomanaʻo heterogeneous, e hoʻololi i nā ʻāpana hoʻomanaʻo o ka board_spec.xml file e like me keia:
















1.3. Hoʻonohonoho i nā mea hoʻokaʻawale hoʻomanaʻo he nui ma Qsys
I kēia manawa, ʻaʻole kākoʻo ka OpenCL Memory Bank Divider i ka hoʻolālā Qsys i ka helu mana-o-2 o nā waihona hoʻomanaʻo, ʻaʻole ia he palena no nā hoʻonohonoho maʻamau. Eia nō naʻe, aia nā hiʻohiʻona kahi e pono ai ka helu non-power-of-2 o nā pilina hoʻomanaʻo. No ka hoʻokomo ʻana i nā helu hoʻomanaʻo ʻole o ka mana-o-2, e hoʻohana i nā OpenCL Memory Bank Dividers e hana i nā ʻōnaehana hoʻomanaʻo heterogeneous me ka helu ʻole-o-2 o nā waihona hoʻomanaʻo. Pono ʻoe e hana i nā OpenCL Memory Bank Dividers inā loaʻa iā ʻoe kahi ʻōnaehana hoʻomanaʻo heterogeneous maoli. E noʻonoʻo i kahi ʻōnaehana me hoʻokahi mea hoʻomanaʻo hoʻomanaʻo DDR a me hoʻokahi kikowaena hoʻomanaʻo QDR. No ka mea he ʻokoʻa nā topologies hoʻomanaʻo o nā panakō ʻelua, ʻaʻole hiki iā ʻoe ke hoʻohui iā lākou ma lalo o kahi hoʻomanaʻo honua hoʻokahi.
Kiʻi 1. Paʻi Paʻi o kahi Pūnaehana Hoʻomanaʻo Heterogeneous ʻEkolu Bank
Loaʻa i kēia ʻōnaehana hoʻomanaʻo heterogeneous ʻelua mau kikowaena hoʻomanaʻo DDR a me hoʻokahi kikowaena hoʻomanaʻo QDR.Inā ʻoe e hoʻohana nei i ka mana 16.0, 16.0.1, a i ʻole 16.0.2 o ka polokalamu Intel Quartus® Prime a me ka Altera SDK no OpenCL, ua hana hewa ka OpenCL Memory Bank Divider i nā poha hoʻomanaʻo ma nā palena o ka helu wahi. No ka hana ʻana i kēia pilikia i ʻike ʻia, e hoʻohui i kahi alahaka pipeline me ka nui o ka pohā o 1 a hoʻohui i kāna haku Avalon ®Memory-Mapped (Avalon-MM) i ke awa kauā o OpenCL Memory Bank Divider.
Nānā:
Hoʻopaʻa ʻia kēia pilikia i ʻike ʻia ma ka polokalamu Intel Quartus Prime a me ka Intel FPGA SDK no OpenCL version 16.1.
Kiʻi 2. Paʻi Paʻi o kahi Pūnaehana Hoʻomanaʻo Heterogeneous ʻEkolu Bank me kahi Alahaka Pipeline 1.4. Hoʻololi i ka Papahana Papa Hoʻopono a me ka Code Host no kāu Heterogeneous Memory Solution
E hoʻohana i ka kernel boardtest.cl i hele mai me ka Intel FPGA SDK no OpenCL Custom Platform Toolkit e hoʻāʻo ai i ka hana a me ka hana o kāu Custom Platform.
ʻO ka papahana boardtest kahi kernel OpenCL e hiki ai iā ʻoe ke hoʻāʻo i ka bandwidth host-to-device, bandwidth memory, a me ka hana maʻamau o kāu Custom Platform.

1. Huli i ka /board/ custom_platform_toolkit/tests/boardtest directory.
2. E wehe i ka boardtest.cl file i loko o kahi hoʻoponopono kikokikona a hāʻawi i kahi wahi hoʻopaʻa i kēlā me kēia hoʻopaʻapaʻa hoʻomanaʻo honua.
   No example:
   __ ʻaʻohe kumu
   mem_stream (__global__attribute__((buffer_location("DDR"))) uint *src, __global __attribute__((buffer_location("QDR"))) uint *dst, uint arg, uint arg2)
   Ma ʻaneʻi, ua hāʻawi ʻia ʻo uint *src i ka hoʻomanaʻo DDR, a ua hāʻawi ʻia ʻo uint *dst i ka hoʻomanaʻo QDR. ʻO ka papa_spec.xml file hōʻike i nā ʻano o nā ʻōnaehana hoʻomanaʻo ʻelua.
3. No ka hoʻohana ʻana i kāu ʻōnaehana hoʻomanaʻo heterogeneous i kāu ʻōnaehana OpenCL, e hoʻololi i kāu code host ma ka hoʻohui ʻana i ka hae CL_MEM_HETEROGENEOUS_INTELFPGA i kāu kelepona clCreateBuffer.
   No example:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, ka nui o (ka inoa ʻole) * ka nui vector, NULL, & kūlana);
   Manaʻo ikaika ʻo Intel e hoʻonoho ʻoe i ka wahi hoʻopaʻa ma ke ʻano he kumu hoʻopaʻapaʻa kernel ma mua o ke kākau ʻana i ka buffer. Ke hoʻohana nei i kahi hoʻomanaʻo honua hoʻokahi, hiki iā ʻoe ke kākau i nā buffers ma mua a ma hope paha o ka hāʻawi ʻana iā lākou i kahi hoʻopaʻapaʻa kernel. Ma nā ʻōnaehana hoʻomanaʻo heterogeneous, hoʻonohonoho ka mea hoʻokipa i ka wahi hoʻopaʻa ma mua o ke kākau ʻana i ka buffer. I nā huaʻōlelo ʻē aʻe, e kāhea ka mea hoʻokipa i ka hana clSetKernelArgument ma mua o ke kāhea ʻana i ka hana clEnqueueWriteBuffer.
   Ma kāu code host, e kāhea i nā kelepona clCreateBuffer, clSetKernelArg, a me clEnqueueWriteBuffer ma ke ʻano penei:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, ka nui o (ka inoa ʻole) * ka nui vector, NULL, & kūlana);
   … kūlana = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (void*)&ddatain);
   … kūlana = clEnqueueWriteBuffer(queue, ddatain, CL_FALSE, 0, sizeof(unsigned) * vectorSize, hdatain, 0, NULL, NULL);
   ʻO ka ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file hōʻike i kahi ʻano like o kēia mau kelepona hana.
4.  Ma hope o kou hoʻololi ʻana i ka boardtest.cl file a me ka code host, e hōʻuluʻulu i ka host a me ka code kernel a hōʻoia i kā lākou hana.
   I ka hōʻuluʻulu ʻana i kāu code kernel, pono ʻoe e hoʻopau i ka burst-interleaving o nā ʻōnaehana hoʻomanaʻo āpau ma o ka hoʻokomo ʻana i ka -no-interleaving. koho ma ke kauoha aoc.

ʻIke pili
Hoʻopau i ka Burst-Interleaving o Global Memory (–no-interleaving )

1.5. Ke hōʻoia nei i ka hana o kāu hoʻomanaʻo heterogeneous Pūnaehana
No ka hōʻoia i ka holo pono ʻana o ka ʻōnaehana hoʻomanaʻo heterogeneous, wehe i ka hae CL_CONTEXT_COMPILER_MODE_INTELFPGA i kāu code host.
I nā ʻōnaehana OpenCL me ka hoʻomanaʻo like ʻole, pono ʻoe e koho e hoʻonohonoho i ka hae CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 i kāu code host e hoʻopau i ka heluhelu ʻana o ka .aocx file a me ka hoʻonohonoho hou ʻana o ka FPGA. Pono ka hoʻonohonoho ʻana i ka hae CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 i ka wā e hoʻomaka koke ai i kāu papa e hōʻoia i ka hana o kāu Papa Kūlana me ka hoʻolālā ʻole i ka papahele a me ka wehewehe ʻana i nā ʻāpana LogicLock™.
Me nā ʻōnaehana hoʻomanaʻo heterogeneous, pono e heluhelu ke kaiapuni holo i nā wahi pale o kēlā me kēia buffer, i wehewehe ʻia ma ka .aocx file, e hōʻoia i ka hana o nā ʻōnaehana hoʻomanaʻo. Eia nō naʻe, makemake paha ʻoe e hōʻoia i ka hana o kāu Custom Platform me ka ʻole o ka hoʻokō ʻana i nā hiʻohiʻona hope o ka hoʻolālā papa, e like me ka hoʻolālā ʻana i ka papahele a me ka wehewehe ʻana i nā ʻāpana LogicLock.

1. E hōʻoia ʻaʻole i hoʻonohonoho ʻia ka hae CL_CONTEXT_COMPILER_MODE_INTELFPGA i kāu code host.
2. E nānā i ka papa/ /source/host/mmd papa kuhikuhi o kāu Custom Platform.
3. Wehe i ka acl_pcie_device.cpp mea hoʻomanaʻo palapala ʻāina (MMD) file ma kahi hoʻoponopono kikokikona.
4.  Hoʻololi i ka hana reprogram ma ka acl_pcie_device.cpp file ma ka hoʻohui ʻana i kahi hoʻihoʻi 0; laina, e like me ka mea i hōʻike ʻia ma lalo nei:
   int ACL_PCIE_DEVICE:: hoʻoponopono hou ʻia (ʻaʻohe *ʻikepili, size_t data_size)
   {
   hoihoi 0;
   // kuhi hewa
   int reprogram_failed = 1;
   // manaʻo ʻaʻohe rbf a i ʻole hash ma fpga.bin
   int rbf_or_hash_not_provided = 1;
   // manaʻo ʻaʻole kūlike nā hashes hoʻoponopono kumu a hoʻokomo
   int hash_mismatch = 1;
   …
   }
5. Hoʻopili hou i ka acl_pcie_device.cpp file.
6. E hōʻoia i ka pau ʻole o ka hae CL_CONTEXT_COMPILER_MODE_INTELFPGA.
   Nānā: Ma hope o kou hoʻohui ʻana i ka hoʻihoʻi 0; i ka hana reprogram a hoʻopili hou i ka MMD file, e heluhelu ana ke kaiapuni holo i ka .aocx file a hāʻawi i nā wahi paʻa akā ʻaʻole e hoʻoponopono hou i ka FPGA. Pono ʻoe e hoʻohālikelike lima i ke kiʻi FPGA me ka .aocx file. No ka hoʻohuli ʻana i kēia ʻano, e wehe i ka hoʻihoʻi 0; mai ka hana reprogram a hoʻopili hou i ka MMD file.

1.6. Moolelo Hooponopono Palapala

Lā	Manao	Nā hoʻololi
Dek-17	2017.12.01	• Kapa hou ia CL_MEM_HETEROGENEOUS_ALTERA iā CL_MEM_HETEROGENEOUS_INTELFPGA.
Dek-16	2016.12.13	• Kapa hou ia CL_CONTEXT_COMPILER_MODE_ALTERA i CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Ke hana nei i nā Pūnaehana Hoʻomanaʻo Heterogeneous ma Intel® FPGA SDK no OpenCL
Nā Papahana Kuʻuna
Hoʻouna Manaʻo
Online Version
Hoʻouna Manaʻo
ID: 683654
Manaʻo: 2016.12.13

Palapala / Punawai

intel Ke hana nei i nā Pūnaehana Hoʻomanaʻo Heterogeneous ma FPGA SDK no nā OpenCL Custom Platforms [pdf] Na kuhikuhi Ke hana ʻana i nā ʻōnaehana hoʻomanaʻo like ʻole ma FPGA SDK no nā OpenCL Custom Platforms, Hoʻokumu ʻana i nā Pūnaehana Hoʻomanaʻo Heterogenous, FPGA SDK no OpenCL Custom Platforms.

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