Ƙirƙirar Tsarukan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa a cikin FPGA SDK don OpenCL Platforms Custom
Umarni

Ƙirƙirar Tsarukan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa a cikin Intel® FPGA SDK don OpenCL Platforms Custom

Aiwatar da ƙwaƙwalwar ajiya iri-iri a cikin Platform na Musamman yana ba da damar ƙarin bandwidth na ƙwaƙwalwar waje (EMIF) tare da samun damar ƙwaƙwalwar ajiya mai girma da sauri. Haɗin samun damar ƙwaƙwalwar ajiya iri-iri tare da ingantaccen aiki
OpenCL ™(1) kwaya na iya haifar da ingantaccen aiki don tsarin OpenCL ɗin ku.
Wannan bayanin kula na aikace-aikacen yana ba da jagora kan ƙirƙirar tsarin ƙwaƙwalwar ajiya iri-iri a cikin Tsarin Kwamfuta don amfani tare da Intel® FPGA SDK don OpenCL(2). Intel yana ɗauka cewa kai ƙwararren ƙwararren FPGA ne wanda ke haɓaka Platform na Musamman waɗanda ke ɗauke da tsarin ƙwaƙwalwar ajiya iri-iri.
Kafin ƙirƙirar tsarin ƙwaƙwalwar ajiya iri-iri, san kanku da Intel FPGA SDK don takaddun Buɗewar da aka kayyade a ƙasa.
Bayanai masu alaƙa

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• Intel FPGA SDK don Buɗe CL Mafi kyawun Jagorar Ayyuka
• Intel FPGA SDK don OpenCL Arria 10 GX FPGA Rarraba Kayan Rarraba Kayan Kayan Kayan Kayan Kayan Kayan Kaya

1.1. Tabbatar da Ayyukan Hukumar FPGA da Mu'amalar EMIF

Tabbatar da kowace ƙa'idar ƙwaƙwalwar ajiya da kanta sannan kuma saita Platform ɗin Custom ɗin ku ta amfani da ƙwaƙwalwar duniya.

1. Tabbatar da kowace ƙirar ƙwaƙwalwar ajiya ta amfani da ƙirar kayan masarufi waɗanda za su iya gwada sauri da kwanciyar hankali na kowane keɓancewa.
2. Ƙaddamar da Platform ɗinku na Musamman ta amfani da ƙwaƙwalwar duniya.
   1. Don misaliampTo, idan kana da uku DDR musaya, daya daga cikinsu dole ne a yi taswira a matsayin iri-iri memory. A wannan yanayin, tabbatar da aikin tarin OpenCL tare da kowane ƙirar DDR da kansa.
      OpenCL da tambarin OpenCL alamun kasuwanci ne na Apple Inc. amfani da izinin Khronos Group™ .
   2.  Intel FPGA SDK na OpenCL ya dogara ne akan ƙayyadaddun ƙayyadaddun Khronos da aka buga, kuma ya wuce Tsarin Gwajin Ƙarfafawa na Khronos. Ana iya samun matsayin yarda na yanzu a www.khronos.org/conformance.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.
ISO 9001: 2015 Rajista
A madadin, idan kuna da musaya na DDR guda biyu da ƙirar ƙimar bayanan quad guda ɗaya (QDR), tabbatar da aikin tarin OpenCL na DDR guda biyu da kuma ƙirar QDR da kanta.
Intel yana ba da shawarar cewa kayi amfani da PCI Express® - (PCIe® -) ko keɓaɓɓen ƙira na EMIF don gwada mu'amalar ƙwaƙwalwar ajiyar ku. Bayan kun tabbatar da cewa kowace ƙirar ƙwaƙwalwar ajiya tana aiki kuma ƙirar OpenCL ɗinku tana aiki tare da wani yanki na mu'amalar ƙwaƙwalwar ajiya, ci gaba.
don ƙirƙirar tsarin ƙwaƙwalwar ajiya iri-iri mai cikakken aiki. 
1.2. Gyara allon allo_spec.xml File
Gyara allon_spec.xml file don tantance nau'ikan tsarin ƙwaƙwalwar ajiya iri-iri waɗanda ke samuwa ga kernels na OpenCL.
A yayin tattara kwaya, Intel FPGA SDK don OpenCL Offline Compiler yana ba da gardamar kernel zuwa ƙwaƙwalwar ajiya dangane da mahawarar wurin buffer ɗin da kuka ƙayyade.
1. Bincika zuwa allon_spec.xml file a cikin kundin adireshin hardware na Platform ɗinku na Custom.
2. Bude allon_spec.xml file a cikin editan rubutu kuma gyara XML daidai.
Don misaliampDon haka, idan tsarin kayan aikin ku yana da abubuwan ƙwaƙwalwar DDR guda biyu azaman ƙwaƙwalwar ajiyar duniya da kuma bankunan QDR guda biyu waɗanda kuke ƙira azaman ƙwaƙwalwa iri-iri, gyara sassan ƙwaƙwalwar ajiya na board_spec.xml file don kama da haka:
















1.3. Ƙirƙirar Ƙwararrun Ƙwaƙwalwar Ƙwaƙwalwa a cikin Qsys
A halin yanzu, Mai Rarraba Bankin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na OpenCL a cikin ƙirar Qsys baya goyan bayan adadin bankunan ƙwaƙwalwar ajiya mara ƙarfi na-2, wanda ba iyaka ba ne don daidaitawa na yau da kullum. Koyaya, akwai yanayi inda adadin mu'amalar ƙwaƙwalwar ajiya mara ƙarfi na-2 ya zama dole. Don ɗaukar adadin mu'amalar ƙwaƙwalwar ajiya mara ƙarfi-na-2, yi amfani da OpenCL Memory Bank Dividers da yawa don ƙirƙirar tsarin ƙwaƙwalwar ajiya iri-iri tare da adadin bankunan ƙwaƙwalwar ajiya mara ƙarfi-na-2. Dole ne ku ƙirƙiri Masu Rarraba Bankin Ƙwaƙwalwa na OpenCL lokacin da kuke da tsarin ƙwaƙwalwar ajiya iri-iri na gaskiya. Yi la'akari da tsarin tare da ƙwaƙwalwar ƙwaƙwalwar DDR guda ɗaya da ƙirar ƙwaƙwalwar QDR guda ɗaya. Saboda bankunan biyu suna da nau'ikan ƙwaƙwalwar ajiya daban-daban, ba za ku iya haɗa su a ƙarƙashin ƙwaƙwalwar ajiya ɗaya ta duniya ba.
Hoto 1. Toshe zane na Tsarin Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwa na Banki Uku
Wannan tsarin ƙwaƙwalwar ajiya iri-iri yana ƙunshe da mu'amalar ƙwaƙwalwar DDR guda biyu da ƙirar ƙwaƙwalwar QDR guda ɗaya.Idan kana amfani da sigar 16.0, 16.0.1, ko 16.0.2 na Intel Quartus® Prime software da Altera SDK don OpenCL, Mai Rarraba Bankin Ƙwaƙwalwa na OpenCL ba daidai ba yana sarrafa fashe ƙwaƙwalwar ajiya a kan iyakokin adireshi. Don yin aiki a kusa da wannan sanannen batu, ƙara gadar bututu tare da fashe girman 1 kuma haɗa Avalon ®Memory-Mapped (Avalon-MM) ubangidansa zuwa tashar bawan OpenCL Memory Bank Divider.
Lura:
Wannan sanannen batun an daidaita shi a cikin software na Intel Quartus Prime da Intel FPGA SDK don sigar OpenCL 16.1.
Hoto 2. Toshe zane na Tsarin Ƙwararren Ƙwararren Ƙwararren Ƙwaƙwalwar Banki Uku tare da Gadar Bututu 1.4. Gyara Shirin Boardtest da Lambar Mai watsa shiri don Maganin Ƙwaƙwalwar Ƙwaƙwalwar Ku
Yi amfani da boardtest.cl kernel wanda yazo tare da Intel FPGA SDK don Buɗewar Kayan aikin Platform na Musamman don gwada ayyuka da aikin Platform ɗinku na Musamman.
Shirin boardtest shine kernel na OpenCL wanda ke ba ku damar gwada bandwidth mai watsa shiri-zuwa-na'ura, bandwidth ƙwaƙwalwar ajiya, da ayyukan gaba ɗaya na Platform ɗin ku.

1. Yi lilo zuwa ga /board/ custom_platform_toolkit/tests/booktest directory.
2. Bude boardtest.cl file a cikin editan rubutu kuma sanya wurin buffer zuwa kowace hujjar ƙwaƙwalwar ajiyar duniya.
   Don misaliampda:
   _kwayar kwaya
   mem_stream (__global__ sifa __((buffer_location("DDR"))) uint *src, __global __siffata__((buffer_location("QDR"))) uint *dst, uint arg, uint arg2)
   Anan, an sanya uint *src zuwa ƙwaƙwalwar ajiyar DDR, kuma an sanya uint *dst zuwa ƙwaƙwalwar QDR. Allon_spec.xml file Yana ƙayyadaddun halaye na tsarin ƙwaƙwalwar ajiya guda biyu.
3. Don yin amfani da tsarin ƙwaƙwalwar ajiya daban-daban a cikin tsarin OpenCL ɗin ku, canza lambar mai masaukin ku ta ƙara CL_MEM_HETEROGENEOUS_INTELFPGA tutar zuwa kiran clCreateBuffer na ku.
   Don misaliampda:
   ddatain = clCreateBuffer (magana, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, girman (ba a sanya hannu ba) * girman girman, NULL, & matsayi;
   Intel yana ba da shawarar sosai cewa ka saita wurin buffer azaman hujjar kwaya kafin rubuta buffer. Lokacin amfani da ƙwaƙwalwar ajiya guda ɗaya ta duniya, zaku iya rubuta buffers ko dai kafin ko bayan sanya su zuwa gardamar kwaya. A cikin tsarin ƙwaƙwalwar ajiya iri-iri, mai watsa shiri yana saita wurin buffer kafin rubuta buffer. A wasu kalmomi, mai watsa shiri zai kira aikin clSetKernelArgument kafin kiran aikin clEnqueueWriteBuffer.
   A cikin lambar rundunar ku, kira clCreateBuffer, clSetKernelArg, da clEnqueueWriteBuffer a cikin tsari mai zuwa:
   ddatain = clCreateBuffer (yanayin, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, girman (ba a sanya hannu ba) * girman girman, NULL, & matsayi;
   … hali = clSetKernelArg (kwaya [k], 0, sizeof(cl_mem), (void*)&ddatain);
   ... matsayi = clEnqueueWriteBuffer ( jerin gwano, ddatain, CL_FALSE, 0, girman (ba a sanya hannu ba) * girman girman, hdatain, 0, NULL, NULL);
   ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file yana gabatar da irin wannan tsari na waɗannan kiran aikin.
4.  Bayan kun gyara boardtest.cl file da lambar runduna, tara mai masaukin baki da lambar kwaya kuma tabbatar da aikin su.
   Lokacin tattara lambar kernel ɗin ku, dole ne ku kashe fashe-interleaving na duk tsarin ƙwaƙwalwar ajiya ta haɗa da -no-interleaving. zaɓi a cikin umarnin aoc.

Bayanai masu alaƙa
Kashe Fashe-Interleaving na Ƙwaƙwalwar Ƙwaƙwalwar Duniya (-ba-in-interleaving )

1.5. Tabbatar da Ayyukan Ƙwaƙwalwar Ƙwaƙwalwar ku Tsari
Don tabbatar da cewa tsarin ƙwaƙwalwar ajiya iri-iri yana aiki yadda ya kamata, cire saitin CL_CONTEXT_COMPILER_MODE_INTELFPGA a lambar mai masaukin ku.
A cikin tsarin OpenCL tare da ƙwaƙwalwar ajiya iri ɗaya, dole ne ku zaɓi don saita tutar CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 a cikin lambar gidan ku don musaki karatun .aocx file da kuma sake tsara tsarin FPGA. Saita CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 tuta yana da amfani yayin zazzage allon allon ku don tabbatar da aikin Platform ɗinku na Musamman ba tare da ƙirƙira tsarin bene da ƙayyadaddun yankuna na LogicLock™ ba.
Tare da tsarin ƙwaƙwalwar ajiya iri-iri, yanayin lokacin aiki dole ne ya karanta wuraren buffer na kowane buffer, wanda aka kwatanta a cikin .aocx file, don tabbatar da aikin tsarin ƙwaƙwalwar ajiya. Koyaya, kuna iya tabbatar da aikin Platform ɗinku na Musamman ba tare da aiwatar da fasalulluka na ƙarshe na ƙirar hukumar ba, kamar tsara tsarin ƙasa da ƙayyadaddun yankuna na LogicLock.

1. Tabbatar da cewa CL_CONTEXT_COMPILER_MODE_INTELFPGA ba a saita tuta a lambar gidan ku ba.
2. Shiga zuwa allon / /source/host/mmd directory na Platform ɗinku na Musamman.
3. Bude na'urar acl_pcie_device.cpp memory-mapped (MMD) file a cikin editan rubutu.
4.  Gyara aikin reprogram a cikin acl_pcie_device.cpp file ta ƙara komawa 0; line, kamar yadda aka nuna a kasa:
   int ACL_PCIE_DEVICE :: reprogram (rashin * bayanai, girman_t data_size)
   {
   dawo 0;
   // ɗauka gazawa
   int reprogram_failed = 1;
   // ɗauka babu rbf ko zanta a fpga.bin
   int rff_or_hash_not_provided = 1;
   // ɗauka tushe da shigo da hashes bita bai dace ba
   int hash_mismatch = 1;
   …
   }
5. Sake tattara acl_pcie_device.cpp file.
6. Tabbatar da cewa tuta CL_CONTEXT_COMPILER_MODE_INTELFPGA ta kasance ba a saita ba.
   Hankali: Bayan kun ƙara dawowa 0; zuwa aikin reprogram kuma sake tattara MMD file, yanayin lokacin aiki zai karanta .aocx file kuma sanya wuraren buffer amma ba zai sake tsara FPGA ba. Dole ne ku dace da hoton FPGA da hannu tare da .aocx file. Don juya wannan hali, cire dawowa 0; daga aikin reprogram kuma sake tattara MMD file.

1.6. Tarihin Bita daftarin aiki

Kwanan wata	Sigar	Canje-canje
Dec-17	2017.12.01	• Sakewa CL_MEM_HETEROGENEOUS_ALTERA zuwa CL_MEM_HETEROGENEOUS_INTELFPGA.
Dec-16	2016.12.13	• Sake masa suna CL_CONTEXT_COMPILER_MODE_ALTERA zuwa CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Ƙirƙirar Tsarukan Ƙwaƙwalwar Ƙwaƙwalwa a cikin Intel® FPGA SDK don OpenCL
Dandali na Musamman
Aika da martani
Online Version
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Saukewa: 683654
Shafin: 2016.12.13

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intel Ƙirƙirar Tsarukan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa a cikin FPGA SDK don OpenCL Platforms Custom [pdf] Umarni Ƙirƙirar Tsarukan Ƙwaƙwalwar Ƙwaƙwalwar Ƙwaƙwalwa a cikin FPGA SDK don OpenCL Platforms Custom, Ƙirƙirar Tsarin Ƙwaƙwalwar Ƙwaƙwalwa, FPGA SDK don OpenCL Custom Platforms

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