Tsim Heterogeneous Memory Systems hauv FPGA SDK rau OpenCL Custom Platforms
Cov lus qhia

Tsim Heterogeneous Memory Systems hauv Intel® FPGA SDK rau OpenCL Custom Platforms

Qhov kev siv ntawm heterogeneous nco nyob rau hauv ib tug Custom Platform tso cai rau ntau sab nraud nco interface (EMIF) bandwidth raws li zoo raws li loj thiab ceev ceev nkag. Kev sib xyaw ua ke ntawm heterogenous nco nkag nrog kev ua kom zoo
OpenCL ™ (1) kernel tuaj yeem ua rau muaj kev txhim kho tseem ceeb rau koj qhov OpenCL system.
Daim ntawv thov no muab kev taw qhia txog kev tsim cov txheej txheem kev nco zoo sib xws hauv Custom Platform rau siv nrog Intel® FPGA SDK rau OpenCL(2). Intel xav tias koj yog tus paub txog FPGA tus tsim qauv uas tab tom tsim Custom Platforms uas muaj ntau lub cim xeeb.
Ua ntej tsim cov txheej txheem nco heterogeneous, paub koj tus kheej nrog Intel FPGA SDK rau OpenCL cov ntaub ntawv teev tseg hauv qab no.
Cov ntaub ntawv ntsig txog

• Intel FPGA SDK rau OpenCL Programming Guide
• Intel FPGA SDK rau OpenCL Cov Lus Qhia Zoo Tshaj Plaws
• Intel FPGA SDK rau OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Txheeb xyuas qhov ua haujlwm ntawm FPGA Board thiab EMIF Interfaces

Tshawb xyuas txhua lub cim xeeb interface ntawm nws tus kheej thiab tom qab ntawd instantiate koj lub Platform Kev Cai siv lub cim xeeb thoob ntiaj teb.

1. Tshawb xyuas txhua lub cim xeeb interface siv cov khoom siv kho vajtse uas tuaj yeem kuaj qhov nrawm thiab ruaj khov ntawm txhua qhov interface.
2. Instantiate koj Custom Platform siv lub cim xeeb thoob ntiaj teb.
   1. Rau example, yog tias koj muaj peb DDR interfaces, ib qho ntawm lawv yuav tsum tau mapped li heterogeneous nco. Hauv qhov no, txheeb xyuas qhov ua haujlwm ntawm OpenCL pawg nrog txhua DDR interface ntawm nws tus kheej.
      OpenCL thiab OpenCL logo yog cov cim lag luam ntawm Apple Inc. siv los ntawm kev tso cai ntawm Khronos Group ™ .
   2.  Intel FPGA SDK rau OpenCL yog raws li kev tshaj tawm Khronos Specification, thiab tau dhau los ntawm Khronos Conformance Testing Process. Cov xwm txheej tam sim no tuaj yeem pom ntawm www.khronos.org/conformance.

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.
Daim ntawv pov thawj ISO 9001: 2015
Xwb, yog tias koj muaj ob qhov DDR interfaces thiab ib qho quad data rate (QDR) interface, txheeb xyuas qhov ua haujlwm ntawm OpenCL pawg ntawm ob DDR interfaces thiab QDR interface ntawm nws tus kheej.
Intel xav kom koj siv PCI Express® - (PCIe® -) lossis EMIF-tsuas yog tsim los kuaj koj lub cim xeeb interfaces. Tom qab koj txheeb xyuas tias txhua lub cim xeeb interface ua haujlwm tau zoo thiab tias koj tus qauv OpenCL ua haujlwm nrog cov txheej txheem ntawm lub cim xeeb interfaces, mus tom ntej.
los tsim kom muaj kev ua haujlwm siab heterogeneous nco system. 
1.2. Hloov kho lub board_spec.xml File
Hloov kho lub board_spec.xml file txhawm rau txheeb xyuas cov hom kev nco heterogeneous uas muaj rau OpenCL kernels.
Thaum lub sijhawm sau cov ntsiav, Intel FPGA SDK rau OpenCL Offline Compiler muab cov lus sib cav rau lub cim xeeb raws li qhov tsis sib haum xeeb qhov chaw sib cav uas koj tau teev tseg.
1. Xauj rau board_spec.xml file nyob rau hauv lub hardware directory ntawm koj Custom Platform.
2. Qhib lub board_spec.xml file hauv cov ntawv nyeem thiab hloov kho XML raws li.
Rau example, yog tias koj lub khoos phis tawj kho vajtse muaj ob lub DDR nco raws li lub ntiaj teb kev nco thiab ob lub txhab nyiaj QDR uas koj ua qauv ua cim xeeb, hloov kho cov ntu nco ntawm board_spec.xml file kom zoo li cov hauv qab no:
















1.3. Teem Ntau Ntau Qhov Kev Ntsuas Hauv Qsys
Tam sim no, OpenCL Memory Bank Divider hauv Qsys tsim tsis txhawb nqa tsis muaj hwj chim-ntawm-2 tus lej ntawm lub txhab nyiaj nco, uas tsis yog qhov txwv rau kev teeb tsa raug. Txawm li cas los xij, muaj cov xwm txheej uas tsis muaj hwj chim-ntawm-2 tus lej ntawm lub cim xeeb cuam tshuam yog tsim nyog. Txhawm rau ua kom tsis muaj zog-ntawm-2 tus lej ntawm lub cim xeeb cuam tshuam, siv ntau lub OpenCL Memory Bank Dividers los tsim cov txheej txheem nco tsis zoo nrog cov tsis muaj hwj chim-ntawm-2 tus lej ntawm lub txhab nyiaj nco. Koj yuav tsum tsim ntau OpenCL Memory Bank Dividers thaum koj muaj qhov tseeb heterogeneous nco system. Xav txog lub kaw lus nrog ib qho DDR nco interface thiab ib qho QDR nco interface. Vim hais tias ob lub tsev txhab nyiaj muaj qhov sib txawv nco topologies, koj tsis tuaj yeem muab lawv tso rau hauv ib lub cim xeeb thoob ntiaj teb.
Daim duab 1. Block Diagram ntawm Peb-Bank Heterogeneous Memory System
Qhov no heterogeneous nco system muaj ob DDR nco interfaces thiab ib QDR nco interface.Yog tias koj siv version 16.0, 16.0.1, lossis 16.0.2 ntawm Intel Quartus® Prime software thiab Altera SDK rau OpenCL, OpenCL Memory Bank Divider tsis raug tswj hwm kev nco tawg thoob plaws thaj tsam chaw nyob. Txhawm rau ua haujlwm nyob ib puag ncig qhov teeb meem paub, ntxiv cov kav dej txuas nrog qhov tawg loj ntawm 1 thiab txuas nws Avalon ®Memory-Mapped (Avalon-MM) tus tswv rau OpenCL Memory Bank Divider tus qhev chaw nres nkoj.
Nco tseg:
Qhov teeb meem paub no yog kho nyob rau hauv Intel Quartus Prime software thiab Intel FPGA SDK rau OpenCL version 16.1.
Daim duab 2. Thaiv Daim duab ntawm Peb Lub Tuam Txhab Heterogeneous Memory System nrog rau Pipeline Choj 1.4. Hloov Kho Cov Kev Pabcuam Boardtest thiab Tus Tswv Cuab Code rau Koj Txoj Kev Nco Heterogeneous
Siv boardtest.cl kernel uas los nrog Intel FPGA SDK rau OpenCL Custom Platform Toolkit los ntsuas qhov ua haujlwm thiab kev ua haujlwm ntawm koj lub Platform Custom.
Qhov kev pab cuam boardtest yog OpenCL kernel uas tso cai rau koj los ntsuas tus tswv-rau-cov khoom siv bandwidth, nco bandwidth, thiab kev ua haujlwm dav dav ntawm koj lub Platform Custom.

1. Xauj rau lub /board/ custom_platform_toolkit/tests/boardtest directory.
2. Qhib lub boardtest.cl file nyob rau hauv cov ntawv nyeem thiab muab qhov chaw tsis nyob rau txhua qhov kev sib cav hauv ntiaj teb nco.
   Rau example:
   __kernel void
   mem_stream (__global__attribute__((buffer_location("DDR")))) uint *src, __global __attribute__((buffer_location("QDR"))) uint *dst, uint arg, uint arg2)
   Ntawm no, uint * src raug muab rau DDR nco, thiab uint * dst raug muab rau QDR nco. board_spec.xml file qhia cov yam ntxwv ntawm ob lub cim xeeb.
3. Txhawm rau siv koj cov kev daws teeb meem heterogeneous nco hauv koj qhov OpenCL system, hloov kho koj tus tswv code los ntawm kev ntxiv CL_MEM_HETEROGENEOUS_INTELFPGA chij rau koj clCreateBuffer hu.
   Rau example:
   ddatain = clCreateBuffer(cov ntsiab lus, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, sizeof(unsigned) * vectorSize, NULL, &status);
   Intel xav kom koj teeb qhov chaw tsis raws li cov lus sib cav ua ntej sau qhov tsis. Thaum siv ib lub cim xeeb thoob ntiaj teb, koj tuaj yeem sau cov buffers ua ntej lossis tom qab muab lawv rau cov lus sib cav kernel. Hauv heterogeneous nco systems, tus tswv tsev teeb tsa qhov chaw tsis ua ntej sau qhov tsis. Hauv lwm lo lus, tus tswv tsev yuav hu rau clSetKernelArgument muaj nuj nqi ua ntej hu rau clEnqueueWriteBuffer muaj nuj nqi.
   Hauv koj tus tswv tsev code, hu rau clCreateBuffer, clSetKernelArg, thiab clEnqueueWriteBuffer hu hauv qab no:
   ddatain = clCreateBuffer( ntsiab lus teb, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, sizeof(unsigned) * vectorSize, NULL, &status);
   … status = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (void*)&ddatain);
   … status = clEnqueueWriteBuffer(queue, ddatain, CL_FALSE, 0, sizeof(unsigned) * vectorSize,hdatain, 0, NULL, NULL);
   Lub ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file nthuav tawm ib qho kev txiav txim zoo sib xws ntawm cov haujlwm hu.
4.  Tom qab koj hloov kho boardtest.cl file thiab tus tswv code, sau tus tswv tsev thiab kernel code thiab txheeb xyuas lawv cov haujlwm.
   Thaum sau koj cov lej code, koj yuav tsum lov tes taw tawg-interleaving ntawm txhua lub cim xeeb los ntawm kev suav nrog - tsis muaj kev cuam tshuam kev xaiv hauv aoc hais kom ua.

Cov ntaub ntawv ntsig txog
Disabling Burst-Interleaving ntawm Ntiaj Teb Kev Nco (–tsis-interleaving )

1.5. Txheeb xyuas qhov kev ua haujlwm ntawm Koj Kev Nco Heterogeneous Qhov system
Txhawm rau kom ntseeg tau tias lub cim xeeb tsis zoo ua haujlwm tau zoo, tshem tawm CL_CONTEXT_COMPILER_MODE_INTELFPGA tus chij hauv koj tus tswv tsev code.
Hauv OpenCL systems nrog lub cim xeeb homogeneous, koj yuav tsum xaiv los teeb tsa CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 tus chij hauv koj tus tswv tsev code kom lov tes taw kev nyeem ntawv .aocx file thiab reprogramming ntawm FPGA. Teem lub CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 tus chij yog qhov muaj txiaj ntsig zoo thaum ua kom koj lub rooj tsavxwm los xyuas qhov kev ua haujlwm ntawm koj lub Platform Kev Cai yam tsis tau tsim cov phiaj xwm hauv pem teb thiab qhia cov cheeb tsam LogicLock™.
Nrog heterogeneous nco systems, lub runtime ib puag ncig yuav tsum nyeem qhov chaw tsis ntawm txhua qhov tsis, piav qhia hauv .aocx file, txhawm rau txheeb xyuas lub cim xeeb ua haujlwm. Txawm li cas los xij, tej zaum koj yuav xav txheeb xyuas qhov ua haujlwm ntawm koj qhov Kev Cai Platform yam tsis tau siv cov yam ntxwv kawg ntawm lub rooj tsavxwm tsim, xws li tsim cov phiaj xwm hauv pem teb thiab qhia cov cheeb tsam LogicLock.

1. Xyuas kom tseeb tias CL_CONTEXT_COMPILER_MODE_INTELFPGA tus chij tsis raug teeb tsa hauv koj tus tswv tsev code.
2. Xa mus rau lub rooj tsavxwm / /source/host/mmd directory of your Custom Platform.
3. Qhib acl_pcie_device.cpp nco-mapped ntaus ntawv (MMD) file hauv ib phau ntawv editor.
4.  Hloov kho qhov kev ua haujlwm reprogram hauv acl_pcie_device.cpp file los ntawm kev ntxiv rov qab 0; kab, raws li qhia hauv qab no:
   int ACL_PCIE_DEVICE::reprogram(void *data, size_t data_size)
   {
   rov 0;
   // xav tias ua tsis tiav
   int reprogram_failed = 1;
   // xav tias tsis muaj rbf lossis hash hauv fpga.bin
   int rbf_or_hash_not_provided = 1;
   // assume base thiab ntshuam kho hashes tsis phim
   int hash_mismatch = 1;
   …
   }
5. Recompile lub acl_pcie_device.cpp file.
6. Xyuas kom tseeb tias CL_CONTEXT_COMPILER_MODE_INTELFPGA tus chij tseem tsis tau teeb tsa.
   Nco ntsoov: Tom qab koj ntxiv rov qab 0; mus rau reprogram muaj nuj nqi thiab recompile MMD file, lub sijhawm ua haujlwm ib puag ncig yuav nyeem .aocx file thiab muab cov chaw tsis nyob tab sis yuav tsis reprogram FPGA. Koj yuav tsum manually phim cov duab FPGA nrog .aocx file. Txhawm rau thim tus cwj pwm no, tshem tawm rov qab 0; los ntawm kev ua haujlwm reprogram thiab rov ua dua MMD file.

1.6. Cov ntaub ntawv kho dua tshiab

Hnub tim	Version	Hloov
Dec-17	2017.12.01	• Rebranded CL_MEM_HETEROGENEOUS_ALTERA rau CL_MEM_HETEROGENEOUS_INTELFPGA.
Dec-16	2016.12.13	• Rebranded CL_CONTEXT_COMPILER_MODE_ALTERA rau CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Tsim Heterogeneous Memory Systems hauv Intel® FPGA SDK rau OpenCL
Kev cai Platforms
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Online Version
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PIB: 683654
Version: 2016.12.13

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intel Tsim Heterogeneous Memory Systems hauv FPGA SDK rau OpenCL Custom Platforms [ua pdf] Cov lus qhia Tsim Heterogeneous Memory Systems hauv FPGA SDK rau OpenCL Custom Platforms, Tsim Heterogeneous Memory Systems, FPGA SDK rau OpenCL Custom Platforms

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