Fausiaina o Faiga Fa'apitoa i le FPGA SDK mo OpenCL Custom Platforms
Faatonuga

Fausiaina o Faiga Fa'apitoa i le Intel® FPGA SDK mo OpenCL Custom Platforms

O le faʻatinoina o mafaufauga eseese i totonu o le Custom Platform e mafai ai ona sili atu le faʻaogaina o le memory interface (EMIF) faʻapea foʻi ma le tele ma le vave faʻaogaina o manatuaga. O le tu'ufa'atasiga o le fa'aogaina o manatuaga fa'atasi ma se fa'asilisili
OpenCL ™(1)kernel e mafai ona i'u ai i le fa'aleleia atili o fa'atinoga mo lau faiga OpenCL.
O lenei tusi talosaga o lo'o tu'uina atu ai le ta'iala i le fa'atupuina o faiga fa'amanatu eseese i totonu o se Fa'asinomaga Fa'apitoa mo le fa'aogaina ma le Intel® FPGA SDK mo OpenCL(2). O lo'o fa'apea Intel o oe o se fa'ata'ita'iga FPGA poto masani o lo'o atia'e Faiga Fa'asinomaga o lo'o iai faiga fa'amanatu eseese.
A'o le'i faia ni faiga fa'amanatu eseese, fa'amasani oe i le Intel FPGA SDK mo pepa OpenCL o lo'o fa'ailoa mai i lalo.
Fa'amatalaga Fa'atatau

• Intel FPGA SDK mo OpenCL Polokalama Taiala
• Intel FPGA SDK mo OpenCL Ta'iala Sili
• Intel FPGA SDK mo OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Fa'amaonia le Gaioiga a le Komiti Fa'atonu FPGA ma le EMIF Interfaces

Fa'amaonia ta'itasi fa'aoga fa'amanatuga ta'ito'atasi ona fa'atino loa lea o lau Custom Platform e fa'aoga ai le manatua o le lalolagi.

1. Fa'amaonia fa'aoga manatua ta'itasi e fa'aaoga ai masini fa'apitoa e mafai ona su'eina le saoasaoa ma le mautu o fa'aoga ta'itasi.
2. Fa'amatagofie lau Faiga Fa'apitoa e fa'aaoga ai le manatua o le lalolagi.
   1. Mo example, afai e tolu au fesoʻotaʻiga DDR, o se tasi oi latou e tatau ona faʻafanua o se manatuaga eseese. I lenei tulaga, fa'amaonia le fa'aogaina o le fa'aputuga OpenCL fa'atasi ai ma fa'aoga DDR ta'itasi.
      OpenCL ma le OpenCL logo o fa'ailoga tau fefa'ataua'iga a Apple Inc. fa'aaogaina i le fa'atagaga a le Khronos Group™ .
   2.  O le Intel FPGA SDK mo OpenCL e faʻavae i luga o se faʻasalalauga Khronos Faʻamatalaga, ma ua pasia le Khronos Conformance Testing Process. E mafai ona maua le tulaga o iai nei ile www.khronos.org/conformance.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.
ISO 9001:2015 Resitala
I le isi itu, afai e lua au fesoʻotaʻiga DDR ma tasi le faʻasologa o faʻamatalaga quad data (QDR), faʻamaonia le faʻaogaina o le faʻapipiʻi OpenCL o fesoʻotaʻiga DDR e lua ma le QDR faʻaoga tutoatasi.
Ua fautuaina e Intel e te fa'aogaina le PCI Express® – (PCIe® -) po'o le EMIF-fa'apitoa mamanu e su'e ai au feso'ota'iga manatua. A maeʻa ona e faʻamaonia o loʻo faʻaogaina taʻiala taʻitasi ma o lau OpenCL design e galue ma se vaega o fesoʻotaʻiga manatua, faʻaauau
e fa'atupuina ai se faiga fa'amanatu fa'apitoa e fa'atino atoatoa. 
1.2. Suia le board_spec.xml File
Suia le board_spec.xml file e fa'amaoti ai ituaiga o faiga fa'amanatu eseese o lo'o avanoa i fatu OpenCL.
I le taimi o le tu'ufa'atasiga o fatu, o le Intel FPGA SDK mo OpenCL Offline Compiler e tu'uina atu ai finauga o fatu i se manatua e fa'avae i luga o le fa'aupuga o le nofoaga fa'amaufa'ailoga e te fa'amaoti mai.
1. Su'e ile board_spec.xml file i le lisi o meafaigaluega a lau Custom Platform.
2. Tatala le board_spec.xml file i totonu o se fa'atonu tusitusiga ma suia le XML e tusa ai.
Mo example, afai o lau masini komepiuta e lua DDR manatua o le faaletonu o le globalmemory ma lua QDR faletupe e te faʻataʻitaʻiina e pei o mafaufauga eseese, sui vaega manatua o le board_spec.xml file e pei o mea nei:
















1.3. Fa'atūina le tele o mea e va'ava'ai i le Qsys
I le taimi nei, o le OpenCL Memory Bank Divider i le Qsys design e le lagolagoina le leai o le mana-o-2 numera o faletupe manatua, e le o se tapulaʻa mo faʻasalalauga masani. Ae ui i lea, o loʻo i ai faʻataʻitaʻiga e le mana-o-2 numera o fesoʻotaʻiga manatua e manaʻomia. Ina ia fa'aogaina le numera e le o le mana-o-2 o feso'ota'iga manatua, fa'aaoga le tele o OpenCL Memory Bank Dividers e fa'atupu ai faiga fa'amanatu eseese ma numera e le-mana-o-2 o faletupe manatua. E tatau ona e fatuina le tele o OpenCL Memory Bank Dividers pe a iai sau faʻaoga faʻaogaina moni. Mafaufau i se faiga e tasi le DDR memory interface ma le QDR memory interface. Talu ai ona o faletupe e lua e eseese mafaufauga faʻapitoa, e le mafai ona e tuʻufaʻatasia i lalo o se manatuaga lalolagi e tasi.
Ata 1. Fa'ailoga poloka o se Tolu-Bank Heterogenous Memory System
O lenei faiga e manatua ai mea eseese e aofia ai fesoʻotaʻiga faʻamaufaʻailoga DDR e lua ma le tasi QDR faʻaoga faʻaoga.Afai o lo'o e fa'aogaina le version 16.0, 16.0.1, po'o le 16.0.2 o le Intel Quartus® Prime software ma le Altera SDK mo OpenCL, o le OpenCL Memory Bank Divider o lo'o fa'agasolo sese le fa'aogaina o manatuaga i tua'oi o tuatusi. Ina ia galue i lenei faʻamatalaga lauiloa, faʻaopoopo se alalaupapa paipa ma le paʻu o le 1 ma faʻafesoʻotaʻi lona Avalon ®Memory-Mapped (Avalon-MM) matai i le OpenCL Memory Bank Divider's slave port.
Fa'aaliga:
O lenei faʻamatalaga lauiloa o loʻo faʻamauina i le Intel Quartus Prime software ma le Intel FPGA SDK mo OpenCL version 16.1.
Ata 2. Fa'ata'otoga poloka o le tolu-Bank Heterogenous Memory System ma se Alalaupapa Paipa. 1.4. Suia le Polokalama Su'ega a le Komiti Fa'atonu ma le Fa'ailoga Fa'atonu mo lau Fofo Fa'amafaufau Eseese
Fa'aoga le fatu o le boardtest.cl e sau ma le Intel FPGA SDK mo OpenCL Custom Platform Toolkit e fa'ata'ita'i ai le fa'atinoga ma le fa'atinoga o lau Custom Platform.
O le polokalame su'ega a le laupapa o le OpenCL kernel e mafai ai ona e su'eina le bandwidth host-to-device, bandwidth memory, ma galuega lautele o lau Custom Platform.

1. Su'e ile /board/ custom_platform_toolkit/tests/boardtest directory.
2. Tatala le boardtest.cl file i totonu o se tusitala tusitusiga ma tuʻuina atu se nofoaga faʻapipiʻi i finauga taʻitasi i le lalolagi atoa.
   Mo exampLe:
   __gaogao gaogao
   mem_stream (__global__attribute__((buffer_location(“DDR”))) uint *src, __global __attribute__((buffer_location(“QDR”))) uint *dst, uint arg, uint arg2)
   O iinei, uint *src ua tofia i le DDR memory, ma uint *dst ua tofia i QDR memory. O le board_spec.xml file o lo'o fa'amaoti mai uiga o faiga fa'amanatu e lua.
3. Ina ia fa'aogaina lau tali fa'amanatu eseese i lau OpenCL system, sui lau code host e ala i le fa'aopoopoina o le fu'a CL_MEM_HETEROGENEOUS_INTELFPGA i lau telefoni clCreateBuffer.
   Mo exampLe:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, lapopo'a(e le'i fa'ailoga) * VectorSize, NULL, &tulaga);
   E fautuaina malosi e Intel e te setiina le nofoaga faʻapipiʻi e fai ma finauga o fatu aʻo leʻi tusia le pa. Pe a faʻaaogaina se mafaufauga faʻalelalolagi e tasi, e mafai ona e tusia le paʻu aʻo leʻi tuʻuina atu pe a maeʻa ona tuʻuina atu i se finauga kernel. I faiga fa'amanatu eseese, e fa'atulaga e le 'au'aunaga le nofoaga pa'u a'o le'i tusia le pa'u. I se isi faaupuga, o le a valaʻau e le talimalo le galuega clSetKernelArgument aʻo leʻi valaʻau le galuega clEnqueueWriteBuffer.
   I lau code host, valaʻau le clCreateBuffer, clSetKernelArg, ma le clEnqueueWriteBuffer valaau i le faasologa lenei:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, lapopo'a(e le'i fa'ailoga) * VectorSize, NULL, &tulaga);
   … tulaga = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (void*)&ddatain);
   … tulaga = clEnqueueWriteBuffer(queue, ddatain, CL_FALSE, 0, sizeof(le saini) * vectorSize,hdatain, 0, NULL, NULL);
   Le ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file o lo'o tu'uina mai ai se fa'asologa tutusa o nei vala'au galuega.
4.  A uma ona e suia le boardtest.cl file ma le code host, tuufaatasia le host ma kernel code ma faʻamaonia a latou galuega.
   A faʻapipiʻi lau kernel code, e tatau ona e faʻamalo le faʻaogaina o mea uma e manatua e ala i le aofia ai o le -no-interleaving. filifiliga i le aoc poloaiga.

Fa'amatalaga Fa'atatau
Fa'ate'a le Burst-Interleaving of Global Memory (–leai se interleaving )

1.5. Fa'amaonia le Fa'atinoga o Lau Fa'amanatuga Eterogene Faiga
Ina ia mautinoa o lo'o fa'agaoioi lelei le faiga o manatuaga eseese, aveese le fu'a CL_CONTEXT_COMPILER_MODE_INTELFPGA i lau code host.
I faiga OpenCL ma manatua tutusa, e tatau ona e filifili e seti le CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 fuʻa i lau code talimalo e faʻamalo le faitau o le .aocx file ma le toe polokalame o le FPGA. Fa'atulaga le CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 fu'a e aoga pe a fa'atonu lau laupapa e fa'amaonia le fa'atinoga o lau Custom Platform e aunoa ma le fa'atulagaina o le fola ma fa'amaoti vaega LogicLock™.
Fa'atasi ai ma faiga fa'amanatu eseese, e tatau i le si'osi'omaga taimi ta'avale ona faitau nofoaga fa'amau o fa'amau ta'itasi, fa'amatala i le .aocx. file, e fa'amaonia le fa'aogaina o faiga fa'amanatu. Ae ui i lea, atonu e te manaʻo e faʻamaonia le faʻaogaina o lau Custom Platform e aunoa ma le faʻatinoina o vaega mulimuli o le mamanu o le laupapa, e pei o le mamanuina o le fola o le fale ma faʻamaonia le LogicLock itulagi.

1. Fa'amaonia o le fu'a CL_CONTEXT_COMPILER_MODE_INTELFPGA e le'i setiina i lau code host.
2. Su'e ile laupapa/ /source/host/mmd directory o lau Custom Platform.
3. Tatala le acl_pcie_device.cpp masini fa'afanua manatua (MMD) file i se fa'atonu tusitusiga.
4.  Suia le galuega reprogram i le acl_pcie_device.cpp file e ala i le faʻaopoopoina o se faʻafouga 0; laina, e pei ona faʻaalia i lalo:
   int ACL_PCIE_DEVICE::toe fa'apolokalame(fa'amavae *fa'amatalaga, size_t data_size)
   {
   toe fo'i 0;
   // manatu ua toilalo
   int reprogram_failed = 1;
   // manatu e leai se rbf poʻo le hash i fpga.bin
   int rbf_or_hash_not_provided = 1;
   // manatu fa'avae ma fa'aulufale mai fa'ailoga fa'ailoga e le fetaui
   int hash_mismatch = 1;
   …
   }
5. Toe fa'aopoopo le acl_pcie_device.cpp file.
6. Fa'amaonia o le fu'a CL_CONTEXT_COMPILER_MODE_INTELFPGA o lo'o tumau pea le le setiina.
   Fa'alogo: A mae'a ona e fa'aopoopo le toe fo'i 0; i le galuega toe faʻatulagaina ma toe faʻapipiʻi le MMD file, o le a faitau le siosiomaga runtime le .aocx file ma atofa nofoaga fa'apolopolo ae le toe fa'apolokalame le FPGA. E tatau ona e fa'afetaui ma le lima le ata FPGA ma le .aocx file. Ina ia fesuiai lenei amio, aveese le toe faafoi 0; mai le galuega reprogram ma toe tuufaatasia le MMD file.

1.6. Fa'amatalaga Toe Iloiloga o Fa'amaumauga

Aso	Fa'aliliuga	Suiga
Tes-17	2017.12.01	• Toe fa'ailoga CL_MEM_HETEROGENEOUS_ALTERA i CL_MEM_HETEROGENEOUS_INTELFPGA.
Tes-16	2016.12.13	• Toe fa'ailoga CL_CONTEXT_COMPILER_MODE_ALTERA i CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Fausiaina o Faiga Fa'aleagaga i Intel® FPGA SDK mo OpenCL
Faiga Fa'apitoa
Lauina Manatu
Faʻasinomaga Faʻainitaneti
Lauina Manatu
ID: 683654
Fa'aliliuga: 2016.12.13

Pepa / Punaoa

intel Fausiaina Faiga Fa'amanatuga Eterogene i le FPGA SDK mo OpenCL Custom Platforms [pdf] Faatonuga Fausiaina o Faiga Fa'apitoa i le FPGA SDK mo OpenCL Custom Platforms, Fa'atupuina o Fa'atonuga Fa'atonu, FPGA SDK mo OpenCL Custom Platforms.

Fa'asinomaga

• Tusi Taiala