MICROCHIP H.264 Encoder
Nhanganyaya
H.264 inofarirwa mavhidhiyo ekutsikirira chiyero chedhijitari vhidhiyo. Iyo inozivikanwa zvakare seMPEG-4 Part10 kana Yepamberi Vhidhiyo Coding (MPEG-4 AVC). H.264 inoshandisa block-wise nzira yekudzvanya vhidhiyo apo saizi yebhuroko inotsanangurwa se 16 x 16 uye inonzi macro block. Iyo compression standard inotsigira akasiyana profiles inotsanangura chiyero chekumanikidza uye kuoma kwekuita. Mafuremu evhidhiyo, ekumanikidzwa, anobatwa senge ini, P furemu, uye B furemu. An I furemu intra-coded furemu uko kudzvanya kunoitwa nekushandisa ruzivo rwuri mukati mefuremu. Hapana mamwe mafuremu anodiwa kuti adecode I furemu. AP furemu inomanikidzwa nekushandisa shanduko neruremekedzo kune yekutanga furemu inogona kuve I furemu kana P furemu. Kutsikirirwa kweB furemu kunoitwa nekushandisa shanduko yekufamba neruremekedzo kune ese ekutanga furemu uye inouya furemu.
Iyo I uye P furemu yekumanikidza maitiro ine ina stages:
- Intra/Inter kufanotaura
- Integer shanduko
- Quantization
- Entropy encoding
H. 264 inotsigira marudzi maviri ekukodha:
- Context Adaptive Variable Length Coding (CAVLC)
- Context Adaptive Binary Arithmetic Coding (CABAC)
Iyo yazvino vhezheni yeH.264 Encoder inoshandisa baseline profile uye inoshandisa CAVLC ye entropy encoding. Zvakare, H.264 Encoder inotsigira kukodha kwemafuremu I neP.
Mufananidzo 1. H.264 Encoder Block Diagram
Features
H. 264 Encoder ine zvinotevera zvakakosha maficha:
- Inodzvanya YCbCr 420 vhidhiyo fomati
- Inogamuchira YCbCr 422 vhidhiyo fomati sekuisa
- Inotsigira 8-bit kune chimwe nechimwe chikamu (Y, Cb, uye Cr)
- Inotsigira ITU-T H.264 Annex B inoenderana neNAL byte kubuda
- Inoshanda pasina yakamira kushanda, CPU, kana processor rubatsiro kwete Inodiwa
- Inotsigira mushandisi configurable Quality Factor (QP)
- Inotsigira P Frame Count (PCOUNT)
- Inotsigira mushandisi inogadziriswa pachikumbaridzo kukosha kweskip block
- Inotsigira computation pachiyero chepixel imwe pawachi
- Inotsigira kudzvanya kusvika pakugadziriswa kwe1080p 60 fps
- Inoshandisa vhidhiyo arbiter interface yekuwana DDR furemu buffers
- Minimal latency (252 µs yeHD yakazara kana mitsara 17 yakachinjika)
Mhuri Dzakatsigirwa
H. 264 Encoder inotsigira zvinotevera zvigadzirwa mhuri:
- PolarFire® SoC
- PolarFire
Hardware Implementation
Ichi chikamu chinotsanangura akasiyana emukati mamodules eH.264 Encoder. Kuiswa kwedata kuH.264 Encoder kunofanirwa kunge kuri kwemufananidzo we raster scan muYCbCr 422 fomati. H.264 Encoder inoshandisa mafomati 422 sekuisa uye inoshandisa kudzvanya mumafomati 420.
Nhamba inotevera inoratidza H.264 Encoder block diagram.
Mufananidzo 1-1. H.264 Encoder – Modules
- Intra Prediction
H.264 inoshandisa dzakasiyana-siyana intra-prediction modes kuderedza ruzivo mu 4 x 4 block. Iyo intra-prediction block muIP inoshandisa chete DC kufanotaura pane 4 x 4 matrix saizi. Iyo DC chikamu chinoverengerwa kubva padyo kumusoro uye kuruboshwe 4 x 4 zvidhinha. - Integer Shanduko
H.264 inoshandisa integer discrete cosine shanduko panogoverwa macoefficients pane integer transform matrix uye quantization matrix zvekuti hapana kuwanda kana kupatsanurwa mukushandurwa kweinhamba. Nhamba inoshandura stage inoshandisa shanduko uchishandisa shift uye kuwedzera mashandiro. - Quantization
Iyo quantization inowanza yega yega inobuda yeinhamba yeshanduko ine predetermined quantization kukosha kunotsanangurwa neQP mushandisi wekuisa kukosha. Nhamba ye QP kukosha inobva ku0 kusvika 51. Chero kukosha kudarika 51 ndiko clamped kusvika 51. Yakaderera QP kukosha inoreva kudzvanya kwakaderera uye mhando yepamusoro uye zvakasiyana. - Motion Estimation
Iyo Motion Estimation inotsvaga 8 x 8 block yeiyo furemu yazvino mu 16 x 16 block yeyapfuura furemu uye inogadzira mafambiro mavector. - Motion Muripo
Iyo Motion muripo inowana mafambiro mavector kubva kuMotion Estimation block uye inowana inoenderana 8 x 8 block mune yapfuura furemu. - CAVLC
H.264 inoshandisa marudzi maviri eentropy encoding-CAVLC neCABAC. Iyo IP inoshandisa CAVLC yekukodha iyo quantized inobuda. - Musoro jenareta
Iyo yemusoro jenareta block inogadzira iyo block headers, iyo chidimbu misoro, iyo Sequence Parameter Set (SPS), iyo Mufananidzo Parameter Set (PPS), uye Network Abstraction Layer (NAL) unit zvichienderana nemuenzaniso wevhidhiyo furemu. Skip block decision logic inoverenga Sum yeAbsolute Difference (SAD) yezvino furemu 16 x 16 macro block uye iyo yapfuura furemu 16 x 16 macro block kubva kune inofamba vector yakafanotaurwa nzvimbo. Iyo skip block inosarudzwa uchishandisa iyo SAD kukosha uye iyo SKIP_THRESHOLD yekuisa. - H.264 Stream Jenareta
H.264 stream generator block inosanganisa CAVLC inobuda pamwe chete nemusoro kuti igadzire encoded inobuda maererano neH.264 standard format. - DDR Nyora Chiteshi uye Verenga Chiteshi
H.264 Encoder inoda kuti decoded frame ichengetwe muDDR memory, iyo inoshandiswa muInter prediction. The
IP inoshandisa DDR kunyora uye kuverenga zviteshi kuti ibatanidze neVhidhiyo Arbiter IP, iyo inodyidzana neDDR ndangariro kuburikidza neDDR controller IP.
Zvinopinza uye Zvinobuda
Ichi chikamu chinotsanangura zvinopinda uye zvinobuda zveH.264 Encoder.
Ports
Matafura anotevera anoronga tsananguro yezvipimo uye zviteshi zvekubuda zveH.264 Encoder.
Tafura 2-1. Zvinopinza uye Zvinobuda zveH.264 Encoder
| Zita rechiratidzo | Direction | Upamhi | Tsanangudzo |
| DDR_CLK_I | Input | 1 | DDR memory controller wachi |
| PIX_CLK_I | Input | 1 | wachi yekuisa iyo mapixels anouya ari sampled |
| RESET_N | Input | 1 | Active-low Asynchronous reset chiratidzo kune dhizaini |
| DATA_VALID_I | Input | 1 | Isa Pixel data siginecha inoshanda |
| DATA_Y_I | Input | 8 | 8-bit Luma pixel kuiswa mune 422 fomati |
| DATA_C_I | Input | 8 | 8-bit Chroma pixel yekupinda mune 422 fomati |
|
FRAME_START_I |
Input |
1 |
Kutanga kwe Frame chiratidzo
Mupendero unokwira wechiratidzo ichi unoonekwa sekutangisa kwefuremu. |
| FRAME_END_I | Input | 1 | End of Frame chiratidzo |
|
DDR_FRAME_START_ADDR_I |
Input |
8 |
DDR ndangariro yekutanga kero (LSB 24-bits ari 0) kuchengetedza iyo yakagadziridzwa furemu. H.264 IP ichachengeta mafuremu mana uye ichashandisa 4 MB yeDDR memory. |
| I_FRAME_FORCE_I | Input | 1 | Mushandisi anogona kumanikidza kuti ini ndigadzire chero nguva. Icho chiratidzo chepulse. |
|
PCOUNT_I |
Input |
8 |
Nhamba yeP mafuremu pane yega yega I frame 422 fomati ukoshi hunotangira pa0 kusvika 255. |
|
QP |
Input |
6 |
Hunhu hweH.264 quantization 422 fornat value inotangira pa0 kusvika 51 apo 0 inomiririra zvemhando yepamusoro uye kutsikirira kwakaderera uye 51 inomiririra kudzvanya kwepamusoro. |
|
SKIP_THRESHOLD_I |
Input |
12 |
Chikumbaridzo cheskip block sarudzo
Kukosha uku kunomiririra kukosha kweSAD ye16 x 16 Macro block yekusvetuka. Rudzi urwu runobva pa0 kusvika pa1024, ine kukosha kwakajairika kwe 512. Chikumbaridzo chepamusoro chinoburitsa mamwe ma skip blocks uye yakaderera mhando. |
| VRES_I | Input | 16 | Kugadziriswa kwemufananidzo wekupinda. Inofanira kuva yakawanda ye16. |
| HRES_I | Input | 16 | Horizontal resolution yemufananidzo wekupinda. Inofanira kuva yakawanda ye16. |
| DATA_VALID_O | Output | 1 | Chiratidzo chinoratidza data yakavharwa inoshanda. |
|
DATA_O |
Output |
16 |
H.264 encoded data output ine NAL unit, slice header, SPS, PPS, uye encoded data of macro blocks. |
|
WRITE_ CHANNEL_BUS |
— |
— |
Nyora chiteshi bhazi kuti ubatanidzwe neVhidhiyo arbiter Nyora chiteshi bhazi. Izvi
inowanikwa kana iyo bhazi interface yasarudzirwa Arbiter Interface. |
|
VERENGA_CHANNEL_BUS |
— |
— |
Verenga chiteshi bhazi kuti ubatanidzwe neVhidhiyo arbiter Verenga chiteshi bhazi. Izvi
inowanikwa kana iyo bhazi interface yasarudzirwa Arbiter Interface. |
| DDR Nyora Native IF-Aya madoko anowanikwa kana iyo Native interface yasarudzwa yeArbiter Interface. | |||
| DDR_WRITE_ACK_I | Input | 1 | Nyora kubvuma kubva kune arbiter kunyora chiteshi. |
| DDR_WRITE_DONE_I | Input | 1 | Nyora kupedzisa kubva kune arbiter. |
| DDR_WRITE_REQ_O | Output | 1 | Nyora chikumbiro kune arbiter. |
| DDR_WRITE_START_ADDR_O | Output | 32 | DDR kero panofanira kunyorerwa. |
| DDR_WBURST_SIZE_O | Output | 8 | DDR nyora kuputika saizi. |
| DDR_WDATA_VALID_O | Output | 1 | Data inoshanda kune arbiter. |
| DDR_WDATA_O | Output | DDR_AXI_DATA_WIDTH | Kuburitsa data kune arbiter. |
| DDR Read Native IF-Aya madoko anowanikwa kana iyo Native interface yasarudzwa yeArbiter Interface. | |||
| DDR_READ_ACK_I | Input | 1 | Verenga kubvuma kubva kune arbiter kuverenga chiteshi. |
| DDR_READ_DONE_I | Input | 1 | Verenga kupedzisa kubva kune arbiter. |
| DDR_RDATA_VALID_I | Input | 1 | Data inoshanda kubva kune arbiter. |
| DDR_RDATA_I | Input | DDR_AXI_DATA_WIDTH | Kuiswa kwedata kubva kune arbiter. |
| DDR_READ_REQ_O | Output | 1 | Verenga chikumbiro kune arbiter. |
| DDR_READ_START_ADDR_O | Output | 32 | DDR kero panofanira kuverengerwa. |
| DDR_RBURST_SIZE_O | Output | 8 | DDR kuverenga kuputika saizi. |
Clock Constraints
Iyo H.264 Encoder IP inoshandisa PIX_CLK_I uye DDR_CLK_I inoisa wachi. Shandisa zvipingamupinyi zvemapoka ewachi yenzvimbo uye nzira uye simbisa nguva sezvo IP inoshandisa wachi domain crossing logic.
Installation Instructions
H. 264 Encoder core inofanira kuiswa kuIP Catalog yeLibero® SoC software. Izvi zvinoitwa otomatiki kuburikidza neiyo IP Catalog yekuvandudza basa muLibero SoC software, kana iyo IP musimboti inogona kutorwa nemaoko kubva kukhathalogi. Kana iyo IP musimboti yaiswa muLibero SoC software IP Catalog, musimboti unogona kugadzirwa, kugadzirwa, uye nekumisikidzwa mukati meSmartDesign kuti ibatanidzwe muLibero purojekiti.
Testbench
Testbench inopiwa kutarisa kushanda kweH.264 Encoder IP.
- Simulation
Iyo simulation inoshandisa 432 × 240 mufananidzo muYCbCr422 fomati inomiririrwa nembiri. files, imwe neimwe yeY uye C sekuisa
uye inogadzira H.264 file fomati ine mafuremu maviri. Matanho anotevera anotsanangura maitiro ekutevedzera musimboti uchishandisa testbench.- Enda kuLibero SoC Catalog > View > Windows > Catalog, uye wobva wawedzera Solutions-Vhidhiyo. Tinya kaviri H264_Encoder, wobva wadzvanya OK.
- Kuti ugadzire inodiwa SmartDesign yeH.264 Encoder IP simulation, baya Libero Project > Execute script. Bhurawuza kune zvinyorwa ..\ \ chikamu\Microchip\SolutionCore\H264_Encoder\ \scripts\H264_SD.tcl, wobva wadzvanya Mhanya .
Mufananidzo 5-2. Enza Script Run
The default AXI data bus width is 512. Kana H.264 Encoder IP yakagadzirirwa 256/128 bhazi upamhi, nyora AXI_DATA_WIDTH:256 kana AXI_DATA_WIDTH:128 mundima yeNharo.
Iyo SmartDesign inooneka. Ona mufananidzo unotevera.
Mufananidzo 5-3. Pamusoro SmartDesign
- On the Files tab, tinya simulation> Import Files.
Mufananidzo 5-4. Import Files
- Enza iyo H264_sim_data_in_y.txt, H264_sim_data_in_c.txt file uye H264_sim_refOut.txt file kubva munzira inotevera: ..\ \ chikamu\Microchip\SolutionCore\H264_Encoder\ \Stimulus.
- Kupinza zvakasiyana file, tsvaga folda ine zvinodiwa file, wobva wadzvanya Open. The imported file yakanyorwa pasi pekufananidza, ona mufananidzo unotevera.
- Pa Stimulus Hierarchy tab, baya H264_Encoder_tb (H264_Encoder_tb. v) > Simulate Pre-Synth Design > Vhura Interactively. IP inofananidzwa nemafuremu maviri. Mufananidzo 5-6. Simulating Pre-Synthesis Dhizaini
ModelSim inotanga ne testbench file sezvinoratidzwa mumufananidzo unotevera.
- Enda kuLibero SoC Catalog > View > Windows > Catalog, uye wobva wawedzera Solutions-Vhidhiyo. Tinya kaviri H264_Encoder, wobva wadzvanya OK.
Zvakakosha: Kana iyo simulation ikakanganiswa nekuda kwekumhanya nguva yakatarwa inotsanangurwa muDO file, shandisa run -all command kupedzisa simulation.
Resource Utilization
H. 264 Encoder inoshandiswa muPolarFire SoC FPGA (MPFS250T-1FCG1152I package) uye inogadzira data yakamanikidzwa nekushandisa 4:2:2 s.ampnguva yedata rekuisa.
Tafura 6-1. Resource Utilization for H.264 Encoder
| Resource | Usage |
| 4 Kutarisa-Up Tables (LUTs) | 69092 |
| D Flip Flops (DFFs) | 65522 |
| Static Random Access Memory (LSRAM) | 232 |
| ISRAM | 30 |
| Math blocks | 19 |
| Interface 4-inopinza LUTs | 9396 |
| Interface DFFs | 9396 |
Configuration Parameters
Tafura inotevera inonyora tsananguro yezvigadziro zvekugadzirisa zvigadziriswe zvinoshandiswa mukugadzirisa hardware yeH.264 Encoder, iyo inogona kusiyana zvichienderana nezvinodiwa zvekushandisa.
Tafura 7-1. Configuration Parameters
| Zita | Tsanangudzo |
| DDR_AXI_DATA_WIDTH | Inotsanangura iyo DDR AXI data upamhi. Inogona kuva 128, 256, kana 512 |
| ARBITER_INTERFACE | Sarudzo yekusarudza iyo yemuno kana yebhazi interface yekubatanidza nevhidhiyo arbiter IP |
IP Configurator
Nhamba inotevera inoratidza H.264 Encoder IP configuarator.
Mufananidzo 7-1. H.264 Encoder Configurator
License
H. 264 Encoder inopiwa mufomu yakavharidzirwa chete pasi perezinesi.
Encrypted RTL source code ndeye rezinesi-yakakiiwa uye inofanirwa kutengwa zvakasiyana. Iwe unogona kuita simulation, synthesis, dhizaini, uye kuronga iyo Field Programmable Gate Array (FPGA) silicon uchishandisa Libero dhizaini suite.
Rezinesi rekuongorora rinopihwa mahara kuti utarise maficha eH.264 Encoder. Rezinesi rekuongorora rinopera mushure mekushandiswa kweawa pane Hardware.
Revision History
Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
Tafura 9-1. Revision History
| Kudzokorora | Date | Tsanangudzo |
| B | 09/2022 | • Updated Features chikamu.
• Yakagadziridza hupamhi hweDATA_O inobuda chiratidzo kubva pa8 kusvika ku16, ona Tafura 2-1. • Updated Mufananidzo 7-1. • Updated 8. Rezinesi chikamu. • Updated 6. Resource Utilization chikamu. • Updated Mufananidzo 5-3. |
| A | 07/2022 | Kusunungurwa kwekutanga. |
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RUZIVO IYI INOPIWA NE MICROCHIP "SESE ZVIRI". MICROCHIP HAIITA ZVINOmiririrwa KANA KUTI MWARATIDZO YERUPI RWERUDZI ZVINO ZVINOTAURA KANA ZVINOREVA, KUNYORA KANA KUTAURA, ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINO zvinosanganisira ASI ZVISI ZVINOGWADZIRWA KUTI ZVINO ZVINOREVA KUTI ZVINOTAURWA KUTI ZVINOTAURWA, ZVINOTAURWA, ZVINOTAURWA, ZVINOTAURWA. KUNE CHINANGWA CHAKATADZWA, KANA KUTI MAWARANTI ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVICHAITWA NEZVINHU ZVAKAITWA, HUNHU, KANA KUITA.
HAPANA CHIITIKO CHICHAITWA MICROCHIP KUNE MHOSVA DZEPI ZVIRI KUNHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU , ZVINHU , ZVINOITWA , ZVAKAITIKA , KANA ZVINOTEVERA KURASIKA , KUPARADZWA , MUTEMO , KANA KUTI KUTI MUTE CHESE ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINO KANA MASHANDISI AWO, ZVISINEI ZVAKAITWA MAZANO ZVINOGONA KANA KUKABADZA ZVINOFONEKWA. ZVINO ZVIKURU ZVINOBVUNZWA NEMUTEMO, MICROCHIP YAKATAURWA YOSE PAZVINOITWA ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISA KWAKO HAKUZOPIRI MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINHU ZVINOITWA NERUZIVO KANA KUSHANDISWA KWAKO HAKUZOPFUURA MUNHU WEMURIPO, KANA UCHIDA, WAWAKABHADHARA ZVINHU ZVINO KUNYANYA KUTI MICROCHIP.
Kushandiswa kweMicrochip zvishandiso mukutsigira hupenyu uye / kana kuchengetedza zvikumbiro zviri panjodzi yemutengi, uye mutengi anobvuma kudzivirira, kubhadharira uye kubata Microchip isingakuvadzi kubva kune chero uye zvese zvinokuvadza, zvirevo, masutu, kana mari inokonzerwa nekushandiswa kwakadaro. Hapana marezinesi anofambiswa, zviri pachena kana neimwe nzira, pasi peMicrochip intellectual property rights kunze kwekunge zvataurwa neimwe nzira.
Trademarks
Iyo Microchip zita uye logo, iyo Microchip logo, Adaptec, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXTouchlus MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetri , SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, uye XMEGA zviratidzo zvakanyoreswa zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, neZL zvikwangwani zvakanyoreswa zveMicrochip Technology Incorporated muU.SA.
A
djacent Key Suppression, AKS, Analog-for-the-Digital Age, Chero Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, Clockstudio, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDMrage Avenet. , DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, IntelliMOS, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, KoD, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX , RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-IS, storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, Trusted Time, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, uye ZENA zviratidzo zveMicrochip Technology Incorporated muUSA nedzimwe nyika.
SQTP chiratidzo chesevhisi cheMicrochip Technology Incorporated muUSA
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, neSymmcom zviratidzo zvekutengeserana zveMicrochip Technology Inc. kune dzimwe nyika.
GestIC ichiratidzo chekutengeserana chakanyoreswa cheMicrochip Technology Germany II GmbH & Co. KG, inotsigira Microchip Technology Inc., kune dzimwe nyika.
Mamwe matrademark ese ataurwa pano zvinhu zvemakambani avo.
© 2022, Microchip Technology Incorporated nemakambani ayo. All Rights Reserved.
ISBN: 978-1-6683-1311-4
Quality Management System
Kuti uwane ruzivo nezve Microchip's Quality Management Systems, ndapota shanya www.microchip.com/quality.
Munyika Yose Kutengesa uye Basa
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