Kugadzira Heterogeneous Memory Systems muFPGA SDK yeOpenCL Tsika Platform
Mirayiridzo

Kugadzira Heterogeneous Memory Systems muIntel® FPGA SDK yeOpenCL Custom Platforms

Kuitwa kweheterogeneous memory muCustom Platform inobvumira mamwe ekunze memory interface (EMIF) bandwidth pamwe nekukura uye nekukurumidza ndangariro kupinda. Iko kusanganiswa kweheterogenous memory yekuwana neyakagadziridzwa
OpenCL ™ (1) kernel inogona kukonzera kuvandudzwa kwekuita kweOpenCL system yako.
Ichi chinyorwa chekunyorera chinopa gwara rekugadzira heterogeneous memory masisitimu muCustom Platform yekushandisa neIntel® FPGA SDK yeOpenCL(2). Intel inofungidzira kuti iwe uri mugadziri weFPGA ane ruzivo ari kugadzira Tsika Platforms ine heterogeneous memory system.
Usati wagadzira iyo heterogeneous memory masisitimu, zijaira iwe neIntel FPGA SDK yeOpenCL zvinyorwa zvinotsanangurwa pazasi.
Related Information

• Intel FPGA SDK ye OpenCL Programming Guide
• Intel FPGA SDK yeOpenCL Yakanyanya Maitiro Ekushandisa
• Intel FPGA SDK ye OpenCL Arria 10 GX FPGA Development Kit Reference Platform Porting Guide

1.1. Kuongorora Basa reFPGA Board uye EMIF Interfaces

Simbisa imwe neimwe yekurangarira interface yakazvimirira uye wobva wasimbisa yako Yetsika Platform uchishandisa ndangariro yepasirese.

1. Simbisa imwe neimwe yekurangarira interface uchishandisa Hardware dhizaini inogona kuyedza kumhanya uye kugadzikana kweimwe neimwe interface.
2. Simbisa yako Yetsika Platform uchishandisa ndangariro yepasirese.
   1. For example, kana iwe uine matatu DDR interfaces, imwe yacho inofanirwa kuve yakadhindwa senge heterogeneous memory. Muchiitiko ichi, simbisa mashandiro eOpenCL stack neimwe DDR interface yakazvimirira.
      OpenCL nelogo yeOpenCL zviratidzo zveApple Inc. zvinoshandiswa nemvumo yeKhronos Group™ .
   2.  Iyo Intel FPGA SDK yeOpenCL yakavakirwa pane yakaburitswa Khronos Specification, uye yakapfuura iyo Khronos Conformance Yekuyedza Maitiro. Ikozvino kuenderana mamiriro anogona kuwanikwa pa www.khronos.org/conformance.

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.
ISO 9001:2015 Yakanyoreswa
Neimwe nzira, kana uine maviri DDR interfaces uye imwe quad data rate (QDR) interface, simbisa mashandiro eOpenCL stack yeaviri DDR interface uye QDR interface yakazvimirira.
Intel inokurudzira kuti ushandise PCI Express® - (PCIe® -) kana EMIF-yakasarudzika madhizaini kuti uedze nzvimbo dzako dzekurangarira. Mushure mekuona kuti imwe neimwe yekurangarira inoshanda uye kuti dhizaini yako yeOpenCL inoshanda nechikamu chememory interface, enderera.
kugadzira inoshanda zvizere heterogeneous memory system. 
1.2. Kugadzirisa board_spec.xml File
Shandura board_spec.xml file kutsanangura marudzi eheterogeneous memory masisitimu anowanikwa kune OpenCL kernels.
Munguva yekubatanidza kernel, iyo Intel FPGA SDK yeOpenCL Offline Compiler inopa kernel nharo kundangariro zvichibva pane buffer nzvimbo nharo yaunotsanangura.
1. Bhurawuza kuboard_spec.xml file mune hardware dhairekitori yeCustom yako Platform.
2. Vhura board_spec.xml file mune chinyorwa edhita uye shandura iyo XML zvinoenderana.
For exampuye, kana system yako yehardware iine DDR mbiri sememory yepasi rose uye mabhangi maviri eQDR aunotevedzera seyeuko dzakasiyana, shandura ndangariro dzebhodhi_spec.xml file kufanana nezvinotevera:
















1.3. Kumisikidza Multiple Memory Dividers muQsys
Parizvino, iyo OpenCL Memory Bank Divider muQsys dhizaini haitsigire isiri-simba-ye-2 nhamba yemabhangi ekurangarira, izvo zvisiri izvo zvinogumira kune zvakajairwa zvigadziriso. Nekudaro, pane zviitiko apo isiri-simba-ye-2 nhamba yendangariro yekusangana inodiwa. Kuti ugamuchire asiri-simba-e-2 nhamba yekurangarira, shandisa akawanda OpenCL Memory Bank Dividers kugadzira heterogeneous memory masisitimu ane asiri-simba-e-2 nhamba yemabhangi ekurangarira. Iwe unofanirwa kugadzira akawanda OpenCL Memory Bank Dividers kana uine yechokwadi heterogeneous memory system. Funga nezve system ine imwe DDR memory interface uye imwe QDR memory interface. Nekuti mabhanga maviri ane akasiyana ndangariro topologies, haugone kuasanganisa pasi peyeuko imwe yepasirese.
Mufananidzo 1. Block Diagram ye Three-Bank Heterogeneous Memory System
Iyi heterogeneous memory system ine maviri DDR memory interfaces uye imwe QDR memory interface.Kana uri kushandisa vhezheni 16.0, 16.0.1, kana 16.0.2 yeIntel Quartus® Prime software uye Altera SDK yeOpenCL, OpenCL Memory Bank Divider inobata zvisizvo kuputika kwendangariro pamiganhu yekero. Kuti ugadzirise nyaya iyi inozivikanwa, wedzera pombi bhiriji rine kuputika saizi 1 uye batanidza tenzi wayo weAvalon®Memory-Mapped (Avalon-MM) kuchiteshi chevaranda cheOpenCL Memory Bank Divider.
Cherechedza:
Iyi nyaya inozivikanwa inogadziriswa muIntel Quartus Prime software uye Intel FPGA SDK yeOpenCL vhezheni 16.1.
Mufananidzo 2. Block Digiramu yeTtatu-Bhangi Heterogeneous Memory System ine Pipeline Bridge 1.4. Kugadzirisa iyo Boardtest Chirongwa uye Iyo Yekugamuchira Kodhi yeYako Heterogeneous Memory Solution
Shandisa boardtest.cl kernel inouya neIntel FPGA SDK yeOpenCL Custom Platform Toolkit kuyedza kushanda nekushanda kweCustom Platform yako.
Iyo boardtest chirongwa iOpenCL kernel inokubvumira kuti uedze host-to-device bandwidth, memory bandwidth, uye zvakajairika kushanda kweCustom Platform yako.

1. Bhurawuza ku /board/ custom_platform_toolkit/tests/boardtest directory.
2. Vhura iyo boardtest.cl file mune chinyorwa edhita uye govera nzvimbo yebuffer kune yega yega yepasi rose yekurangarira nharo.
   For example:
   __kernel void
   mem_stream (__global__attribute__((buffer_location(“DDR”))) uint *src, __global __attribute__((buffer_location(“QDR”)))) uint *dst, uint arg, uint arg2)
   Pano, uint * src inopihwa kuDDR memory, uye uint *dst inopihwa QDR memory. The board_spec.xml file inotsanangura maitiro eese mamemory system.
3. Kuti ukwidziridze mhinduro yako yekurangarira muOpenCL system, shandura kodhi yako yekugamuchira nekuwedzera iyo CL_MEM_HETEROGENEOUS_INTELFPGA mureza kune yako clCreateBuffer kufona.
   For example:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags
   CL_MEM_HETEROGENEOUS_INTELFPGA, sizeof(isina kusaina) * vectorSize, NULL, &status);
   Intel inokurudzira zvakasimba kuti iwe uise iyo buffer nzvimbo senge kernel nharo usati wanyora buffer. Paunenge uchishandisa ndangariro imwe chete yepasirese, unogona kunyora mabhafa usati kana mushure mekuvapa kune kernel nharo. Mune heterogeneous memory system, mugadziri anoseta buffer nzvimbo asati anyora buffer. Mune mamwe mazwi, muridzi achadaidza clSetKernelArgument basa asati adaidza clEnqueueWriteBuffer basa.
   Mune kodhi yako yekugamuchira, koka iyo clCreateBuffer, clSetKernelArg, uye clEnqueueWriteBuffer mafoni nenzira inotevera:
   ddatain = clCreateBuffer(context, CL_MEM_READ_WRITE | memflags |
   CL_MEM_HETEROGENEOUS_INTELFPGA, sizeof(isina kusaina) * vectorSize, NULL, &status);
   … chimiro = clSetKernelArg(kernel[k], 0, sizeof(cl_mem), (isina*)&ddatain);
   … chimiro = clEnqueueWriteBuffer(mutsara, ddatain, CL_FALSE, 0, sizeof(isina kusaina) * vectorSize,hdatain, 0, NULL, NULL);
   Iyo ALTERAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/host/memspeed.cpp file inopa kurongeka kwakafanana kweidzi basa mafoni.
4.  Mushure mekugadzirisa boardtest.cl file uye iyo kodhi kodhi, unganidza iyo host uye kernel kodhi uye simbisa mashandiro avo.
   Paunenge uchigadzira yako kernel kodhi, iwe unofanirwa kudzima kuputika-kupindirana kwese ndangariro masisitimu nekubatanidza iyo -no-interleaving. sarudzo mune iyo ac command.

Related Information
Kudzima Kuputika-Kupindirana kweGlobal Memory (-hapana-inopindirana )

1.5. Kuonesa Kushanda kweYako Heterogeneous Memory System
Kuti uone kuti iyo heterogeneous memory system inoshanda nemazvo, bvisa mureza weCL_CONTEXT_COMPILER_MODE_INTELFPGA mukodhi yako yekugamuchira.
MuOpenCL masisitimu ane homogeneous memory, unofanira kusarudza kuseta CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 mureza mukodhi yako yekugamuchira kuti uvhare kuverenga kwe.aocx. file uye kurongazve kweFPGA. Kuseta CL_CONTEXT_COMPILER_MODE_INTELFPGA=3 mureza kunobatsira paunenge uchimisikidza bhodhi rako kuti uone kushanda kweCustom Platform yako pasina kugadzira floorplan uye kudoma matunhu eLogicLock™.
Iine heterogeneous memory system, nharaunda yenguva yekumhanya inofanirwa kuverenga nzvimbo dzebuffer dzebafa yega yega, inotsanangurwa mu.aocx. file, kuratidza mashandiro ememory system. Nekudaro, iwe ungangoda kuonesa kushanda kweCustom yako Platform pasina kuita ekupedzisira maficha ebhodhi dhizaini, sekugadzira iyo floorplan uye kutsanangura iyo LogicLock matunhu.

1. Ona kuti CL_CONTEXT_COMPILER_MODE_INTELFPGA mureza hauna kuiswa mukodhi yako yekugamuchira.
2. Bhurawuza kubhodhi/ /source/host/mmd dhairekitori yeCustom Platform yako.
3. Vhura iyo acl_pcie_device.cpp memory-mapped device (MMD) file mune text editor.
4.  Shandura basa reprogram mu acl_pcie_device.cpp file nekuwedzera kudzoka 0; mutsetse, sezvinoratidzwa pasi apa:
   int ACL_PCIE_DEVICE::reprogram(isina *data, size_t data_size)
   {
   return 0;
   // funga kukundikana
   int reprogram_failed = 1;
   // usafunga kuti hapana rbf kana hashi mufpga.bin
   int rbf_or_hash_not_provided = 1;
   // fungidzira hwaro uye kupinza kudzokorora hashes hazvienderane
   int hash_mismatch = 1;
   …
   }
5. Dzokorora iyo acl_pcie_device.cpp file.
6. Tarisa kuti CL_CONTEXT_COMPILER_MODE_INTELFPGA mureza unoramba usina kurongwa.
   Chenjerera: Mushure mekuwedzera kudzoka 0; kune reprogram basa uye dzokorora iyo MMD file, iyo nguva yekumhanya ichaverenga iyo .aocx file uye govera iyo buffer nzvimbo asi haizogadzirise iyo FPGA. Unofanira kuenzanisa mufananidzo weFPGA ne.aocx file. Kuti udzore maitiro aya, bvisa kudzoka 0; kubva pane reprogram basa uye dzokorora iyo MMD file.

1.6. Document Revision History

Date	Version	Kuchinja
Dec-17	2017.12.01	• Yakashandurwazve kuti CL_MEM_HETEROGENEOUS_ALTERA kuita CL_MEM_HETEROGENEOUS_INTELFPGA.
Dec-16	2016.12.13	• Yakashandurwa kuti CL_CONTEXT_COMPILER_MODE_ALTERA kuita CL_CONTEXT_COMPILER_MODE_INTELFPGA.

Kugadzira Heterogeneous Memory Systems muIntel® FPGA SDK yeOpenCL
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ID: 683654
Shanduro: 2016.12.13

Zvinyorwa / Zvishandiso

intel Kugadzira Heterogeneous Memory Systems muFPGA SDK yeOpenCL Custom Platforms [pdf] Mirayiridzo Kugadzira Heterogeneous Memory Systems muFPGA SDK yeOpenCL Custom Platforms, Kugadzira Heterogeneous Memory Systems, FPGA SDK yeOpenCL Tsika Mapuratifomu.

References

• User Manual