Trenz Electronic TE0725LP FPGA Module Technical Overview and Schematics

Legal Notices

Regarding the usage of our schematics and alike documentation for Trenz module TE0725LP. Project is protected under copyright and we strongly and strictly prohibit the reverse engineering or recreation, even if the design is just adapted or modified. TE0725LP is protected under such right and in case of plagiarism we will have to do anything necessary in order to protect our assets. Schematics and other handouts serve for informational purposes only!

Manufacturer: Trenz Electronic GmbH
Address: Beendorfer Str. 23, 32609 Huellhorst, Germany

Certifications: CE UKCA RoHS

Revision History

REV -01: Initial revision

REV -02:

L1, L2, L6 ferrit beads BKP0603HS121-T replaced with MPZ0603S121HT000.
Added J4 and R30 (JTAG only Enable).
Added Diode D1 for INIT reset.
Added Diode D3 for U8 input protection.
Added a pull-up resistor R29 on U7B RESET, pin A4.
Added a pull-up resistor R31 on SPI_DQ2, pin C4.
Added capacitor C22 to avoid false resetting.
Resistors R13, R72, R29, R18, R20, R31, R21, R3, R9 value 5.6kOhms changed to 2.2kOhms.
Resistor R7 10 kOhms replaced with 2.2 kOhms to optimise the voltage divider values.
Resistors R4, R15 value 2kOhms changed to 330Ohms according to AMD specification (UG470).
Added a 2.4 kOhm resistor R32.
Capacitor C21 value 47 uF changed to 100 uF, added additional decoupling capacitors C33, C34, C35 according to AMD specification (UG 483).
Added C24 to improve noise immunity.
AVCC power rail filter is improved. C1 connected to 1.8V.
Added pages Legal notices, power diagram.
Added System Overview.
Added testpoints TP1 - TP15.

System Overview

The TE0725LP module integrates a Xilinx Artix-7 FPGA. The system architecture connects the FPGA to various peripherals and interfaces. Key components and connections include:

FPGA: Xilinx Artix-7
Interfaces: XADC, SPI, JTAG, UART, XMOD, I2C
Memory: Serial Flash, Serial EEPROM, HyperRAM
Clocking: 25.000000 MHz Oscillator (CLK_SYS)
Indicators: Red LED (D2) for SYSLED
FPGA Banks: Connections to Bank 0, Bank 14, Bank 15, Bank 34, and Bank 35, supporting various IO standards and LVDS pairs.

The module also includes mounting holes and markings for serial numbers, RoHS, UKCA, CE logos, and address overlays.

Power Management

The TE0725LP module supports different power-on sequencing based on the input voltage (VIN). It details sequencing for VIN = 3.3V and VIN = 1.8V.

Supported Voltage Ranges

Power Rail	Direction	Range	Tolerance	Description	Note
VIN	IN	3.3V / 1.8V	+/-3%	Micromodule Power	J1, J2, J3
1.8V_OUT	OUT	1.8V	+/-3%	Power supply for external use	J3
VCCIO35	IN	1.8V ... 3.3V	+/-3%	Power of Bank 35	J1
VCCIO34	IN	1.8V ... 3.3V	+/-3%	Power of Bank 34	J2

The power converter circuits utilize TPS62510DRCR regulators to provide stable voltage outputs.

B2B Connectors (J1, J2, J3) Pin Assignments

J1 (50 Pins)

Pin	Net Name	FPGA Chip/Pin	Function
1	GND		Ground
2	GND		Ground
3	B35 L13 P	U1E A7	IO_L13P_T2_MRCC_35
4	B35 L13 N	U1E C3	IO_L13N_T2_MRCC_35
5	B35 L1 P	U1E D6	IO_L1P_T0_AD4P_35
6	B35 L1 N	U1E F2	IO_L1N_T0_AD4N_35
7	B35 L14 P	U1E G5	IO_L14P_T2_SRCC_35
8	B35 L14 N	U1E J1	IO_L14N_T2_SRCC_35
9	B35 L2 P	U1E C5	IO_L2P_T0_AD12P_35
10	B35 L2 N	U1E E2	IO_L2N_T0_AD12N_35
11	B35 L15 P	U1E H2	IO_L15P_T2_DQS_35
12	B35 L15 N	U1E G2	IO_L15N_T2_DQS_35
13	B35 L3 P	U1E C2	IO_L3P_T0_DQS_AD5P_35
14	B35 L3 N	U1E A6	IO_L3N_T0_DQS_AD5N_35
15	B35 L16 P	U1E C7	IO_L16P_T2_35
16	B35 L16 N	U1E E5	IO_L16N_T2_35
17	B35 L4 P	U1E B7	IO_L4P_T0_35
18	B35 L4 N	U1E D7	IO_L4N_T0_35
19	B35 L17 P	U1E A5	IO_L17P_T2_35
20	B35 L17 N	U1E C4	IO_L17N_T2_35
21	B35 L5 P	U1E B4	IO_L5P_T0_AD13P_35
22	B35 L5 N	U1E A4	IO_L5N_T0_AD13N_35
23	B35 L18 P	U1E A3	IO_L18P_T2_35
24	B35 L18 N	U1E B1	IO_L18N_T2_35
25	B35 L6 P	U1E A1	IO_L6P_T0_35
26	B35 L6 N	U1E B3	IO_L6N_T0_VREF_35
27	B35 L19 P	U1E C1	IO_L19P_T3_35
28	B35 L19 N	U1E B2	IO_L19N_T3_VREF_35
29	B35 L7 P	U1E E3	IO_L7P_T1_AD6P_35
30	B35 L7 N	U1E D3	IO_L7N_T1_AD6N_35
31	B35 L20 P	U1E E1	IO_L20P_T3_35
32	B35 L20 N	U1E D2	IO_L20N_T3_35
33	B35 L8 P	U1E H6	IO_L8P_T1_AD14P_35
34	B35 L8 N	U1E G4	IO_L8N_T1_AD14N_35
35	B35 L21 P	U1E G3	IO_L21P_T3_DQS_35
36	B35 L21 N	U1E J4	IO_L21N_T3_DQS_35
37	B35 L9 P	U1E H4	IO_L9P_T1_DQS_AD7P_35
38	B35 L9 N	U1E J3	IO_L9N_T1_DQS_AD7N_35
39	B35 L22 P	U1E H5	IO_L22P_T3_35
40	B35 L22 N	U1E G6	IO_L22N_T3_35
41	B35 L10 P	U1E J2	IO_L10P_T1_AD15P_35
42	B35 L10 N	U1E K2	IO_L10N_T1_AD15N_35
43	B35 L23 P	U1E K1	IO_L23P_T3_35
44	B35 L23 N	U1E H6	IO_L23N_T3_35
45	B35 L11 P	U1E K1	IO_L11P_T1_SRCC_35
46	B35 L11 N	U1E H5	IO_L11N_T1_SRCC_35
47	B35 L24 P	U1E K2	IO_L24P_T3_35
48	B35 L24 N	U1E J1	IO_L24N_T3_35
49	B35 L12 P	U1E K1	IO_L12P_T1_MRCC_35
50	B35 L12 N	U1E H5	IO_L12N_T1_MRCC_35

J2 (50 Pins)

Pin	Net Name	FPGA Chip/Pin	Function
1	GND		Ground
2	GND		Ground
3	B34 L13 P	U1D K4	IO_L13P_T2_MRCC_34
4	B34 L13 N	U1D N3	IO_L13N_T2_MRCC_34
5	B34 L1 P	U1D P6	IO_L1P_T0_34
6	B34 L1 N	U1D K6	IO_L1N_T0_34
7	B34 L14 P	U1D L1	IO_L14P_T2_SRCC_34
8	B34 L14 N	U1D M1	IO_L14N_T2_SRCC_34
9	B34 L2 P	U1D K3	IO_L2P_T0_34
10	B34 L2 N	U1D M3	IO_L2N_T0_34
11	B34 L15 P	U1D N2	IO_L15P_T2_DQS_34
12	B34 L15 N	U1D N1	IO_L15N_T2_DQS_34
13	B34 L3 P	U1D M4	IO_L3P_T0_DQS_34
14	B34 L3 N	U1D M2	IO_L3N_T0_DQS_34
15	B34 L16 P	U1D K5	IO_L16P_T2_34
16	B34 L16 N	U1D L4	IO_L16N_T2_34
17	B34 L4 P	U1D L6	IO_L4P_T0_34
18	B34 L4 N	U1D L5	IO_L4N_T0_34
19	B34 L17 P	U1D U1	IO_L17P_T2_34
20	B34 L17 N	U1D V1	IO_L17N_T2_34
21	B34 L5 P	U1D U4	IO_L5P_T0_34
22	B34 L5 N	U1D U3	IO_L5N_T0_34
23	B34 L18 P	U1D U2	IO_L18P_T2_34
24	B34 L18 N	U1D V2	IO_L18N_T2_34
25	B34 L6 P	U1D V5	IO_L6P_T0_34
26	B34 L6 N	U1D U5	IO_L6N_T0_VREF_34
27	B34 L19 P	U1D V4	IO_L19P_T3_34
28	B34 L19 N	U1D R3	IO_L19N_T3_VREF_34
29	B34 L7 P	U1D U6	IO_L7P_T1_34
30	B34 L7 N	U1D U5	IO_L7N_T1_34
31	B34 L20 P	U1D V4	IO_L20P_T3_34
32	B34 L20 N	U1D R3	IO_L20N_T3_34
33	B34 L8 P	U1D U6	IO_L8P_T1_34
34	B34 L8 N	U1D U5	IO_L8N_T1_34
35	B34 L21 P	U1D V7	IO_L21P_T3_DQS_34
36	B34 L21 N	U1D V9	IO_L21N_T3_DQS_34
37	B34 L9 P	U1D V5	IO_L9P_T1_DQS_34
38	B34 L9 N	U1D V2	IO_L9N_T1_DQS_34
39	B34 L22 P	U1D U9	IO_L22P_T3_34
40	B34 L22 N	U1D V9	IO_L22N_T3_34
41	B34 L10 P	U1D U7	IO_L10P_T1_34
42	B34 L10 N	U1D V5	IO_L10N_T1_34
43	B34 L23 P	U1D U6	IO_L23P_T3_34
44	B34 L23 N	U1D U7	IO_L23N_T3_34
45	B34 L11 P	U1D R7	IO_L11P_T1_SRCC_34
46	B34 L11 N	U1D U6	IO_L11N_T1_SRCC_34
47	B34 L24 P	U1D R5	IO_L24P_T3_34
48	B34 L24 N	U1D U7	IO_L24N_T3_34
49	B34 L12 P	U1D R3	IO_L12P_T1_MRCC_34
50	B34 L12 N	U1D T3	IO_L12N_T1_MRCC_34

J3 (14 Pins)

Pin	Net Name	FPGA Chip/Pin	Function
1	GND		Ground
2	GND		Ground
3	F_TCK	E10	TCK_0
4	F_TDO	E13	TDO_0
5	F_TDI	E11	TDI_0
6	F_TMS	E12	TMS_0
7	UART_RXD		UART RXD
8	UART_TXD		UART TXD
9	XMOD_E		XMOD E
10	nRST		Reset
11	XADC N		XADC N
12	XADC P		XADC P
13	GND		Ground
14	GND		Ground

Bank 14 HR (U1A) Pin Assignments

Pin assignments for Bank 14 High Range (HR) on FPGA chip U1A:

FPGA Pin	Net Name	Function
N13	VCCO_14	VCCO_14
P15	IO_L13P_T2_MRCC_14	IO_L13P_T2_MRCC_14
R15	IO_L13N_T2_MRCC_14	IO_L13N_T2_MRCC_14
T14	IO_L14P_T2_SRCC_14	IO_L14P_T2_SRCC_14
T15	IO_L14N_T2_SRCC_14	IO_L14N_T2_SRCC_14
R16	IO_L15P_T2_DQS_RDWR_B_14	IO_L15P_T2_DQS_RDWR_B_14
T16	IO_L15N_T2_DQS_DOUT_CSO_B_14	IO_L15N_T2_DQS_DOUT_CSO_B_14
V15	IO_L16P_T2_CSI_B_14	IO_L16P_T2_CSI_B_14
V16	IO_L16N_T2_A15_D31_14	IO_L16N_T2_A15_D31_14
U17	IO_L17P_T2_A14_D30_14	IO_L17P_T2_A14_D30_14
U18	IO_L17N_T2_A13_D29_14	IO_L17N_T2_A13_D29_14
U16	IO_L18P_T2_A12_D28_14	IO_L18P_T2_A12_D28_14
V17	IO_L18N_T2_A11_D27_14	IO_L18N_T2_A11_D27_14
T11	IO_L19P_T3_A10_D26_14	IO_L19P_T3_A10_D26_14
U11	IO_L19N_T3_A09_D25_VREF_14	IO_L19N_T3_A09_D25_VREF_14
U12	IO_L20P_T3_A08_D24_14	IO_L20P_T3_A08_D24_14
V12	IO_L20N_T3_A07_D23_14	IO_L20N_T3_A07_D23_14
V10	IO_L21P_T3_DQS_14	IO_L21P_T3_DQS_14
V11	IO_L21N_T3_DQS_A06_D22_14	IO_L21N_T3_DQS_A06_D22_14
U14	IO_L22P_T3_A05_D21_14	IO_L22P_T3_A05_D21_14
V14	IO_L22N_T3_A04_D20_14	IO_L22N_T3_A04_D20_14
T13	IO_L23P_T3_A03_D19_14	IO_L23P_T3_A03_D19_14
U13	IO_L23N_T3_A02_D18_14	IO_L23N_T3_A02_D18_14
T9	IO_L24P_T3_A01_D17_14	IO_L24P_T3_A01_D17_14
T10	IO_L24N_T3_A00_D16_14	IO_L24N_T3_A00_D16_14
R10	IO_25_14	IO_25_14
L17	VCCO_14	VCCO_14
T12	VCCO_14	VCCO_14
U15	VCCO_14	VCCO_14
V18	VCCO_14	VCCO_14
K17	IO_L1P_T0_D00_MOSI_14	IO_L1P_T0_D00_MOSI_14
K18	IO_L1N_T0_D01_DIN_14	IO_L1N_T0_D01_DIN_14
L14	IO_L2P_T0_D02_14	IO_L2P_T0_D02_14
M14	IO_L2N_T0_D03_14	IO_L2N_T0_D03_14
L15	IO_L3P_T0_DQS_PUDC_B_14	IO_L3P_T0_DQS_PUDC_B_14
L16	IO_L3N_T0_DQS_EMCCLK_14	IO_L3N_T0_DQS_EMCCLK_14
L18	IO_L4P_T0_D04_14	IO_L4P_T0_D04_14
M18	IO_L4N_T0_D05_14	IO_L4N_T0_D05_14
R12	IO_L5P_T0_D06_14	IO_L5P_T0_D06_14
R13	IO_L5N_T0_D07_14	IO_L5N_T0_D07_14
L13	IO_L6P_T0_FCS_B_14	IO_L6P_T0_FCS_B_14
M13	IO_L6N_T0_D08_VREF_14	IO_L6N_T0_D08_VREF_14
R18	IO_L7P_T1_D09_14	IO_L7P_T1_D09_14
T18	IO_L7N_T1_D10_14	IO_L7N_T1_D10_14
N14	IO_L8P_T1_D11_14	IO_L8P_T1_D11_14
P14	IO_L8N_T1_D12_14	IO_L8N_T1_D12_14
N17	IO_L9P_T1_DQS_14	IO_L9P_T1_DQS_14
P18	IO_L9N_T1_DQS_D13_14	IO_L9N_T1_DQS_D13_14
M16	IO_L10P_T1_D14_14	IO_L10P_T1_D14_14
M17	IO_L10N_T1_D15_14	IO_L10N_T1_D15_14
N15	IO_L11P_T1_SRCC_14	IO_L11P_T1_SRCC_14
N16	IO_L11N_T1_SRCC_14	IO_L11N_T1_SRCC_14
P17	IO_L12P_T1_MRCC_14	IO_L12P_T1_MRCC_14
R17	IO_L12N_T1_MRCC_14	IO_L12N_T1_MRCC_14

Bank 15 HR (U1B) Pin Assignments

Pin assignments for Bank 15 High Range (HR) on FPGA chip U1B:

FPGA Pin	Net Name	Function
A17	VCCO_15	VCCO_15
C13	VCCO_15	VCCO_15
D16	VCCO_15	VCCO_15
G15	IO_0_15	IO_0_15
H18	IO_L13P_T2_MRCC_15	IO_L13P_T2_MRCC_15
K14	IO_L13N_T2_MRCC_15	IO_L13N_T2_MRCC_15
G13	IO_L1P_T0_AD0P_15	IO_L1P_T0_AD0P_15
F15	IO_L1N_T0_AD0N_15	IO_L1N_T0_AD0N_15
H14	IO_L14P_T2_SRCC_15	IO_L14P_T2_SRCC_15
D14	IO_L14N_T2_SRCC_15	IO_L14N_T2_SRCC_15
C14	IO_L2P_T0_AD8P_15	IO_L2P_T0_AD8P_15
F16	IO_L2N_T0_AD8N_15	IO_L2N_T0_AD8N_15
B13	IO_L3P_T0_DQS_AD1P_15	IO_L3P_T0_DQS_AD1P_15
H1	IO_L15P_T2_DQS_15	IO_L15P_T2_DQS_15
B11	IO_L3N_T0_DQS_AD1N_15	IO_L3N_T0_DQS_AD1N_15
D18	IO_L15N_T2_DQS_ADV_B_15	IO_L15N_T2_DQS_ADV_B_15
A11	IO_L4P_T0_15	IO_L4P_T0_15
E17	IO_L16P_T2_A28_15	IO_L16P_T2_A28_15
F13	IO_L4N_T0_15	IO_L4N_T0_15
D17	IO_L16N_T2_A27_15	IO_L16N_T2_A27_15
H16	IO_L5P_T0_AD9P_15	IO_L5P_T0_AD9P_15
C16	IO_L17P_T2_A26_15	IO_L17P_T2_A26_15
D12	IO_L5N_T0_AD9N_15	IO_L5N_T0_AD9N_15
C17	IO_L17N_T2_A25_15	IO_L17N_T2_A25_15
B16	IO_L6P_T0_15	IO_L6P_T0_15
E18	IO_L18P_T2_A24_15	IO_L18P_T2_A24_15
B17	IO_L6N_T0_VREF_15	IO_L6N_T0_VREF_15
A18	IO_L18N_T2_A23_15	IO_L18N_T2_A23_15
A15	IO_L7P_T1_AD2P_15	IO_L7P_T1_AD2P_15
G18	IO_L19P_T3_A22_15	IO_L19P_T3_A22_15
A16	IO_L7N_T1_AD2N_15	IO_L7N_T1_AD2N_15
H15	IO_L19N_T3_A21_VREF_15	IO_L19N_T3_A21_VREF_15
A13	IO_L8P_T1_AD10P_15	IO_L8P_T1_AD10P_15
C15	IO_L20P_T3_A20_15	IO_L20P_T3_A20_15
A14	IO_L8N_T1_AD10N_15	IO_L8N_T1_AD10N_15
D15	IO_L20N_T3_A19_15	IO_L20N_T3_A19_15
B18	IO_L9P_T1_DQS_AD3P_15	IO_L9P_T1_DQS_AD3P_15
E16	IO_L21P_T3_DQS_15	IO_L21P_T3_DQS_15
G18	IO_L9N_T1_DQS_AD3N_15	IO_L9N_T1_DQS_AD3N_15
J18	IO_L21N_T3_DQS_A18_15	IO_L21N_T3_DQS_A18_15
H17	IO_L10P_T1_AD11P_15	IO_L10P_T1_AD11P_15
K15	IO_L22P_T3_A17_15	IO_L22P_T3_A17_15
J17	IO_L10N_T1_AD11N_15	IO_L10N_T1_AD11N_15
J15	IO_L22N_T3_A16_15	IO_L22N_T3_A16_15
K15	IO_L11P_T1_SRCC_15	IO_L11P_T1_SRCC_15
H1	IO_L23P_T3_FOE_B_15	IO_L23P_T3_FOE_B_15
K16	IO_L11N_T1_SRCC_15	IO_L11N_T1_SRCC_15
J16	IO_L23N_T3_FWE_B_15	IO_L23N_T3_FWE_B_15
K15	IO_L12P_T1_MRCC_15	IO_L12P_T1_MRCC_15
H13	IO_L24P_T3_RS1_15	IO_L24P_T3_RS1_15
K16	IO_L12N_T1_MRCC_15	IO_L12N_T1_MRCC_15
J16	IO_L24N_T3_RS0_15	IO_L24N_T3_RS0_15
H10	VCCADC_0	VCCADC_0
H9	GNDADC_0	GNDADC_0
J10	VP_0	VP_0
K9	VN_0	VN_0
K10	VREFP_0	VREFP_0
J9	VREFN_0	VREFN_0

Bank 34 HR (U1D) Pin Assignments

Pin assignments for Bank 34 High Range (HR) on FPGA chip U1D:

FPGA Pin	Net Name	Function
K4	VCCO_34	VCCO_34
N3	VCCO_34	VCCO_34
P6	VCCO_34	VCCO_34
V8	VCCO_34	VCCO_34
K6	IO_0_34	IO_0_34
N5	IO_L13P_T2_MRCC_34	IO_L13P_T2_MRCC_34
P5	IO_L13N_T2_MRCC_34	IO_L13N_T2_MRCC_34
L1	IO_L1P_T0_34	IO_L1P_T0_34
P3	IO_L14P_T2_SRCC_34	IO_L14P_T2_SRCC_34
B34 L1 P	IO_L1N_T0_34	IO_L1N_T0_34
P2	IO_L14N_T2_SRCC_34	IO_L14N_T2_SRCC_34
B34 L14 P	IO_L2P_T0_34	IO_L2P_T0_34
P3	IO_L15P_T2_DQS_34	IO_L15P_T2_DQS_34
B34 L14 N	IO_L2N_T0_34	IO_L2N_T0_34
B34 L3 P	IO_L15N_T2_DQS_34	IO_L15N_T2_DQS_34
N2	IO_L3P_T0_DQS_34	IO_L3P_T0_DQS_34
B34 L3 N	IO_L16P_T2_34	IO_L16P_T2_34
R2	IO_L3N_T0_DQS_34	IO_L3N_T0_DQS_34
B34 L15 P	IO_L16N_T2_34	IO_L16N_T2_34
N1	IO_L4P_T0_34	IO_L4P_T0_34
B34 L15 N	IO_L17P_T2_34	IO_L17P_T2_34
M4	IO_L4N_T0_34	IO_L4N_T0_34
B34 L16 P	IO_L17N_T2_34	IO_L17N_T2_34
M3	IO_L5P_T0_34	IO_L5P_T0_34
B34 L16 N	IO_L18P_T2_34	IO_L18P_T2_34
M2	IO_L5N_T0_34	IO_L5N_T0_34
B34 L17 P	IO_L18N_T2_34	IO_L18N_T2_34
K5	IO_L6P_T0_34	IO_L6P_T0_34
B34 L17 N	IO_L19P_T3_34	IO_L19P_T3_34
L4	IO_L6N_T0_VREF_34	IO_L6N_T0_VREF_34
B34 L18 P	IO_L19N_T3_VREF_34	IO_L19N_T3_VREF_34
M6	IO_L7P_T1_34	IO_L7P_T1_34
B34 L18 N	IO_L20P_T3_34	IO_L20P_T3_34
N6	IO_L7N_T1_34	IO_L7N_T1_34
B34 L19 P	IO_L20N_T3_34	IO_L20N_T3_34
U1	IO_L8P_T1_34	IO_L8P_T1_34
B34 L19 N	IO_L21P_T3_DQS_34	IO_L21P_T3_DQS_34
V1	IO_L8N_T1_34	IO_L8N_T1_34
B34 L20 P	IO_L21N_T3_DQS_34	IO_L21N_T3_DQS_34
U4	IO_L9P_T1_DQS_34	IO_L9P_T1_DQS_34
B34 L20 N	IO_L22P_T3_34	IO_L22P_T3_34
U3	IO_L9N_T1_DQS_34	IO_L9N_T1_DQS_34
B34 L21 P	IO_L22N_T3_34	IO_L22N_T3_34
U2	IO_L10P_T1_34	IO_L10P_T1_34
B34 L21 N	IO_L23P_T3_34	IO_L23P_T3_34
V2	IO_L10N_T1_34	IO_L10N_T1_34
B34 L22 P	IO_L23N_T3_34	IO_L23N_T3_34
U7	IO_L11P_T1_SRCC_34	IO_L11P_T1_SRCC_34
B34 L22 N	IO_L24P_T3_34	IO_L24P_T3_34
V5	IO_L11N_T1_SRCC_34	IO_L11N_T1_SRCC_34
B34 L23 P	IO_L24N_T3_34	IO_L24N_T3_34
U6	IO_L12P_T1_MRCC_34	IO_L12P_T1_MRCC_34
B34 L23 N	IO_25_34	IO_25_34
V4	IO_L12N_T1_MRCC_34	IO_L12N_T1_MRCC_34

Bank 35 HR (U1E) Pin Assignments

Pin assignments for Bank 35 High Range (HR) on FPGA chip U1E:

FPGA Pin	Net Name	Function
A7	VCCO_35	VCCO_35
C3	VCCO_35	VCCO_35
D6	VCCO_35	VCCO_35
F2	IO_0_35	IO_0_35
G5	IO_L13P_T2_MRCC_35	IO_L13P_T2_MRCC_35
J1	IO_L13N_T2_MRCC_35	IO_L13N_T2_MRCC_35
F4	IO_L1P_T0_AD4P_35	IO_L1P_T0_AD4P_35
C6	IO_L1N_T0_AD4N_35	IO_L1N_T0_AD4N_35
C5	IO_L14P_T2_SRCC_35	IO_L14P_T2_SRCC_35
B7	IO_L14N_T2_SRCC_35	IO_L14N_T2_SRCC_35
D2	IO_L2P_T0_AD12P_35	IO_L2P_T0_AD12P_35
B6	IO_L2N_T0_AD12N_35	IO_L2N_T0_AD12N_35
H2	IO_L15P_T2_DQS_35	IO_L15P_T2_DQS_35
B35 L1 P	IO_L15N_T2_DQS_35	IO_L15N_T2_DQS_35
A6	IO_L3P_T0_DQS_AD5P_35	IO_L3P_T0_DQS_AD5P_35
G2	IO_L16P_T2_35	IO_L16P_T2_35
A5	IO_L3N_T0_DQS_AD5N_35	IO_L3N_T0_DQS_AD5N_35
F3	IO_L16N_T2_35	IO_L16N_T2_35
C7	IO_L4P_T0_35	IO_L4P_T0_35
E6	IO_L17P_T2_35	IO_L17P_T2_35
H1	IO_L4N_T0_35	IO_L4N_T0_35
E5	IO_L17N_T2_35	IO_L17N_T2_35
F1	IO_L5P_T0_AD13P_35	IO_L5P_T0_AD13P_35
G1	IO_L18P_T2_35	IO_L18P_T2_35
E1	IO_L5N_T0_AD13N_35	IO_L5N_T0_AD13N_35
B35 L18 P	IO_L18N_T2_35	IO_L18N_T2_35
E7	IO_L6P_T0_35	IO_L6P_T0_35
G6	IO_L19P_T3_35	IO_L19P_T3_35
D7	IO_L6N_T0_VREF_35	IO_L6N_T0_VREF_35
B35 L19 P	IO_L19N_T3_VREF_35	IO_L19N_T3_VREF_35
B4	IO_L7P_T1_AD6P_35	IO_L7P_T1_AD6P_35
G4	IO_L20P_T3_35	IO_L20P_T3_35
A4	IO_L7N_T1_AD6N_35	IO_L7N_T1_AD6N_35
B35 L20 P	IO_L20N_T3_35	IO_L20N_T3_35
A3	IO_L8P_T1_AD14P_35	IO_L8P_T1_AD14P_35
B35 L21 P	IO_L21P_T3_DQS_35	IO_L21P_T3_DQS_35
B3	IO_L8N_T1_AD14N_35	IO_L8N_T1_AD14N_35
B35 L21 N	IO_L21N_T3_DQS_35	IO_L21N_T3_DQS_35
B2	IO_L9P_T1_DQS_AD7P_35	IO_L9P_T1_DQS_AD7P_35
B35 L22 P	IO_L22P_T3_35	IO_L22P_T3_35
B1	IO_L9N_T1_DQS_AD7N_35	IO_L9N_T1_DQS_AD7N_35
B35 L22 N	IO_L22N_T3_35	IO_L22N_T3_35
A1	IO_L10P_T1_AD15P_35	IO_L10P_T1_AD15P_35
B35 L23 P	IO_L23P_T3_35	IO_L23P_T3_35
B35 L10 N	IO_L10N_T1_AD15N_35	IO_L10N_T1_AD15N_35
B35 L23 N	IO_L23N_T3_35	IO_L23N_T3_35
B35 L11 P	IO_L11P_T1_SRCC_35	IO_L11P_T1_SRCC_35
B35 L24 P	IO_L24P_T3_35	IO_L24P_T3_35
B35 L11 N	IO_L11N_T1_SRCC_35	IO_L11N_T1_SRCC_35
B35 L24 N	IO_L24N_T3_35	IO_L24N_T3_35
B35 L12 P	IO_L12P_T1_MRCC_35	IO_L12P_T1_MRCC_35
B35 L25 P	IO_25_35	IO_25_35
B35 L12 N	IO_L12N_T1_MRCC_35	IO_L12N_T1_MRCC_35

FPGA Configuration

The TE0725LP supports various FPGA configuration modes, as detailed in Xilinx's 7 Series FPGA Configuration User Guide (UG470).

Table 2-1: 7 Series FPGA Configuration Modes

Configuration Mode	M[2:0]	Bus Width	CCLK Direction
Master Serial	000	x1	Output
Master SPI	001	x1, x2, x4	Output
Master BPI	010	x8, x16	Output
Master SelectMAP	100	x8, x16	Output
JTAG	101	x1	Not Applicable
Slave SelectMAP	110	x8, x16, x32⁽¹⁾	Input
Slave Serial⁽²⁾	111	x1	Input

The module utilizes a MT25QU512ABB8E12-0SIT flash memory for configuration storage and supports JTAG programming.

FPGA Power Miscellaneous

This section details the power supply connections and decoupling for the Xilinx Artix-7 FPGA, including:

VCCINT: Core voltage for the FPGA.
VCCAUX: Auxiliary voltage for the FPGA.
VCCBRAM: Voltage for Block RAM.
VCCADC: Voltage for Analog-to-Digital Converter.
AGND, GND: Ground connections.
VP, VN, VREFP, VREFN: Analog reference pins for XADC.

Extensive decoupling capacitors are used across various power rails to ensure signal integrity and stability.

Power Supply Circuits

The power supply section shows the implementation of voltage regulators, specifically the TPS62510DRCR, used to generate the 1V and 1.8V outputs from the input VIN.

Key power rails managed include:

VIN (Input Voltage)
1V (Regulated Output)
1.8V (Regulated Output)
1.8V_OUT (External Output)

The circuits include input filtering, voltage regulation, and output indicators.

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