Trenz Electronic TE0725LP FPGA Module Documentation
Legal Notices
Regarding the usage of our schematics and alike documentation for Trenz module TE0725LP. Project is protected under copyright and we strongly and strictly prohibit the reverse engineering or recreation, even if the design is just adapted or modified. TE0725LP is protected under such right and in case of plagiarism we will have to do anything necessary in order to protect our assets. Schematics and other handouts serve for informational purposes only!
Revision History
| REV | Description |
|---|---|
| -01 | Initial revision |
| -02 | 1. L1, L2, L6 ferrit beads BKP0603HS121-T replaced with MPZ0603S121HT000. 2. Added J4 and R30 (JTAG only Enable). 3. Added Diode D1 for INIT reset. 4. Added Diode D3 for U8 input protection. 5. Added a pull-up resistor R29 on U7B RESET, pin A4. 6. Added a pull-up resistor R31 on SPI_DQ2, pin C4. 7. Added capacitor C22 to avoid false resetting. 8. Resistors R13, R72, R29, R18, R20, R31, R21, R3, R9 value 5.6kOhms changed to 2.2kOhms. 9. Resistor R7 10 kOhms replaced with 2.2 kOhms to optimise the voltage divider values. 10. Resistors R4, R15 value 2kOhms changed to 330Ohms according to AMD specification (UG470). 11. Added a 2.4 kOhm resistor R32. 12. Capacitor C21 value 47 uF changed to 100 uF, added additional decoupling capacitors C33, C34, C35 according to AMD specification (UG 483). 13. Added C24 to improve noise immunity. 14. AVCC power rail filter is improved. C1 connected to 1.8V. 15. Added pages Legal notices, power diagram. 16. Added System Overview. 17. Added testpoints TP1 - TP15. |
System Overview
The TE0725LP module is centered around a Xilinx Artix-7 FPGA. It interfaces with various components for configuration, memory, and communication:
- FPGA: Xilinx Artix-7
- Configuration Memory: SPI Flash, Serial EEPROM
- Memory: HyperRAM
- Clock: 25.000000 MHz CLK_SYS Oscillator
- Interfaces: JTAG (for debugging), UART/XMOD (for serial communication)
- Indicators: SYSLED (Red LED D2)
- External Connectors: J1, J2, J3 provide access to FPGA banks and power rails.
- Certifications: The module features CE, UKCA, and RoHS compliance markings.
Power-on Sequencing and Supported Voltage Ranges
The module supports power-on sequencing for both 3.3V and 1.8V VIN inputs. The diagrams illustrate how the input voltage is regulated to various internal FPGA power rails such as VCCINT, VCCBRAM, VCCIO, and VCCAUX through components like buck converters (e.g., U5, U6, TPS62510DRCR) and associated passive components.
Supported Voltage Ranges:
| Power Rail | Direction | Range | Tolerance | Description | Note |
|---|---|---|---|---|---|
| VIN | IN | 3.3V / 1.8V | +/-3% | Micromodule Power | J1, J2, J3 |
| 1.8V_OUT | OUT | 1.8V | +/-3% | Power supply for external use | J3 |
| VCCIO35 | IN | 1.8V ... 3.3V | +/-3% | Power of Bank 35 | J1 |
| VCCIO34 | IN | 1.8V ... 3.3V | +/-3% | Power of Bank 34 | J2 |
Key signals include power buses, control signals, and net names.
Connector Pinouts
The TE0725LP module provides several connectors for external access:
J1 (50 Pins)
This connector primarily carries VCCIO35 power rails and associated FPGA I/O pins for Bank 35.
J2 (50 Pins)
This connector primarily carries VCCIO34 power rails and associated FPGA I/O pins for Bank 34.
J3 (14 Pins)
This connector provides access to JTAG, UART/XMOD interfaces, power pins, and other essential FPGA signals.
FPGA Configuration Modes
The Xilinx Artix-7 FPGA on the TE0725LP supports various configuration modes, detailed in the table below:
| Configuration Mode | M[2:0] | Bus Width | CCLK Direction |
|---|---|---|---|
| Master Serial | 000 | x1 | Output |
| Master SPI | 001 | x1, x2, x4 | Output |
| Master BPI | 010 | x8, x16 | Output |
| Master SelectMAP | 100 | x8, x16 | Output |
| JTAG | 101 | x1 | Not Applicable |
| Slave SelectMAP | 110 | x8, x16, x32 | Input |
| Slave Serial | 111 | x1 | Input |
FPGA Bank Pin Assignments
The module exposes multiple FPGA I/O banks (14, 15, 34, 35) via its connectors. The following tables detail the pin assignments for each bank:
Bank 14 (J3)
Signals: SPI_DOO, SPI_DQ1, SPI_DO2, SPI_DQ3, UART_TXD, UART_RXD, XMOD E, XADC P, XADC N, TCK, TDI, TDO, TMS, nRST, GND, VCCIO35, VCCIO34.
Bank 15 (J3)
Signals: LVDS_IO, SPI-DOO, SPI-DQ1, SPI-DO2, SPI-DQ3, UART_TXD, UART_RXD, XMOD E, XADC P, XADC N, TCK, TDI, TDO, TMS, nRST, GND, VCCIO35, VCCIO34.
Bank 34 (J2)
This bank provides numerous I/O pins for the FPGA, connected via J2. Signals include various data (IO_xP, IO_xN), clock (MRCC, SRCC), and control lines.
Bank 35 (J1)
This bank provides numerous I/O pins for the FPGA, connected via J1. Signals include various data (IO_xP, IO_xN), clock (MRCC, SRCC), and control lines.
FPGA Power Distribution and Miscellaneous
This section details the power supply and decoupling network for the Xilinx Artix-7 FPGA. It includes:
- Core Voltage: VCCINT, VCCBRAM
- Auxiliary Voltage: VCCAUX
- I/O Voltages: VCCIO35, VCCIO34
- Analog Voltage: VCCADC, AVCC
- Grounds: AGND, GND
- Decoupling: Numerous capacitors (e.g., 470nF, 4.7uF, 100uF) and inductors (e.g., 2.2uH) are used for filtering and stability across various power rails.
- Clock Source: A 25.000000 MHz oscillator (SiT8008BI-73-18S-25.000000E) is connected to the FPGA's clock input.
- XADC: Connections for the FPGA's Analog-to-Digital Converter (XADC P, XADC N) are shown.
Power Supply Circuits
The module utilizes buck converters, specifically the TPS62510DRCR, to generate essential voltage rails. The power supply circuits manage input voltages (VIN) to produce regulated outputs such as 1.8V OUT and 1V. These circuits include inductors (e.g., 2.2uH), capacitors, and feedback resistors for precise voltage regulation.
