Trenz Electronic TE0725LP Module Documentation
Legal Notices
Regarding the usage of our schematics and alike documentation for Trenz module TE0725LP. Project is protected under copyright and we strongly and strictly prohibit the reverse engineering or recreation, even if the design is just adapted or modified. TE0725LP is protected under such right and in case of plagiarism we will have to do anything necessary in order to protect our assets. Schematics and other handouts serve for informational purposes only!
Revision History / Changes List
| REV | Description |
|---|---|
| -01 | Initial revision |
| -02 | 1. L1, L2, L6 ferrit beads BKP0603HS121-T replaced with MPZ0603S121HT000. 2. Added J4 and R30 (JTAG only Enable). 3. Added Diode D1 for INIT reset. 4. Added Diode D3 for U8 input protection. 5. Added a pull-up resistor R29 on U7B RESET, pin A4. 6. Added a pull-up resistor R31 on SPI_DQ2, pin C4. 7. Added capacitor C22 to avoid false resetting. 8. Resistors R13, R72, R29, R18, R20, R31, R21, R3, R9 value 5.6kOhms changed to 2.2kOhms. 9. Resistor R7 10 kOhms replaced with 2.2 kOhms to optimise the voltage divider values. 10. Resistors R4, R15 value 2kOhms changed to 330Ohms according to AMD specification (UG470). 11. Added a 2.4 kOhm resistor R32. 12. Capacitor C21 value 47 uF changed to 100 uF, added additional decoupling capacitors C33, C34, C35 according to AMD specification (UG 483). 13. Added C24 to improve noise immunity. 14. AVCC power rail filter is improved. C1 connected to 1.8V. 15. Added pages Legal notices, power diagram. 16. Added System Overview. 17. Added testpoints TP1 - TP15. |
System Overview
The system overview diagram illustrates the core components and their interconnections. The Xilinx Artix-7 FPGA is central, connected to various peripherals and interfaces. Key connections include SPI SCK, JTAG, UART/XMOD, Serial Flash, Serial EEPROM, and HyperRAM. The diagram also shows the XADC, I2C interface, and a 25.000000 MHz clock source. Memory banks (Bank 0, 14, 15, 34, 35) and their respective I/O counts are indicated, along with a system LED (Red LED D2).
Power-on Sequencing and Supported Voltage Ranges
Two diagrams detail the power-on sequencing for different input voltage (VIN) conditions: VIN = 3.3V and VIN = 1.8V. These illustrate the flow of power to various FPGA voltage rails (VCCINT, VCCBRAM, VCCIO) and supporting components.
| Power Rail | Direction | Range | Tolerance | Description | Note |
|---|---|---|---|---|---|
| VIN | IN | 3.3V / 1.8V | +/-3% | Micromodule Power | J1, J2, J3 |
| 1.8V_OUT | OUT | 1.8V | +/-3% | Power supply for external use | J3 |
| VCCIO35 | IN | 1.8V ... 3.3V | +/-3% | Power of Bank 35 | J1 |
| VCCIO34 | IN | 1.8V ... 3.3V | +/-3% | Power of Bank 34 | J2 |
Additional signals include control signals (EN_GT_R) and power converters.
Connector Pinouts
Detailed pinout information is provided for several connectors, including J1, J2, J3, and JB1. These connectors facilitate access to FPGA I/O banks (e.g., Bank 34, Bank 35), JTAG interface, UART/XMOD communication, and other essential signals.
FPGA Configuration Modes
The document outlines the 7 Series FPGA Configuration Modes, detailing how the FPGA can be configured via different interfaces like Master Serial, Master SPI, Master BPI, Master SelectMAP, and JTAG. A table specifies the configuration mode, M[2:0] values, Bus Width, and CCLK Direction.
| Configuration Mode | M[2:0] | Bus Width | CCLK Direction |
|---|---|---|---|
| Master Serial | 000 | x1 | Output |
| Master SPI | 001 | x1, x2, x4 | Output |
| Master BPI | 010 | x8, x16 | Output |
| Master SelectMAP | 100 | x8, x16 | Output |
| JTAG | 101 | x1 | Not Applicable |
| Slave SelectMAP | 110 | x8, x16, x32(1) | Input |
| Slave Serial (2) | 111 | x1 | Input |
Schematic sections detail the FPGA configuration circuitry, including connections for JTAG, SPI, and flash memory (MT25QU512ABB8E12-0SIT).
Bank Schematics
Detailed schematics are provided for various FPGA I/O banks and associated circuitry:
- Bank 14 & 16 Schematics: Details connections for Bank 14 and Bank 16, including I2C interface (SDA, SCL, WP) and various FPGA I/O pins.
- Bank 15 Schematics: Outlines connections for Bank 15, including interfaces for HyperRAM/Flash memory and FPGA I/O pins.
- Bank 34 Schematics: Presents the pin assignments and connections for Bank 34 of the FPGA, showing numerous I/O signals.
- Bank 35 Schematics: Details the pin assignments and connections for Bank 35 of the FPGA, also featuring numerous I/O signals.
FPGA Power Miscellaneous
This section covers miscellaneous power-related circuitry for the FPGA, including connections for VCCINT, VCCAUX, VCCBRAM, VCCADC, and AGND. It shows the distribution of these power rails and associated decoupling capacitors to ensure stable operation.
Power Supply Schematics
The power supply schematics detail the voltage regulation circuits. They show the implementation of power converters, likely using TPS62510DRCR, to generate specific voltage rails such as 1V and 1.8V from the main input voltage (VIN). These diagrams illustrate input filtering, switching elements, and output voltage monitoring.
testpointsTP1-TP15.VG
