Trenz TE0725LP FPGA Module: Schematics and Technical Information

This document provides detailed schematics, revision history, system overview, and technical specifications for the Trenz Electronic TE0725LP FPGA module. It includes information on power sequencing, voltage ranges, connector pinouts, and FPGA configuration modes.

Page 1: Legal Notices

This section outlines the legal usage terms for the provided schematics and documentation for the Trenz module TE0725LP. The project is protected by copyright, and reverse engineering or recreation is strictly prohibited. Trenz Electronic reserves the right to protect its assets against plagiarism. The schematics and other handouts are provided for informational purposes only.

Page 2: Changes List

This page details the revision history of the TE0725LP module. Key changes include:

Revision -01: Initial release.
Revision -02: Modifications include replacing ferrit beads, adding J4 and R30 for JTAG enable, adding diodes for INIT reset and U8 input protection, adding pull-up resistors (R29, R31), adding capacitor C22 for stability, changing resistor values (R13, R72, R29, R18, R20, R31, R21, R3, R9 from 5.6kΩ to 2.2kΩ; R7 from 10kΩ to 2.2kΩ; R4, R15 from 2kΩ to 330Ω), adding resistor R32 (2.4 kΩ), increasing capacitor C21 from 47µF to 100µF with additional decoupling capacitors (C33, C34, C35), adding C24 for noise immunity, improving AVCC power rail filtering, and adding pages for Legal Notices, Power Diagram, and System Overview, as well as test points TP1-TP15.

Page 3: System Overview

This section provides a system overview diagram illustrating the architecture of the TE0725LP module. It shows the Xilinx Artix-7 FPGA as the central component, connected to various peripherals and interfaces:

FPGA: Xilinx Artix-7, with multiple banks (Bank 0, 14, 15, 34, 35) providing numerous I/O pins.
Interfaces: SPI, UART, I2C, JTAG, XADC.
Peripherals: Oscillator (25.000000 MHz CLK_SYS), Serial Flash, Serial EEPROM, HyperRAM, Red LED (SYSLED).
Connectors: J1, J2, J3, JB1 are shown, facilitating access to these interfaces and power.
Physical Features: Mentions mounting holes and placement of logos (RoHS, UKCA, CE) and serial numbers.

Page 4: Power-on Sequencing and Voltage Ranges

This section details the power-on sequencing and supported voltage ranges for the TE0725LP module.

Power-on Sequencing:

Diagrams illustrate the power-on sequence for both 3.3V and 1.8V input voltages (VIN). They show how power rails like VCCIO35, VCCIO34, VCCINT, VCCBRAM, VCCAUX, and AVCC are supplied and controlled, along with enable (EN) and power good (PG) signals.

Supported Voltage Ranges:

A table outlines the supported voltage ranges for various power rails:

Power Rail	Direction	Range	Tolerance	Description	Note
VIN	IN	3.3V / 1.8V	+/-3%	Micromodule Power	J1, J2, J3
1.8V_OUT	OUT	1.8V	+/-3%	Power supply for external use	J3
VCCIO35	IN	1.8V ... 3.3V	+/-3%	Power of Bank 35	J1
VCCIO34	IN	1.8V ... 3.3V	+/-3%	Power of Bank 34	J2

The document also defines net naming conventions for power buses and control signals.

Page 5: B2B Connectors

This section details the pinouts for the board-to-board (B2B) connectors (J1, J2, J3, JB1) used on the TE0725LP module. It maps the physical pins to the FPGA signals and power rails.

JB1 Connector: Carries JTAG signals (TCK, TDO, TDI, TMS), UART (RXD, TXD), XMOD, and reset signals.
J1 Connector: Provides access to FPGA Bank 35 I/O signals, VCCIO35, and GND.
J2 Connector: Provides access to FPGA Bank 34 I/O signals, VCCIO34, and GND.
J3 Connector: Provides 1.8V output, VCCIO35, VCCIO34, VIN, and GND.

Detailed pin assignments for each connector are provided, showing signal names and their corresponding FPGA pin numbers or power rail connections.

Page 6: FPGA Configuration

This section describes the configuration modes for the Xilinx Artix-7 FPGA and provides schematic details for the configuration circuitry.

FPGA Configuration Modes:

A table (Table 2-1) lists the various configuration modes, including Master Serial, Master SPI, Master BPI, Master SelectMAP, JTAG, Slave SelectMAP, and Slave Serial. It specifies the M[2:0] mode pins, Bus Width, and CCLK Direction for each mode, referencing the AMD UG470 document.

Configuration Circuitry:

The schematic shows the connections for configuration interfaces, including JTAG, SPI, and clock signals. It details the interface to the flash memory (MT25QU512ABB8E12-0SIT) and associated components like resistors, capacitors, and diodes for initialization and programming.

Page 7: Bank 14 & Bank 16 Connections

This page details the pin assignments and connections for FPGA Bank 14 and Bank 16. It shows the mapping of I/O pins to specific functions and peripherals.

Bank 14: Includes I2C interface signals (SDA, SCL, WP), SPI signals (CS, MOSI, MISO, etc.), UART signals (TXD, RXD), and numerous general-purpose I/O (IO_L*).
Bank 16: Primarily shows general-purpose I/O signals.

Page 8: Bank 15 Connections

This section details the pin assignments and connections for FPGA Bank 15. It highlights signals related to HyperRAM and Flash memory interfaces.

Bank 15: Features signals for HyperRAM/Flash memory control and data, including HR_CLK, HR_DATA, HR_CTRL, RESET, RWDS, Chip Select (CS), and Interrupt (INT).

Page 9: Bank 34 Connections

This page provides the detailed pinout and connections for FPGA Bank 34. It lists a comprehensive set of general-purpose I/O signals available on this bank.

Page 10: Bank 35 Connections

This section details the pin assignments and connections for FPGA Bank 35, similar to Bank 34, showing a wide array of general-purpose I/O signals.

Page 11: FPGA Power and Miscellaneous Connections

This section illustrates the power supply connections and miscellaneous signals for the FPGA. It shows the distribution of power rails such as VCCINT, VCCAUX, VCCBRAM, VCCADC, AGND, and AVCC, along with their associated decoupling capacitors and filters.

Power Rails: Details connections for VCCINT (1V), VCCAUX (1.8V), VCCBRAM (1V), VCCADC (1.8V), AGND, and AVCC.
Decoupling: Extensive use of capacitors (e.g., 470nF, 4.7µF, 100µF) is shown for power rail filtering.
XADC: Connections for the XADC (XADC P, XADC N) are also depicted.

Page 12: Power Management

This section presents the power management circuitry for the TE0725LP module. It includes schematics for the voltage regulators used to generate the required power rails.

Voltage Regulators: Shows the use of TPS62510DRCR regulators to provide 1V and 1.8V outputs from the main input voltage (VIN).
Power Sequencing: Illustrates the control signals and sequences for powering up the module.
Filtering: Includes input and output filtering components for the power supplies.

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