Comparing Power Supply Technologies in AI Data Centers and Telecom

Introduction

With the onset of 5G Networks, there is a significant global expansion requiring high-quality telecom rectifiers. To meet the demand for improved efficiency, lower operating costs, and reduced Bill of Materials (BOM), Wide Bandgap (WBG) solutions are gaining renewed interest. Similarly, Server power supplies are being pushed towards higher efficiency levels with minimal heat loss. Hyperscale data centers, which power the digital economy, big data, IoT, and artificial intelligence (AI), now operate with server racks exceeding 30 kW and employ sophisticated cooling management systems.

5G networks, with their larger antenna arrays (up to 64 Transmit / 64 Receive) facilitating 100-1000X higher data rates and supporting trillions of IoT devices, require substantially more power. While technological advancements have reduced the power needed per base station, a greater number of base stations are still necessary. To support these advanced power management methods, power supplies for base stations must meet increasingly stringent efficiency requirements across all load conditions, from standby to full load.

New Silicon Carbide (SiC) Field Effect Transistors (FETs) enable previously unattainable efficiency targets. This article examines the main topologies and device capabilities, discussing the competitive landscape including Si Superjunction MOSFETs, SiC Cascode JFETs (CJFETs), and Gallium Nitride (GaN) FETs.

Some Basics

A common feature of these power supplies is a power-factor-correction (PFC) section that converts AC to DC at near unity power factor, typically outputting 400 V. This is followed by a DC-DC converter that steps down the 400 V to 48 V or 12 V for system use. Point-of-load converters then supply power to CPUs and memory banks.

Data center server power supplies often operate at light to medium loads for a significant portion of their lifespan. Therefore, both the PFC and DC-DC sections must maintain high efficiency across all load conditions while adhering to thermal constraints during peak load operation. The 80plus standard, used for computing power supplies, reflects this requirement. Servers must meet the Titanium standard, which mandates high efficiency even at 10% load.

Figure 1 illustrates the 80 Plus Standard for Testing Compute Power Supplies, and Figure 2 details the Open Compute Project's Data Center Server Power Supply Standard (80 Plus Titanium). A typical power supply architecture, shown in Figure 3, includes an EMI filter, input bridge rectifier, a dual interleaved boost converter (PFC) with a 650 V / 750 V FET and SiC JBS diode, and a full-bridge LLC stage for the DC-DC conversion. Switching frequencies for the PFC stage typically range from 65–150 kHz. Higher frequencies allow for smaller inductors, trading off power density against efficiency at lower frequencies. Silicon Superjunction MOSFETs with SiC JBS diodes are used to maintain high efficiency during hard switching at 65–150 kHz. Si Superjunction MOSFETs offer fast switching, while SiC Schottky diodes minimize switching losses.

Semiconductor Devices

For the high-voltage side of the PFC and DC-DC units, 650 V / 750 V class devices are commonly used for 48 V and 12 V architectures. Table 1 provides a comparison of industry-equivalent products in the TO247 package, including Silicon Superjunction (Si SJ) devices and onsemi SiC CJFETs. SiC MOS options may require different drive voltages (e.g., –4 V to 18 V). SiC devices generally offer lower gate charge and significantly reduced diode reverse recovery charge (Qrr). The body diode conduction losses of Silicon Superjunction and SiC CJFETs are lower than those of SiC MOSFETs.

Table 2 compares similar devices in a DFN8x8 footprint. Silicon SJ, SiC CJFET, and GaN devices can be driven by standard Silicon gate drives. onsemi SiC CJFETs provide very low on-resistances. Comparing devices at 150°C Rds(on) is best achieved using figures of merit, where WBG solutions demonstrate superior performance, particularly in Rds*Coss(tr) and Rds*Qrr.

Figure 4 illustrates the cross-sectional architecture of common SiC, GaN, and Si Superjunction FETs. GaN HEMTs are lateral devices, while SiC and Si Superjunction FETs are vertical current flow devices. Vertical current flow enables more compact high-voltage devices as the source and drain terminals are on opposite sides of the wafer.

In GaN HEMTs, conduction is confined to the 2DEG channel. SiC devices utilize a short surface channel, with bulk conduction carrying most of the current. The SiC JFET, with its bulk channel and vertical structure, offers the lowest drain-source on-resistance per unit area (RdsA) and the smallest chip size. It is often cascaded with a low-voltage Si MOSFET to form the SiC CJFET.

As device technology advances, the ultimate switching speed limit is determined by the load current charging the device Coss. A low Coss(tr) combined with low on-resistance provides the fastest slew rate and shortest delay time to reach 400 V. SiC CJFETs are particularly well-suited for high-frequency power conversion in this regard.

Regarding Qrr, WBG devices significantly outperform Superjunction Silicon devices. They are preferred for circuits employing hard-switched turn-on, such as in a continuous current mode (CCM) totem pole PFC. In cases where the body diode conducts during the freewheeling state, conduction losses occur due to the body diode's on-state drop. Synchronous conduction, achieved by turning on the FET channel, mitigates these losses. A delay between current reversal detection and FET turn-on can become a significant fraction of the switching period at high frequencies. For instance, a 100 ns dead time is negligible at a 100 kHz switching frequency (10 µs period) but represents 10% of a 1 MHz (100 ns period) cycle. Therefore, low body diode VFSD and low Qrr are advantageous characteristics, areas where SiC CJFETs excel.

Efficient circuit designs avoid hard-switched turn-on, as while turn-off losses can be minimized with WBG devices, turn-on losses remain a factor. The low gate charge of available CJFETs and their low on-resistance contribute to reduced turn-off losses, enabling frequencies in soft-switched circuits to increase by 5–10X.

SiC CJFETs offer excellent avalanche capability, enhancing converter system reliability. Despite their smaller chip sizes, they often surpass the avalanche capability of Superjunction FETs, especially at high current levels. GaN devices, which cannot handle avalanche, are designed with high breakdown voltages to avoid this operating zone.

Gate Drive Considerations

A key advantage of SiC CJFETs is their compatibility with standard gate drives. The low-voltage MOSFET in the cascode configuration has a 5 V Vth and a Vgsmax rating of ±20 V, allowing it to be driven like a Silicon Superjunction MOSFET from 0 to 10 V or 0 to 12 V. Figure 5 compares recommended gate drive voltages and absolute maximum voltage ratings for various power device technologies. SiC MOSFETs typically require negative and positive gate drive, with a total swing of 20 to 25 V. Gate voltages are often close to the absolute maximum ratings, necessitating careful attention to gate spikes. The wide gate swing can increase gate charge losses at higher frequencies. Manufacturers' recommendations for managing Vth hysteresis issues must be followed. SiC CJFETs offer flexibility in gate drive, being compatible with silicon power switch gate voltages.

GaN enhancement mode devices generally have a low Vth and are driven within a narrow gate voltage range, often close to the absolute maximum VGS limits. This necessitates specialized drivers and careful layout to prevent damage. The cascode configuration can help circumvent some of these issues, and the lower gate voltage swing is beneficial for reducing gate losses at higher frequencies.

As devices operate at higher speeds, maintaining device turn-off at high dV/dt becomes challenging, as does managing gate voltage spikes caused by power loop and gate drive loop inductances. Packages with source Kelvin pins have been introduced to address this, with further options discussed later in this article.

Circuit Topologies – PFC Stage

Figure 6 shows a Totem-Pole PFC (TPPFC) circuit and its measured efficiency at 100 kHz on an onsemi demonstration board at 1.5 kW. This circuit eliminates diode conduction losses from both the input diode bridge and the SiC PFC diode. Operating in CCM mode with hard-switched devices, the Totem Pole PFC significantly reduces losses, enabling the achievement of Titanium power efficiency targets.

High power density can be achieved using SiC CJFETs without compromising efficiency, although control and magnetics design complexity increases. An alternative method uses auxiliary switches to achieve zero-voltage transitions at turn-on, eliminating the need for current crossing detection. Similar or better results can be obtained using resonant techniques like auxiliary resonant commutated pole (ARCP), which eliminates both turn-on and turn-off losses. However, the cost-performance benefits of these advanced techniques are most favorable at power levels exceeding 5 kW.

Circuit Topologies: DC-DC Stage

For fixed output voltage, the full-bridge LLC converter offers excellent power density and efficiency, making it the industry standard for higher power levels. For lower power levels, a half-bridge LLC implementation may be used. Frequencies between 100–500 kHz are common, with loss reduction efforts focusing on the transformer secondary and low-voltage secondary MOSFETs due to high current levels at the 12 V output.

For high-voltage FETs, the Vds transition from off-state to diode conduction requires charging the output capacitance. A low Coss(tr) is necessary for rapid charging. Users must minimize dead time before gating the FET for synchronous conduction to reduce body diode conduction losses. Low Rds in the on-state minimizes conduction losses, and the low EOFF of Superjunction and WBG switches helps minimize losses.

If Zero Voltage Switching (ZVS) is lost under light load conditions, diode hard recovery can occur. While this poses no risk for WBG switches like SiC CJFETs, it can damage Silicon Superjunction MOSFETs. To mitigate this, fast recovery versions of Superjunction FETs are often used, but this precaution is not necessary for SiC CJFETs.

Outlook for the Near Future

While Si Superjunction FETs continue to improve, the rate of improvement for SiC and GaN devices is expected to significantly outpace that of Silicon in the coming years. Improvements in RdsA (30–50% every 2–3 years) and package technology are anticipated. Key challenges include reducing inductance and enhancing heat removal in small surface mount options.

A likely trend is the migration to half-bridge elements designed for direct surface mount or as embedded elements within the PCB. This simplifies PCB layout and allows for lower inductance power and gate loops.

Another emerging trend is the integration of the driver with the power device, either as a single driver + switch or as a half-bridge element. This integration absorbs the complexity of unique driving voltage levels and circuits required for SiC and GaN devices, making them more user-friendly. This approach allows each device to perform at its full potential, leading to greater system cost savings and power loss reduction, thereby accelerating WBG adoption.

The SIP half-bridge with integrated gate drive, utilizing 35 mΩ, 1200 V SiC CJFETs, has been described in previous articles. Surface mount options are becoming more prevalent from various suppliers, and this trend is expected to accelerate.

The cost of 650 V wide bandgap switches is decreasing rapidly. onsemi's 650 V / 750 V CJFETs are projected to reach price parity within the next two years. Coupled with ease of use, this is expected to significantly accelerate the deployment of WBG devices in data center server and telecom power supply applications.

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