intel F-Tile Interlaken FPGA IDesign Eksample User Itọsọna

 

Imudojuiwọn fun Intel® Quartus® Prime Design Suite: 21.4
Ẹya IP: 3.1.0

1. Itọsọna Ibẹrẹ Ni kiakia

F-Tile Interlaken Intel® FPGA IP mojuto n pese bench testbench ati apẹrẹ ohun elo kan tẹlẹ.ample ti o atilẹyin akopo ati hardware igbeyewo. Nigbati o ba ṣe ina apẹrẹ example, paramita olootu laifọwọyi ṣẹda awọn files pataki lati ṣe adaṣe, ṣajọ, ati idanwo apẹrẹ naa.

Awọn testbench ati oniru example ṣe atilẹyin NRZ ati ipo PAM4 fun awọn ẹrọ F-tile.
F-Tile Interlaken Intel FPGA IP mojuto ṣe ipilẹṣẹ apẹrẹ examples fun awọn akojọpọ atilẹyin atẹle ti nọmba awọn ọna ati awọn oṣuwọn data.

Tabili 1. Awọn Ijọpọ Atilẹyin IP ti Nọmba Awọn ọna ati Awọn oṣuwọn Data
Awọn akojọpọ atẹle ni atilẹyin ni ẹya sọfitiwia Intel Quartus® Prime Pro Edition 21.4. Gbogbo
awọn akojọpọ miiran yoo ṣe atilẹyin ni ẹya iwaju ti Intel Quartus Prime Pro Edition.

 

Nọmba 1. Awọn Igbesẹ Idagbasoke fun Oniru Example

(1) Iyatọ yii ṣe atilẹyin Ipo Wiwo-ẹgbẹ Interlaken.
(2) Fun apẹrẹ iṣeto-ọna 10, F-tile nilo awọn ọna 12 ti TX PMA lati jẹki aago transceiver ti o ni asopọ fun idinku skew ikanni.

* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

F-Tile Interlaken Intel FPGA IP apẹrẹ mojuto example ṣe atilẹyin awọn ẹya wọnyi:

• Ti abẹnu TX to RX ni tẹlentẹle loopback mode
• Laifọwọyi ṣe ipilẹṣẹ awọn apo-iwe iwọn ti o wa titi
• Awọn agbara iṣayẹwo idii ipilẹ
• Agbara lati lo System Console lati tun apẹrẹ fun idi idanwo tun-ṣe

Aworan 2. Ipele Ipele Ipele Ipele

Alaye ti o jọmọ

• F-Tile Interlaken Intel FPGA IP Itọsọna olumulo
• F-Tile Interlaken Intel FPGA IP Awọn akọsilẹ idasilẹ

1.1. Hardware ati Software Awọn ibeere
Lati ṣe idanwo exampFun apẹrẹ, lo hardware ati sọfitiwia atẹle:

• Ẹya sọfitiwia Intel Quartus Prime Pro Edition 21.4
• console eto ti o wa pẹlu sọfitiwia Intel Quartus Prime Pro Edition
• Simulator ti o ni atilẹyin:
  - Afoyemọ * VCS*
  - Synopsys VCS MX
  - Siemens * EDA ModelSim* SE tabi Questa *
  - Cadence* Xcelium*
• Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Ti o npese awọn Design
olusin 3. Ilana

Tẹle awọn igbesẹ wọnyi lati ṣe ina apẹrẹ example ati testbench:

1. Ninu sọfitiwia Intel Quartus Prime Pro Edition, tẹ File ➤ Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Intel Quartus Prime tuntun, tabi tẹ File ➤ Ṣii Project lati ṣii iṣẹ Intel Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan.
2. Pato ẹbi ẹrọ Agilex ki o yan ẹrọ pẹlu F-Tile fun apẹrẹ rẹ.
3. Ninu Katalogi IP, wa ati tẹ F-Tile Interlaken Intel FPGA IP lẹẹmeji. Ferese Iyatọ IP Tuntun yoo han.
4. Pato orukọ ipele oke kan fun aṣa IP iyatọ rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
5. Tẹ O DARA. Olootu paramita yoo han.

Aworan 4. Eksample Design Tab

6. Lori awọn IP taabu, pato awọn sile fun nyin IP mojuto iyatọ.
7. Lori EksampLe Design taabu, yan Simulation aṣayan lati se ina testbench. Yan aṣayan Synthesis lati ṣe ina apẹrẹ hardware example. O gbọdọ yan o kere ju ọkan ninu awọn aṣayan Simulation ati Synthesis lati ṣe ipilẹṣẹ apẹrẹ tẹlẹample.
8. Fun Ti ipilẹṣẹ HDL kika, mejeeji Verilog ati VHDL aṣayan wa.
9. Fun Apo Idagbasoke Àkọlé, yan Agilex I-Series Transceiver-SOC Development Kit.

Akiyesi: Nigbati o ba yan aṣayan Apo Idagbasoke, awọn iṣẹ iyansilẹ pin ti ṣeto ni ibamu si nọmba apakan apakan ẹrọ Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) ati pe o le yatọ si ẹrọ ti o yan. Ti o ba pinnu lati ṣe idanwo apẹrẹ lori ohun elo lori PCB ti o yatọ, yan Ko si aṣayan kit idagbasoke ati ṣe awọn iṣẹ iyansilẹ pin ti o yẹ ni .qsf file
10. Tẹ ina Eksample Design. Awọn Yan Example Design Directory window han.
11. Ti o ba fẹ yi awọn oniru exampọna itọsọna tabi orukọ lati awọn aṣiṣe ti o han (ilk_f_0_example_design), lọ kiri si ọna tuntun ki o tẹ apẹrẹ tuntun example liana orukọ.
12. Tẹ O DARA.

Akiyesi: Ninu F-Tile Interlaken Intel FPGA IP apẹrẹ example, a SystemPLL ti wa ni instantiated laifọwọyi, ati ki o ti sopọ si F-Tile Interlaken Intel FPGA IP mojuto. Ọna ilana ilana SystemPLL ni apẹrẹ example ni:

example_design.test_env_inst.test_dut.dut.pll

SystemPLL ninu apẹrẹ example pin kanna aago itọkasi 156.26 MHz bi Transceiver.

1.3. Ilana Ilana
F-Tile Interlaken Intel FPGA IP mojuto ṣe ipilẹṣẹ atẹle naa files fun apẹrẹ
example:
olusin 5. Directory Be

Table 2. Hardware Design Eksample File Awọn apejuwe
Awọn wọnyi files wa ninuample_installation_dir>/ilk_f_0_example_design liana.

Table 3. Testbench File Apejuwe
Eyi file jẹ ninu awọnample_installation_dir>/ilk_f_0_example_design / apẹẹrẹample_design / rtl liana.

Table 4. Testbench awọn iwe afọwọkọ
Awọn wọnyi files wa ninuample_installation_dir>/ilk_f_0_example_design / apẹẹrẹample_design / testbench liana.

1.4. Simulating awọn Oniru Example Testbench
olusin 6. Ilana

Tẹle awọn igbesẹ wọnyi lati ṣe adaṣe testbench:

1. Ni aṣẹ aṣẹ, yipada si iwe ilana kikopa testbench. Ona liana niample_installation_dir>/ example_design / testbench.
2. Ṣiṣe awọn iwe afọwọkọ kikopa fun atilẹyin iṣeṣiro ti o fẹ. Awọn akosile akopọ ati ki o nṣiṣẹ testbench ni labeabo. Iwe afọwọkọ rẹ yẹ ki o ṣayẹwo pe SOP ati awọn iṣiro EOP baramu lẹhin ti kikopa ti pari.

Table 5. Igbesẹ lati Ṣiṣe Simulation

3. Ṣe itupalẹ awọn abajade. Simulation aṣeyọri kan firanṣẹ ati gba awọn apo-iwe, ati ṣafihan “Idanwo ti kọja”.
Awọn testbench fun apẹrẹ example pari awọn iṣẹ wọnyi:

• Instantiates awọn F-Tile Interlaken Intel FPGA IP mojuto.
• Tẹjade ipo PHY.
• Ṣiṣayẹwo amuṣiṣẹpọ metaframe (SYNC_LOCK) ati ọrọ (dina) awọn aala
  (ỌRỌ_LOCK).
• Nduro fun awọn ọna onikaluku lati wa ni titiipa ati titọ.
• Bẹrẹ gbigbe awọn apo-iwe.
• Ṣiṣayẹwo awọn iṣiro apo-iwe:
  - CRC24 aṣiṣe
  - Awọn SOPs
  - Awọn EOPs

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri kan:

Akiyesi: Interlaken design example kikopa testbench rán 100 awọn apo-iwe ati ki o gba 100 awọn apo-iwe.

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo kikopa aṣeyọri fun ipo Iwo-ẹgbẹ Interlaken:

1.5. Iṣakojọpọ ati Iṣeto ni Apẹrẹ Hardware Example

1. Rii daju example oniru iran jẹ pari.
2. Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣii iṣẹ akanṣe Intel Quartus Primeample_installation_dir>/ example_design.qpf>.
3. Lori awọn Ṣiṣẹda akojọ, tẹ Bẹrẹ Iṣakojọpọ.
4. Lẹhin akojọpọ aṣeyọri, a .sof file wa ninu rẹ pàtó kan liana.
   Tẹle awọn igbesẹ wọnyi lati ṣe eto hardware example ṣe apẹrẹ lori ẹrọ Intel Agilex pẹlu F-tile:
   a. So Apo Idagbasoke pọ si kọnputa agbalejo.
   b. Ṣe ifilọlẹ ohun elo Iṣakoso Aago, eyiti o jẹ apakan ti ohun elo idagbasoke. Ṣeto titun nigbakugba fun oniru example bi atẹle:
   Fun ipo NRZ:
   - Si5391 (U18), OUT0: Ṣeto si iye pll_ref_clk (3) fun ibeere apẹrẹ rẹ.
   Fun ipo PAM:
   - Si5391 (U45), OUT1: Ṣeto si iye pll_ref_clk (3) fun ibeere apẹrẹ rẹ.
   - Si5391 (U19), OUT1: Ṣeto si iye mac_pll_ref_clk (3) fun ibeere apẹrẹ rẹ. c. Tẹ Awọn irinṣẹ ➤ Oluṣeto eto ➤ Hardware Eto.
   d. Yan ẹrọ siseto. Fi Intel Agilex I-Series Transceiver-SoC Development Apo.
   e. Rii daju pe Ipo ti ṣeto si JTAG.
   f. Yan ẹrọ Intel Agilex I-Series ki o tẹ Fi ẹrọ kun. Awọn pirogirama ṣe afihan aworan atọka ti awọn asopọ laarin awọn ẹrọ lori igbimọ rẹ.
   g. Ṣayẹwo apoti fun .asọ.
   h. Ṣayẹwo apoti ti o wa ninu Eto / atunto ọwọn.
   i. Tẹ Bẹrẹ.

1.6. Idanwo Oniru Hardware Example
Lẹhin ti o ṣajọ F-tile Interlaken Intel FPGA IP apẹrẹ exampati tunto ẹrọ rẹ, o le lo System Console lati ṣe eto ipilẹ IP ati awọn iforukọsilẹ rẹ.

Tẹle awọn igbesẹ wọnyi lati mu Eto Console soke ki o ṣe idanwo apẹrẹ ohun elo example:

• Ko si awọn aṣiṣe fun CRC32, CRC24, ati oluṣayẹwo.
• Awọn SOPs ti a firanṣẹ ati awọn EOP yẹ ki o baamu pẹlu awọn SOP ti o gba ati awọn EOP.

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo aṣeyọri ni ipo Interlaken:

Awọn atẹle sampIṣẹjade le ṣe afihan ṣiṣe idanwo aṣeyọri ni ipo Interlaken Lookside:

 

2. Oniru Example Apejuwe

Apẹrẹ example ṣe afihan awọn iṣẹ ṣiṣe ti Interlaken IP mojuto.

2.1. Oniru Example irinše
Awọn example oniru so eto ati PLL itọkasi asaju ati awọn ti a beere oniru irinše. Awọn example oniru configures IP mojuto ni ti abẹnu loopback mode ati ki o gbogbo awọn apo-iwe lori IP mojuto TX olumulo data ni wiwo. IP mojuto rán awọn wọnyi awọn apo-iwe lori awọn ti abẹnu loopback ona nipasẹ awọn transceiver.

Lẹhin ti olugba IP mojuto gba awọn apo-iwe lori ọna loopback, o ṣe ilana awọn apo-iwe Interlaken ati gbejade wọn lori wiwo gbigbe data olumulo RX. Awọn example oniru sọwedowo wipe awọn apo-iwe gba ati ki o zqwq baramu.

F-Tile Interlaken Intel FPGA IP apẹrẹample pẹlu awọn eroja wọnyi:

1. F-Tile Interlaken Intel FPGA IP mojuto
2. Packet monomono ati Packet Checker
3. F-Tile Reference ati System PLL Agogo Intel FPGA IP mojuto

2.2. Oniru Example Sisan
F-Tile Interlaken Intel FPGA IP apẹrẹ ohun elo example pari awọn igbesẹ wọnyi:

1. Tun F-tile Interlaken Intel FPGA IP ati F-Tile tunto.
2. Tu ipilẹ silẹ lori IP Interlaken (atunṣe eto) ati F-tile TX (tile_tx_rst_n).
3. Ṣe atunto F-tile Interlaken Intel FPGA IP ni ipo loopback inu.
4. Tu silẹ atunṣe ti F-tile RX (tile_rx_rst_n).
5. Firanṣẹ ṣiṣan ti awọn apo-iwe Interlaken pẹlu data asọye tẹlẹ ninu fifuye isanwo si wiwo olumulo data gbigbe olumulo TX ti ipilẹ IP.
6. Ṣayẹwo awọn apo-iwe ti o gba ati ṣe ijabọ ipo naa. Oluyẹwo apo-iwe ti o wa ninu apẹrẹ ohun elo example pese awọn agbara iṣayẹwo idii ipilẹ atẹle wọnyi:
   Ṣayẹwo pe lẹsẹsẹ soso ti a firanṣẹ jẹ deede.
   • Awọn sọwedowo pe data ti o gba ni ibamu pẹlu awọn iye ti a nireti nipa aridaju mejeeji ibẹrẹ ti pakẹti (SOP) ati ipari awọn idii (EOP) ni ibamu nigba ti data n gbejade ati gbigba.

* Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

2.3. Awọn ifihan agbara wiwo
Table 6. Design Example Interface Awọn ifihan agbara

2.4. Forukọsilẹ Map

Akiyesi:

• Apẹrẹ ExampAdirẹsi iforukọsilẹ le bẹrẹ pẹlu 0x20 *** lakoko ti adirẹsi iforukọsilẹ IP mojuto Interlaken bẹrẹ pẹlu 0x10 ***.
• Adirẹsi iforukọsilẹ F-tile PHY bẹrẹ pẹlu 0x30** lakoko ti adirẹsi iforukọsilẹ F-tile FEC bẹrẹ pẹlu 0x40**. Iforukọsilẹ FEC wa ni ipo PAM4 nikan.
• Koodu wiwọle: RO-Ka Nikan, ati RW-Ka/Kọ.
• System console Say oniru Mofiample forukọsilẹ ati awọn ijabọ ipo idanwo loju iboju.

Table 7. Design Example Forukọsilẹ Map

Table 8. Design Example Forukọsilẹ Map fun Interlaken Look-side Design Example
Lo yi Forukọsilẹ map nigba ti o ba se ina awọn oniru Mofiample pẹlu Muu ṣiṣẹ paramita Ipo-ẹgbẹ Interlaken ti wa ni titan.

2.5. Tunto
Ninu F-Tile Interlaken Intel FPGA IP mojuto, o bẹrẹ atunto (reset_n=0) ki o dimu titi ti ipilẹ IP yoo fi pada jẹwọ atunto (reset_ack_n=0). Lẹhin ti a ti yọkuro atunto (reset_n=1), jẹwọ atunto yoo pada si ipo ibẹrẹ (reset_ack_n=1). Ninu apẹrẹ example, iforukọsilẹ rst_ack_sticky kan ni idaniloju idaniloju atunto ati lẹhinna nfa yiyọkuro ti atunto (reset_n=1). O le lo awọn ọna miiran ti o baamu awọn iwulo apẹrẹ rẹ.

Pataki: Ni eyikeyi ohn ibi ti awọn ti abẹnu ni tẹlentẹle loopback wa ni ti beere, o gbọdọ tu TX ati RX ti F-tile lọtọ ni kan pato ibere. Tọkasi iwe afọwọkọ console eto fun alaye diẹ sii.

Ṣe nọmba 7. Tunto Ọkọọkan ni Ipo NRZ

olusin 8. Tunto Ọkọọkan ni Ipo PAM4

 

3. F-Tile Interlaken Intel FPGA IP Design Eksample User Itọsọna Archives

Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.

 

4. Itan Atunyẹwo iwe fun F-Tile Interlaken Intel FPGA IP Design Example User Itọsọna

 

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn aami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si lọwọlọwọ
awọn pato ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ.

 

Ka siwaju sii Nipa Itọsọna yii & Ṣe igbasilẹ PDF:

Awọn iwe aṣẹ / Awọn orisun

intel F-Tile Interlaken FPGA IDesign Eksample [pdf] Itọsọna olumulo F-Tile Interlaken FPGA IDesign Example

Awọn itọkasi

• Itọsọna olumulo