F-Tile Interlaken Intel® FPGA IP Design Example User Guide

1. Quick Start Guide

The F-Tile Interlaken Intel® FPGA IP core provides a simulation testbench. A hardware design example that supports compilation and hardware testing will be available in the Intel Quartus® Prime Pro Edition software version 21.4. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design.

The testbench and design example supports NRZ and PAM4 mode for F-tile devices. The F-Tile Interlaken Intel FPGA IP core generates design examples for the following supported combinations of number of lanes and data rates.

Table 1. IP Supported Combinations of Number of Lanes and Data Rates

The following combinations are supported in the Intel Quartus Prime Pro Edition software version 21.3. All other combinations will be supported in a future version of the Intel Quartus Prime Pro Edition.

Figure 1. Development Steps for the Design Example

Development Steps for the Design Example: A flowchart illustrating the process: Design Example Generation leads to Compilation (Simulator) and Functional Simulation. Separately, Design Example Generation also leads to Compilation (Intel Quartus Prime) and Hardware Testing.

The F-Tile Interlaken Intel FPGA IP core design example supports the following features:

• Internal TX to RX serial loopback mode
• Automatically generates fixed size packets
• Basic packet checking capabilities
• Ability to use System Console to reset the design for re-testing purpose

Figure 2. High-level Block Diagram

High-level Block Diagram: Shows a 'System Console' and 'JTAG Interface' connecting to a 'Traffic Generator' and 'Traffic Checker'. These, in turn, interface with the 'F-Tile Interlaken Intel FPGA IP', which includes a 'Serial Internal Loopback' path.

Related Information

• F-Tile Interlaken Intel FPGA IP User Guide
• F-Tile Interlaken Intel FPGA IP Release Notes

1.1. Hardware and Software Requirements

To test the example design, use the following hardware and software:

• Intel Quartus Prime Pro Edition software version 21.3
• System Console
• Supported Simulator:
  • Synopsys* VCS*
  • Synopsys VCS MX
  • Siemens* EDA ModelSim* SE or Questa*

1.2. Generating the Design

Figure 3. Procedure

Generating the Design Procedure: A sequence of steps: Start Parameter Editor, Specify IP Variation and Select Device, Select Design Parameters, Specify Example Design, and finally Initiate Design Generation.

Figure 4. Example Design Tab

Example Design Tab: Illustrates the user interface for selecting design options, including 'Available Example Design' (e.g., 'Interlaken Serial Loopback Design'), 'Example Design Files' (Simulation, Synthesis), and 'Generated HDL Format' (Verilog).

Follow these steps to generate the design example and testbench:

1. In the Intel Quartus Prime Pro Edition software, click File > New Project Wizard to create a new Intel Quartus Prime project, or click File > Open Project to open an existing Intel Quartus Prime project. The wizard prompts you to specify a device.
2. Specify the device family Agilex and select device with F-Tile for your design.
3. In the IP Catalog, locate and double-click F-Tile Interlaken Intel FPGA IP. The New IP Variant window appears.
4. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
5. Click OK. The parameter editor appears.
6. On the IP tab, specify the parameters for your IP core variation.
7. On the Example Design tab, select the Simulation option to generate the testbench.
8. For Generated HDL Format, both Verilog and VHDL option is available.
9. Click Generate Example Design. The Select Example Design Directory window appears.
10. If you want to modify the design example directory path or name from the defaults displayed (ilk_f_0_example_design), browse to the new path and type the new design example directory name.
11. Click OK.

1.3. Directory Structure

The F-Tile Interlaken Intel FPGA IP core generates the following files for the design example:

Figure 5. Directory Structure

Directory Structure: A hierarchical view of the generated design example files and directories, showing main folders like example_design, rtl, testbench, sim, synth, and sub-files within them, organized under a root directory like <ilk_f_0_example_design>.

Table 2. Hardware Design Example File Descriptions

These files are in the <design_example_installation_dir>/ilk_f_0_example_design directory.

Table 3. Testbench File Description

This file is in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

Table 4. Testbench Scripts

These files are in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

1.4. Simulating the Design Example Testbench

Figure 6. Procedure

Simulating the Design Example Testbench Procedure: A flowchart outlining the simulation process: Change to Testbench Directory, Run <Simulation Script>, and Analyze Results.

Follow these steps to simulate the testbench:

1. At the command prompt, change to the testbench simulation directory. The directory path is <design_example_installation_dir>/example_design/testbench.
2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete.

Table 5. Steps to Run Simulation

The testbench for the design example completes the following tasks:

• Instantiates the F-Tile Interlaken Intel FPGA IP core.
• Prints PHY status.
• Checks metaframe synchronization (SYNC_LOCK) and word (block) boundaries (WORD_LOCK).
• Waits for individual lanes to be locked and aligned.
• Starts transmitting packets.
• Checks packet statistics:
  • CRC24 errors
  • SOPs
  • EOPs

The following sample output illustrates a successful simulation test run:

******************************************
INFO: Waiting for lanes to be aligned
All of the receiver lanes are aligned and are ready
to receive traffic.
***************************************************
***************************************************
INFO: Start transmitting packets
***************************************************
***************************************************
INFO: Stop transmitting packets
***************************************************
***************************************************
INFO: Checking packets statistics
***************************************************
CRC 24 errors reported: 0
SOPs transmitted: 100
EOPs transmitted: 100
SOPs received: 100
EOPs received: 100
ECC error count: 0
***************************************************
INFO: Test PASSED
***************************************************

1.5. Compiling the Design Example

1. Ensure the example design generation is complete.
2. In the Intel Quartus Prime Pro Edition software, open the Intel Quartus Prime project <design_example_installation_dir>/example_design.qpf.
3. On the Processing menu, click Start Compilation.

2. Design Example Description

The design example demonstrates the functionalities of the Interlaken IP core.

2.1. Design Example Components

The example design connects system and PLL reference clocks and required design components. The example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.

After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.

The F-Tile Interlaken Intel IP design example includes the following components:

1. F-Tile Interlaken Intel FPGA IP core
2. Packet Generator and Packet Checker
3. F-Tile Reference and System PLL Clocks Intel FPGA IP core

2.2. Interface Signals

Table 6. Design Example Interface Signals

⁽¹⁾ Only available in PAM4 variants.

2.3. Register Map

Table 7. Design Example Register Map

2.4. Reset

In the F-Tile Interlaken Intel FPGA IP core, you initiate the reset (reset_n=0) and hold until the IP core returns a reset acknowledge (reset_ack_n=0). After the reset is removed (reset_n=1), the reset acknowledge returns to its initial state (reset_ack_n=1). In the design example, a rst_ack_sticky register holds the reset acknowledge assertion and then triggers the removal of the reset (reset_n=1). You can use alternative methods that fit your design needs.

Figure 7. Reset Sequence in NRZ Mode

Reset Sequence in NRZ Mode: A timing diagram showing the interaction of signals like sys_pll_rst, reset_n, reset_ack_n, usr_rst, and rst_ack_sticky during reset and lock states for NRZ mode.

Figure 8. Reset Sequence in PAM4 Mode

Reset Sequence in PAM4 Mode: A timing diagram similar to the NRZ mode, illustrating reset sequences and signal interactions for PAM4 mode, including signals like rst and locked.

3. F-Tile Interlaken Intel FPGA IP Design Example User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

4. Document Revision History