Intel® FPGA P-Tile Avalon ®
IP ṣiṣanwọle fun PCI Express*
Apẹrẹ Example User Itọsọna
Imudojuiwọn fun Intel®
Quartus® NOMBA Design Suite: 21.3
Ẹya IP: 6.0.0
Itọsọna olumulo

Apẹrẹ Example Apejuwe

1.1. Apejuwe Iṣẹ-ṣiṣe fun Input/Ojade ti a ṣe eto (PIO) Apẹrẹ Example

Apẹrẹ PIO example ṣe awọn gbigbe iranti lati ẹrọ isise ogun si ẹrọ ibi-afẹde. Ninu example, awọn isise isise ibeere nikan-dword MemRd ati emWr
Awọn TLPs.
Apẹrẹ PIO example laifọwọyi ṣẹda awọn files pataki lati ṣedasilẹ ati sakojo ni Intel NOMBA software. Apẹrẹ example ni wiwa kan jakejado ibiti o ti sile. Sibẹsibẹ, ko bo gbogbo awọn parameterizations ti o ṣeeṣe ti P-Tile Hard IP fun PCIe.
Apẹrẹ yii example pẹlu awọn eroja wọnyi:

• Ti ipilẹṣẹ P-Tile Avalon Streaming Lile IP Endpoint iyatọ (DUT) pẹlu awọn aye ti o pato. Ẹya paati yii n ṣe awakọ data TLP ti o gba si ohun elo PIO
• Ohun elo PIO (APPS) paati, eyiti o ṣe itumọ pataki laarin awọn TLP PCI Express ati Avalon-MM ti o rọrun lati kọ ati ka si iranti onchip.
• Ohun lori-ërún iranti (MEM) paati. Fun apẹrẹ 1 × 16 example, on-ni ërún iranti oriširiši 16 KB iranti Àkọsílẹ. Fun apẹrẹ 2 × 8 example, iranti on-chip oriširiši meji 16 KB iranti ohun amorindun.
• Tun IP Tu silẹ: IP yii di Circuit iṣakoso ni atunto titi ẹrọ yoo fi tẹ ipo olumulo ni kikun. FPGA n ṣe afihan iṣẹjade INIT_DONE lati ṣe ifihan pe ẹrọ naa wa ni ipo olumulo. Itusilẹ Tun IP ṣe ipilẹṣẹ ẹya iyipada ti ifihan INIT_DONE inu lati ṣẹda iṣẹjade nINIT_DONE ti o le lo fun apẹrẹ rẹ. Ifihan nINIT_DONE ga titi gbogbo ẹrọ yoo fi wọ ipo olumulo. Lẹhin ti nINIT_DONE sọ (kekere), gbogbo ọgbọn wa ni ipo olumulo ati ṣiṣẹ deede. O le lo ifihan agbara nINIT_DONE ni ọkan ninu awọn ọna wọnyi:
  • Lati ẹnu-ọna ita tabi ipilẹ inu.
  • Lati ẹnu-ọna igbewọle atunto si transceiver ati I/O PLLs.
  • Lati ẹnu-ọna kikọ ṣiṣẹ ti awọn bulọọki apẹrẹ gẹgẹbi awọn bulọọki iranti ifibọ, ẹrọ ipinlẹ, ati awọn iforukọsilẹ iyipada.
  • Lati wakọ ni amuṣiṣẹpọ forukọsilẹ awọn ebute igbewọle atunto ninu apẹrẹ rẹ.

Awọn kikopa testbench instantiates awọn PIO oniru example ati ki o kan Gbongbo Port BFM lati ni wiwo pẹlu awọn afojusun Endpoint.
Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ
Olusin 1. Àkọsílẹ aworan atọka fun Platform onise PIO 1×16 Design Example Simulation Testbench

Olusin 2. Àkọsílẹ aworan atọka fun Platform onise PIO 2×8 Design Example Simulation Testbench

Eto idanwo naa kọwe si ati ka data pada lati ipo kanna ni iranti on-chip. O ṣe afiwe data ti a ka si abajade ti a nireti. Awọn ijabọ idanwo naa, “Simulation duro nitori ipari aṣeyọri” ti ko ba si awọn aṣiṣe. The P-Tile Avalon
Apẹrẹ ṣiṣanwọle example ṣe atilẹyin awọn atunto wọnyi:

• Gen4 x16 Ipari
• Gen3 x16 Ipari
• Gen4 x8x8 Ipari
• Gen3 x8x8 Ipari

Akiyesi: Idanwo kikopa fun apẹrẹ PCIe x8x8 PIO example jẹ tunto fun ọna asopọ PCIe x8 kan botilẹjẹpe apẹrẹ gangan n ṣe awọn ọna asopọ PCIe x8 meji.
Akiyesi: Apẹrẹ yii example nikan ṣe atilẹyin awọn eto aiyipada ni Parameter Olootu ti P-tile Avalon Streaming IP fun PCI Express.
Olusin 3. Awọn akoonu Eto Onise Platform fun P-Tile Avalon ṣiṣanwọle PCI Express 1×16 PIO Design Example
Apẹrẹ Platform ṣe ipilẹṣẹ apẹrẹ yii fun to awọn iyatọ Gen4 x16.

Olusin 4. Awọn akoonu Eto Onise Platform fun P-Tile Avalon ṣiṣanwọle PCI Express 2×8 PIO Design Example
Apẹrẹ Platform ṣe ipilẹṣẹ apẹrẹ yii fun to awọn iyatọ Gen4 x8x8.

1.2. Apejuwe Iṣẹ-ṣiṣe fun Gbongbo Nikan I/O Foju (SR-IOV) Apẹrẹ Example
Apẹrẹ SR-IOV example ṣe awọn gbigbe iranti lati ẹrọ isise ogun si ẹrọ ibi-afẹde. O ṣe atilẹyin to awọn PF meji ati 32 VF fun PF.
Apẹrẹ SR-IOV example laifọwọyi ṣẹda awọn files pataki lati ṣedasilẹ ati sakojo ni Intel Quartus Prime software. O le ṣe igbasilẹ apẹrẹ ti a ṣajọpọ si
Ohun elo Idagbasoke Intel Stratix® 10 DX tabi Apo Idagbasoke Intel Agilex™ kan.
Apẹrẹ yii example pẹlu awọn eroja wọnyi:

• Ti ipilẹṣẹ P-Tile Avalon śiśanwọle (Avalon-ST) IP Endpoint iyatọ (DUT) pẹlu awọn paramita ti o pato. Ẹya paati yii n ṣakoso data TLP ti o gba si ohun elo SR-IOV.
• Ohun elo SR-IOV (APPS) paati, eyiti o ṣe itumọ pataki laarin awọn TLP PCI Express ati Avalon-ST ti o rọrun lati kọ ati ka si iranti on-chip. Fun paati SR-IOV APPS, iranti kika TLP yoo ṣe agbekalẹ Ipari pẹlu data.
  • Fun ohun SR-IOV oniru Mofiample pẹlu PFs meji ati 32 VF fun PF, awọn ipo iranti 66 wa ti apẹrẹ example wọle si. Awọn PF meji le wọle si awọn ipo iranti meji, lakoko ti awọn 64 VF (2 x 32) le wọle si awọn ipo iranti 64.
• Itusilẹ IP tunto.
  Awọn kikopa testbench instantiates awọn SR-IOV oniru example ati ki o kan Gbongbo Port BFM lati ni wiwo pẹlu awọn afojusun Endpoint.

Olusin 5. Àkọsílẹ aworan atọka fun Platform onise SR-IOV 1×16 Design Example Simulation Testbench

Olusin 6. Àkọsílẹ aworan atọka fun Platform onise SR-IOV 2×8 Design Example Simulation Testbench

Eto idanwo naa kọwe si ati ka data pada lati ipo kanna ni iranti on-chip kọja 2 PFs ati 32 VFs fun PF. O ṣe afiwe data ti a ka si ti a reti
esi. Awọn ijabọ idanwo naa, “Simulation duro nitori ipari aṣeyọri” ti ko ba si awọn aṣiṣe.
Apẹrẹ SR-IOV example ṣe atilẹyin awọn atunto wọnyi:

• Gen4 x16 Ipari
• Gen3 x16 Ipari
• Gen4 x8x8 Ipari
• Gen3 x8x8 Ipari

Olusin 7. Awọn akoonu Eto Onise Platform fun P-Tile Avalon-ST pẹlu SR-IOV fun PCI Express 1×16 Design Example

Olusin 8. Awọn akoonu Eto Onise Platform fun P-Tile Avalon-ST pẹlu SR-IOV fun PCI Express 2×8 Design Example

Quick Bẹrẹ Itọsọna

Lilo sọfitiwia Intel Quartus Prime, o le ṣe agbekalẹ apẹrẹ I/O (PIO) ti a ṣe eto example fun Intel FPGA P-Tile Avalon-ST Lile IP fun PCI Express * IP mojuto. Awọn ti ipilẹṣẹ oniru example ṣe afihan awọn paramita ti o pato. PIO example gbe data lati a ogun isise to a afojusun ẹrọ. O yẹ fun awọn ohun elo bandiwidi kekere. Apẹrẹ yii example laifọwọyi ṣẹda awọn files pataki lati ṣedasilẹ ati sakojo ni Intel Quartus Prime software. O le ṣe igbasilẹ apẹrẹ akojọpọ si Igbimọ Idagbasoke FPGA rẹ. Lati ṣe igbasilẹ si ohun elo aṣa, ṣe imudojuiwọn Intel Quartus Prime Eto File (.qsf) pẹlu awọn ti o tọ pin iyansilẹ. Olusin 9. Awọn Igbesẹ Idagbasoke fun Oniru Example

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO 9001: 2015 forukọsilẹ
2.1. Ilana Ilana
olusin 10. Ilana Itọsọna fun Apẹrẹ Ti ipilẹṣẹ Example

2.2. Ti o npese awọn Design Example
olusin 11. Ilana

1. Ninu sọfitiwia Intel Quartus Prime Pro Edition, ṣẹda iṣẹ akanṣe tuntun (File ➤ New Project oso).
2. Pato Itọsọna naa, Orukọ, ati Ohun elo Ipele-oke.
3. Fun Ise agbese Iru, gba awọn aiyipada iye, Sofo ise agbese. Tẹ Itele.
4. Fun Fikun-un Files tẹ Itele.
5. Fun Ẹbi, Ẹrọ & Eto Igbimọ labẹ Ẹbi, yan Intel Agilex tabi Intel Stratix 10.
6. Ti o ba yan Intel Stratix 10 ni igbesẹ ti o kẹhin, yan Stratix 10 DX ninu atokọ fa-isalẹ Ẹrọ.
7. Yan Ẹrọ Àkọlé fun apẹrẹ rẹ.
8. Tẹ Pari.
9. Ni awọn IP Catalog wa ki o si fi awọn Intel P-Tile Avalon-ST Lile IP fun PCI Express.
10. Ninu apoti ifọrọwerọ IP tuntun, pato orukọ kan fun IP rẹ. Tẹ Ṣẹda.
11. Lori Awọn Eto Ipele-oke ati awọn taabu Eto PCIe, pato awọn paramita fun iyatọ IP rẹ. Ti o ba ti wa ni lilo SR-IOV oniru example, ṣe awọn igbesẹ wọnyi lati mu SR-IOV ṣiṣẹ:
    a. Lori taabu PCIe * Device labẹ PCIe * PCI Express / PCI Capabilities taabu, ṣayẹwo apoti Mu awọn iṣẹ ti ara lọpọlọpọ ṣiṣẹ.
    b. Lori PCIe * Multifunction ati SR-IOV Eto Eto taabu, ṣayẹwo awọn apoti Jeki SR-IOV support ki o si pato awọn nọmba ti PFs ati VFs. Fun awọn atunto x8, ṣayẹwo awọn apoti Mu awọn iṣẹ ti ara lọpọlọpọ ṣiṣẹ ati Mu atilẹyin SR-IOV ṣiṣẹ fun awọn taabu PCIe0 ati PCIe1 mejeeji.
    c. Lori taabu PCIe * MSI-X labẹ PCIe * PCI Express / PCI Capabilities taabu, mu ẹya MSI-X ṣiṣẹ bi o ṣe nilo.
    d. Lori taabu PCIe * Mimọ Adirẹsi Awọn iforukọsilẹ, mu BAR0 ṣiṣẹ fun PF ati VF mejeeji.
    e. Awọn eto paramita miiran ko ni atilẹyin fun apẹẹrẹ yiiample.
12. Lori Examptaabu Awọn apẹrẹ, ṣe awọn yiyan wọnyi:
    a. Fun Example Apẹrẹ Files, tan awọn aṣayan Simulation ati Synthesis.
    Ti o ko ba nilo kikopa tabi iṣelọpọ wọnyi files, nlọ awọn ti o baamu aṣayan (s) ni pipa significantly din awọn example oniru iran akoko.
    b. Fun Ọna kika HDL ti ipilẹṣẹ, Verilog nikan wa ni idasilẹ lọwọlọwọ.
    c. Fun Apo Idagbasoke Àkọlé, yan boya Intel Stratix 10 DX P-Tile ES1 FPGA Apo Idagbasoke, Intel Stratix 10 DX P-Tile Production FPGA Development Apo tabi Intel Agilex F-Series P-Tile ES0 FPGA Apo Idagbasoke.
    13. Yan ina Eksample Apẹrẹ lati ṣẹda kan oniru example ti o le ṣedasilẹ ati ki o gba lati ayelujara si hardware. Ti o ba yan ọkan ninu awọn igbimọ idagbasoke P-Tile, ẹrọ ti o wa lori igbimọ naa tun kọwe ẹrọ ti a ti yan tẹlẹ ninu iṣẹ Intel Quartus Prime ti awọn ẹrọ ba yatọ. Nigbati awọn tọ béèrè o lati pato awọn liana fun nyin Mofiampfun apẹrẹ, o le gba itọsọna aiyipada, ./intel_pcie_ptile_ast_0_example_design, tabi yan itọsọna miiran.
    Olusin 12. Example Awọn aṣa Tab
    
13. Tẹ Pari. O le fipamọ .ip rẹ file nigbati o ba ṣetan, ṣugbọn kii ṣe dandan lati ni anfani lati lo example apẹrẹ.
14. Ṣii example oniru ise agbese.
15. Ṣe akopọ example oniru ise agbese lati se ina awọn .sof file fun pipe example apẹrẹ. Eyi file jẹ ohun ti o ṣe igbasilẹ si igbimọ kan lati ṣe ijẹrisi ohun elo.
16. Pa rẹ Mofiample oniru ise agbese.
    Ṣe akiyesi pe o ko le yi awọn ipin pin PCIe pada ninu iṣẹ Intel Quartus Prime. Sibẹsibẹ, lati rọ PCB afisona, o le gba advantage ti ipadasẹhin ọna ati awọn ẹya ipadabọ polarity ni atilẹyin nipasẹ IP yii.

2.3. Simulating awọn Oniru Example
Iṣeto kikopa pẹlu lilo Awoṣe Iṣẹ-iṣẹ Bus Port Bus (BFM) lati lo P-tile Avalon Streaming IP fun PCIe (DUT) bi o ṣe han ni atẹle
olusin.
Olusin 13. Apẹrẹ PIO Example Simulation Testbench

Fun alaye diẹ sii lori testbench ati awọn modulu inu rẹ, tọka si Testbench ni oju-iwe 15.
Aworan sisan ti o tẹle n fihan awọn igbesẹ lati ṣe simulate apẹrẹ example:
Olusin 14. Ilana

1.  Yipada si iwe ilana kikopa testbench, / pcie_ed_tb/pcie_ed_tb/sim/ / simulator.
2. Ṣiṣe awọn iwe afọwọkọ kikopa fun simulator ti o fẹ. Tọkasi tabili ni isalẹ.
3. Ṣe itupalẹ awọn abajade.

Akiyesi: P-Tile ko ṣe atilẹyin awọn iṣeṣiro PIPE ti o jọra.
Tabili 1. Igbesẹ lati Ṣiṣe Simulation

Simulator	Ṣiṣẹ Directory	Awọn ilana
ModelSim * SE, Siemens * EDA QuestaSim * - Intel FPGA Edition	<example_design>/pcie_ed_tb/ pcie_ed_tb/sim/imọran/	1. Pe vsim (nipa titẹ vsim, eyiti o mu window console kan wa nibiti o le ṣiṣe awọn aṣẹ wọnyi). 2. ṣe msim_setup.tcl Akiyesi: Ni omiiran, dipo ṣiṣe Igbesẹ 1 ati 2, o le tẹ: vsim -c -do msim_setup.tcl. 3. ld_debug 4. run -gbogbo 5. Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle, “Ifarawe duro nitori ipari aṣeyọri!”
VCS*	<example_design>/pcie_ed_tb/ pcie_ed_tb/sim/synopsys/vcs	1. Iru sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS=””USER_DEFINED_ELAB_OPTIONS=”-xlrm\ uniq_prior_final”USER_DEFINED_SIM_OPTIONS=”
tesiwaju…

Simulator	Ṣiṣẹ Directory	Awọn ilana
		Akiyesi: Aṣẹ ti o wa loke jẹ aṣẹ laini ẹyọkan. 2. Simulation aṣeyọri pari pẹlu ifiranṣẹ atẹle, “Ifarawe duro nitori ipari aṣeyọri!” Akiyesi: Lati ṣiṣẹ kikopa ni ipo ibaraenisepo, lo awọn igbesẹ wọnyi: (ti o ba ti ṣe ipilẹṣẹ simv ti o ṣiṣẹ tẹlẹ ni ipo ibaraenisepo, paarẹ simv ati simv.diadir) 1. Ṣii vcs_setup.sh file ki o si fi aṣayan yokokoro kan kun si aṣẹ VCS: vcs -debug_access+r 2. Ṣe akopọ apẹrẹ example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS=”- xlrm uniq_prior_final” SKIP_SIM=1 3. Bẹrẹ kikopa ni ipo ibaraenisepo: simv -gui &

Testbench yii ṣe simulates titi di iyatọ Gen4 x16 kan.
Awọn ijabọ kikopa naa, “Simulation duro nitori ipari aṣeyọri” ti ko ba si awọn aṣiṣe.
2.3.1. Testbench
Testbench nlo module awakọ idanwo kan, altpcietb_bfm_rp_gen4_x16.sv, lati bẹrẹ iṣeto ni ati awọn iṣowo iranti. Ni ibẹrẹ, module awakọ idanwo n ṣafihan alaye lati Gbongbo Port ati Awọn iforukọsilẹ Aye Iṣeto Ipari, ki o le ṣe ibamu si awọn aye ti o ṣalaye nipa lilo Olootu Parameter.
Awọn example oniru ati testbench ti wa ni agbara ti ipilẹṣẹ da lori awọn iṣeto ni ti o yan fun P-Tile IP fun PCIe. Awọn testbench nlo awọn paramita ti o pato ninu Olootu Parameter ni Intel Quartus Prime. Eleyi testbench simulates soke to a ×16 PCI Express ọna asopọ lilo ni tẹlentẹle PCI Express ni wiwo. Apẹrẹ testbench jẹ ki ọna asopọ PCI Express diẹ sii ju ọkan lọ lati ṣe adaṣe ni akoko kan. Nọmba ti o tẹle ṣe afihan ipele giga view ti apẹrẹ PIO example.
Olusin 15. Apẹrẹ PIO Example Simulation Testbench

Ipele oke ti testbench ṣe afihan awọn modulu akọkọ wọnyi:

• altpcietb_bfm_rp_gen4x16.sv —Eyi ni Gbongbo Port PCIe BFM.
  // Itọsọna ọna
  / intel_pcie_ptile_ast_0_example_design/pcie_ed_tb/ip/
  pcie_ed_tb/dut_pcie_tb_ip/intel_pcie_ptile_tbed_ / SIM
• pcie_ed_dut.ip: Eyi ni apẹrẹ Ipari pẹlu awọn aye ti o pato.
  // Itọsọna ọna
  / intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
• pcie_ed_pio0.ip: module yii jẹ ibi-afẹde ati olupilẹṣẹ ti awọn iṣowo fun apẹrẹ PIO example.
  // Itọsọna ọna
  / intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
• pcie_ed_sriov0.ip: module yii jẹ ibi-afẹde ati olupilẹṣẹ ti awọn iṣowo fun apẹrẹ SR-IOV tẹlẹample.
  // Itọsọna ọna
  / intel_pcie_ptile_ast_0_example_design/ip/pcie_ed

Olusin 16. SR-IOV Oniru Eksample Simulation Testbench

Ni afikun, testbench ni awọn ilana ṣiṣe ti o ṣe awọn iṣẹ ṣiṣe wọnyi:

• Ṣe ina aago itọkasi fun aaye Ipari ni igbohunsafẹfẹ ti a beere.
• Pese PCI Express tun ni ibere soke.

Fun awọn alaye diẹ sii lori Gbongbo Port BFM, tọka si ipin TestBench ti Intel FPGA P-Tile Avalon ṣiṣanwọle IP fun Itọsọna olumulo PCI Express.
Alaye ti o jọmọ
Intel FPGA P-Tile Avalon sisanwọle IP fun PCI Express User Itọsọna
2.3.1.1. Idanwo Driver Module
Module awakọ idanwo, intel_pcie_ptile_tbed_hwtcl.v, ṣe afihan BFM toplevel, altpcietb_bfm_top_rp.v.
BFM ipele-oke pari awọn iṣẹ ṣiṣe wọnyi:

1. Instantiates awọn iwakọ ati atẹle.
2. Instantiates awọn Gbongbo Port BFM.
3. Instantiates ni tẹlentẹle ni wiwo.

Module iṣeto ni, altpcietb_g3bfm_configure.v, ṣe awọn iṣẹ ṣiṣe wọnyi:

1. Tunto ati fi awọn igi.
2. Tunto Gbongbo Port ati Endpoint.
3. Ṣe afihan aaye Iṣeto ni kikun, BAR, MSI, MSI-X, ati awọn eto AER.

2.3.1.2. Apẹrẹ PIO Example Testbench

Nọmba ti o wa ni isalẹ fihan apẹrẹ PIO example kikopa oniru logalomomoise. Awọn idanwo fun apẹrẹ PIO example ti wa ni asọye pẹlu paramita apps_type_hwtcl ṣeto si
3. Awọn igbeyewo ṣiṣe labẹ yi paramita iye ti wa ni telẹ ni ebfm_cfg_rp_ep_rootport, find_mem_bar ati downstream_loop.
olusin 17. PIO Design Example Simulation Design logalomomoise

Testbench bẹrẹ pẹlu ikẹkọ ọna asopọ ati lẹhinna wọle si aaye iṣeto ti IP fun kika. Iṣẹ-ṣiṣe ti a npe ni downstream_loop (ti a ṣalaye ni Gbongbo Port
PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) lẹhinna ṣe idanwo ọna asopọ PCIe. Idanwo yii ni awọn igbesẹ wọnyi:

1. Pese aṣẹ kikọ iranti kan lati kọ dword kan ti data sinu iranti on-chip lẹhin Ipari.
2. Pese pipaṣẹ kika iranti lati ka data pada lati iranti ori-chip.
3. Ṣe afiwe data kika pẹlu data kikọ. Ti wọn ba baramu, idanwo naa ka eyi bi Pass.
4. Tun Igbesẹ 1, 2 ati 3 ṣe fun awọn aṣetunṣe 10.

Akọsilẹ iranti akọkọ waye ni ayika 219 us. O tẹle pẹlu iranti kika ni wiwo Avalon-ST RX ti P-tile Hard IP fun PCIe. Ipari TLP yoo han ni kete lẹhin ibeere kika iranti ni wiwo Avalon-ST TX.
2.3.1.3. SR-IOV Oniru Eksample Testbench
Nọmba ti o wa ni isalẹ fihan apẹrẹ SR-IOVample kikopa oniru logalomomoise. Awọn idanwo fun apẹrẹ SR-IOV example ṣe nipasẹ iṣẹ ti a pe ni sriov_test,
eyi ti o ti telẹ ni altpcietb_bfm_cfbp.sv.
Olusin 18. SR-IOV Oniru Eksample Simulation Design logalomomoise

SR-IOV testbench ṣe atilẹyin fun awọn iṣẹ ṣiṣe ti ara meji (PFs) ati 32 Foju Awọn iṣẹ (VFs) fun PF.
Testbench bẹrẹ pẹlu ikẹkọ ọna asopọ ati lẹhinna wọle si aaye iṣeto ti IP fun kika. Lẹhin iyẹn, o ṣe awọn igbesẹ wọnyi:

1. Fi ibeere kikọ iranti ranṣẹ si PF atẹle nipa ibeere kika iranti lati ka data kanna pada fun lafiwe. Ti data kika ba baamu data kikọ, o jẹ
   a Pass. Idanwo yii jẹ ṣiṣe nipasẹ iṣẹ ṣiṣe ti a pe ni my_test (ti a ṣalaye ni altpcietb_bfm_cfbp.v). Idanwo yii tun ṣe lẹmeji fun PF kọọkan.
2. Fi ibeere kikọ iranti ranṣẹ si VF atẹle nipa ibeere kika iranti lati ka data kanna pada fun lafiwe. Ti data kika ba baamu data kikọ, o jẹ
   a Pass. Idanwo yii jẹ ṣiṣe nipasẹ iṣẹ ṣiṣe ti a pe ni cfbp_target_test (ti a ṣalaye ni altpcietb_bfm_cfbp.v). Idanwo yii tun ṣe fun VF kọọkan.

Akọsilẹ iranti akọkọ waye ni ayika 263 us. O tẹle pẹlu iranti kika ni wiwo Avalon-ST RX ti PF0 ti P-tile Hard IP fun PCIe. Ipari TLP yoo han ni kete lẹhin ibeere kika iranti ni wiwo Avalon-ST TX.
2.4. Iṣakojọpọ Oniru Example

1. Lilö kiri si / intel_pcie_ptile_ast_0_example_design/ ati ki o ṣii pcie_ed.qpf.
2. Ti o ba yan boya ninu awọn ohun elo idagbasoke meji ti o tẹle, awọn eto ti o jọmọ VID wa ninu .qsf file ti ipilẹṣẹ apẹrẹ example, ati awọn ti o ti wa ni ko ti beere lati fi wọn pẹlu ọwọ. Ṣe akiyesi pe awọn eto wọnyi jẹ igbimọ-pato.
   • Intel Stratix 10 DX P-Tile ES1 FPGA ohun elo idagbasoke
   • Intel Stratix 10 DX P-Tile Production FPGA idagbasoke ohun elo
   • Intel Agilex F-Series P-Tile ES0 FPGA ohun elo idagbasoke
3. Lori akojọ aṣayan Ṣiṣe, yan Bẹrẹ Iṣakojọpọ.

2.5. Fifi sori ẹrọ Awakọ Kernel Linux

Ṣaaju ki o to le idanwo awọn oniru example ni hardware, o gbọdọ fi sori ẹrọ ni Linux ekuro
awako. O le lo awakọ yii lati ṣe awọn idanwo wọnyi:
• A PCIe ọna asopọ igbeyewo ti o ṣe 100 kikọ ki o si ka
• Aaye iranti DWORD
ka ati ki o kọ
• Aaye iṣeto ni DWORD ka ati kọ
(1)
Ni afikun, o le lo awakọ lati yi iye ti awọn paramita wọnyi pada:
• Bar ti wa ni lilo
• Ẹrọ ti o yan (nipa sisọ awọn nọmba bosi, ẹrọ ati iṣẹ (BDF) fun
ẹrọ)
Pari awọn igbesẹ wọnyi lati fi awakọ kernel sori ẹrọ:

1. Lilö kiri si ./software/kernel/linux labẹ example oniru iran liana.
2. Yi awọn igbanilaaye pada lori fifi sori ẹrọ, fifuye, ati gbejade files:
   $ chmod 777 fi sori ẹrọ fifuye unload
3. Fi sori ẹrọ awakọ naa:
   $ sudo ./fi sori ẹrọ
4. Ṣayẹwo fifi sori ẹrọ awakọ naa:
   $ lsmod | grep intel_fpga_pcie_drv
   Abajade ti a nireti:
   intel_fpga_pcie_drv 17792 0
5. Daju pe Lainos mọ apẹrẹ PCIe example:
   $ lspci -d 1172:000 -v | grep intel_fpga_pcie_drv
   Akiyesi: Ti o ba ti yi ID ataja pada, rọpo ID ataja tuntun fun ti Intel
   ID ataja ni aṣẹ yii.
   Abajade ti a nireti:
   Kernel iwakọ ni lilo: intel_fpga_pcie_drv

2.6. Ṣiṣe awọn Oniru Example
Eyi ni awọn iṣẹ idanwo ti o le ṣe lori apẹrẹ P-Tile Avalon-ST PCIe example:

1. Jakejado itọsọna olumulo yii, awọn ọrọ ọrọ, DWORD ati QWORD ni itumọ kanna ti wọn ni ni pato Ipilẹ Ipilẹ PCI Express. Ọrọ kan jẹ awọn bit 16, DWORD jẹ 32 bits, ati pe QWORD jẹ 64 bits.

Table 2. Idanwo Mosi Atilẹyin nipasẹ awọn P-Tile Avalon-ST PCIe Design Examples

Awọn iṣẹ ṣiṣe	Igi ti a beere	Atilẹyin nipasẹ P-Tile Avalon-ST PCIe Design Example
0: Ayẹwo ọna asopọ - 100 kọ ati ka	0	Bẹẹni
1: Kọ aaye iranti	0	Bẹẹni
2: Ka aaye iranti	0	Bẹẹni
3: Kọ aaye iṣeto ni	N/A	Bẹẹni
4: Ka aaye iṣeto ni	N/A	Bẹẹni
5: Iyipada Pẹpẹ	N/A	Bẹẹni
6: Yi ẹrọ pada	N/A	Bẹẹni
7: Jeki SR-IOV	N/A	Bẹẹni (*)
8: Ṣe idanwo ọna asopọ fun gbogbo iṣẹ foju ti o ṣiṣẹ ti o jẹ ti ẹrọ lọwọlọwọ	N/A	Bẹẹni (*)
9: Ṣe DMA	N/A	Rara
10: Olodun-eto	N/A	Bẹẹni

Akiyesi: (*) Awọn iṣẹ idanwo wọnyi wa nikan nigbati apẹrẹ SR-IOV example ti yan.
2.6.1. Ṣiṣe awọn PIO Design Example

1. Lilö kiri si ./software/user/example labẹ apẹrẹ example liana.
2. Ṣe akopọ apẹrẹ example elo:
   $ ṣe
3. Ṣiṣe idanwo naa:
   $ sudo ./intel_fpga_pcie_link_test
   O le ṣiṣe idanwo ọna asopọ Intel FPGA IP PCIe ni afọwọṣe tabi ipo adaṣe. Yan lati:
   • Ni ipo aifọwọyi, ohun elo yoo yan ẹrọ laifọwọyi. Idanwo naa yan ẹrọ Intel PCIe pẹlu BDF ti o kere julọ nipa ibaramu ID ataja naa.
   Idanwo naa tun yan BAR to wa ni asuwon ti.
   Ni ipo afọwọṣe, idanwo naa beere lọwọ rẹ fun ọkọ akero, ẹrọ, nọmba iṣẹ ati BAR.
   Fun Intel Stratix 10 DX tabi Intel Agilex Development Apo, o le pinnu awọn
   BDF nipa titẹ aṣẹ wọnyi:
   $ lspci -d 1172:
   4. Eyi ni sampawọn iwe afọwọkọ fun adaṣe ati awọn ipo afọwọṣe:
   Ipo aifọwọyi:

Ipo afọwọṣe:

Alaye ti o jọmọ
PCIe Link Oluyewo Loriview
Lo Oluyewo Ọna asopọ PCIe lati ṣe atẹle ọna asopọ ni Ti ara, Ọna asopọ Data ati Awọn Layer Idunadura.
2.6.2. Nṣiṣẹ SR-IOV Design Example

Eyi ni awọn igbesẹ lati ṣe idanwo apẹrẹ SR-IOV example lori hardware:

1. Ṣiṣe idanwo ọna asopọ Intel FPGA IP PCIe nipasẹ ṣiṣe sudo ./
   intel_fpga_pcie_link_test pipaṣẹ ati lẹhinna yan aṣayan 1:
   Yan ẹrọ pẹlu ọwọ.
2. Tẹ BDF ti iṣẹ ti ara fun eyiti a ti pin awọn iṣẹ foju.
3. Tẹ BAR "0" lati tẹsiwaju si akojọ aṣayan idanwo.
4. Tẹ aṣayan 7 sii lati mu SR-IOV ṣiṣẹ fun ẹrọ lọwọlọwọ.
5. Tẹ nọmba awọn iṣẹ foju sii lati muu ṣiṣẹ fun ẹrọ lọwọlọwọ.
   
6. Tẹ aṣayan 8 sii lati ṣe idanwo ọna asopọ fun gbogbo iṣẹ foju ti o ṣiṣẹ ti a pin fun iṣẹ ti ara. Ohun elo idanwo ọna asopọ yoo ṣe awọn kikọ iranti 100 pẹlu dword kan ti data kọọkan ati lẹhinna ka data naa pada fun ṣayẹwo. Ohun elo naa yoo tẹjade nọmba awọn iṣẹ foju ti o kuna idanwo ọna asopọ ni ipari idanwo naa.
   7. Ni titun kan ebute, ṣiṣe awọn lspci –d 1172: | grep -c “Altera” pipaṣẹ lati mọ daju awọn kika ti PFs ati VFs. Abajade ti a nireti ni apapọ nọmba awọn iṣẹ ti ara ati nọmba awọn iṣẹ foju.

P-tile Avalon śiśanwọle IP fun PCI Express Design

Example User Itọsọna Archives

Intel Quartus NOMBA Version	Itọsọna olumulo
21.2	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna
20.3	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna
20.2	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna
20.1	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna
19.4	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna
19.1.1	P-tile Avalon śiśanwọle IP fun PCI Express Design Eksample User Itọsọna

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO
9001:2015
Iforukọsilẹ

Itan Atunyẹwo iwe fun Intel P-Tile Avalon

Sisanwọle Lile IP fun PCIe Design Example User Itọsọna

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Ẹya IP	Awọn iyipada
2021.10.04	21.3	6.0.0	Yi pada awọn atunto atilẹyin fun SR-IOV oniru example lati Gen3 x16 EP ati Gen4 x16 EP si Gen3 x8 EP ati Gen4 x8 EP ni Apejuwe Iṣẹ-ṣiṣe fun Gbongbo I/O Nikan (SR-IOV) Apẹrẹ Example apakan. Ṣe afikun atilẹyin fun Intel Stratix 10 DX P-tile Production FPGA Apo Idagbasoke si Ṣiṣẹda Apẹrẹ Example apakan.
2021.07.01	21.2	5.0.0	Yọ awọn ọna igbi kikopa kuro fun apẹrẹ PIO ati SR-IOV examples lati apakan Simulating awọn Design Example. Ṣe imudojuiwọn aṣẹ lati ṣafihan BDF ni apakan Ṣiṣe awọn PIO Design Example.
2020.10.05	20.3	3.1.0	Yọ apakan awọn iforukọsilẹ kuro lati igba apẹrẹ Avalon ṣiṣanwọle examples ni ko si Iṣakoso Forukọsilẹ.
2020.07.10	20.2	3.0.0	Awọn ọna igbi kikopa ti a ṣafikun, awọn apejuwe ọran idanwo ati awọn apejuwe abajade idanwo fun apẹrẹ apẹẹrẹamples. Awọn ilana iṣeṣiro ti a ṣafikun fun Simulator ModelSim si Simulating the Design Example apakan.
2020.05.07	20.1	2.0.0	Ṣe imudojuiwọn akọle iwe-ipamọ si Intel FPGA P-Tile Avalon ṣiṣanwọle IP fun PCI Express Design Example Itọsọna Olumulo lati pade awọn ilana isọkọ ofin titun. Ṣe imudojuiwọn aṣẹ kikopa ipo ibaraenisepo VCS.
2019.12.16	19.4	1.1.0	Fi kun SR-IOV oniru example apejuwe.
2019.11.13	19.3	1.0.0	Fikun Gen4 x8 Endpoint ati Gen3 x8 Endpoint si atokọ ti awọn atunto atilẹyin.
2019.05.03	19.1.1	1.0.0	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.
ISO
9001:2015
Iforukọsilẹ

Idajọ Ayelujara
Fi esi ranṣẹ
ID: 683038
UG-20234
Ẹya: 2021.10.04

Awọn iwe aṣẹ / Awọn orisun

intel FPGA P-Tile Avalon śiśanwọle IP fun PCI Express Design Eksample [pdf] Itọsọna olumulo FPGA P-Tile, Avalon śiśanwọle IP fun PCI Express Design Eksample, FPGA P-Tile Avalon śiśanwọle IP fun PCI Express Design Eksample, FPGA P-Tile Avalon śiśanwọle IP

Awọn itọkasi

• Itọsọna olumulo