F Tile Serial Lite IV Intel FPGA IP Itọsọna olumulo

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1 F Tile Serial Lite IV Intel FPGA IP

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F Tile Serial Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo
Imudojuiwọn fun Intel® Quartus® Prime Design Suite: 22.1 IP Ẹya: 5.0.0

Online Version Fi esi

UG-20324

ID: 683074 Ẹya: 2022.04.28

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1. Nipa F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Loriview…………………………………………………………………………. 6 2.1. Alaye itusilẹ………………………………………………………………………………………………………………….7 2.2. Awọn ẹya ti a ṣe atilẹyin………………………………………………………………………………………………………….. 7 2.3. Ipele Atilẹyin Ẹya IP………………………………………………………………………………………………….8 2.4. Atilẹyin Iyara Ohun elo ………………………………………………………………………………………………….8 2.5. Lilo Awọn orisun ati Aiduro………………………………………………………………………………………………………… 9 2.6. Iṣiṣẹ Bandiwidi ………………………………………………………………………………………………………………… 9
3. Bibẹrẹ………………………………………………………………………………………………………………………. 11 3.1. Fifi sori ẹrọ ati Gbigba iwe-aṣẹ Intel FPGA IP Cores………………………………………………………………………………. Ipo Igbelewọn IP FPGA IP………………………………………………………………………………. 11 3.1.1. Pato Awọn paramita IP ati Awọn aṣayan……………………………………………………………………………………………………… Ti ipilẹṣẹ File Igbekale………………………………………………………………………………………………………………………………………… Simulating Intel FPGA IP Cores……………………………………………………………………………………………………………… 14 3.4. Simularada ati Imudaniloju Oniru naa………………………………………………………………. 16 3.4.1. Ṣiṣẹpọ Awọn Koko IP ni Awọn Irinṣẹ EDA miiran …………………………………………………………………………. 17 3.5. Ṣe akopọ apẹrẹ ni kikun .....................................................................................................
4. Apejuwe isẹ……………………………………………………………………………………………………………………….. 19 4.1. Ọna Data TX……………………………………………………………………………………………………………….20 4.1.1. TX MAC Adapter……………………………………………………………………………………………….. 21 4.1.2. Ọrọ Iṣakoso (CW) Fi sii ………………………………………………………………………………… 23 4.1.3. TX CRC………………………………………………………………………………………………………………………………………………………… Ayipada TX MII……………………………………………………………………………………………….28 4.1.4. TX PCS ati PMA……………………………………………………………………………………………………….. 29 4.1.5. Ọna data RX ………………………………………………………………………………………………………………… 30 4.2. RX PCS ati PMA……………………………………………………………………………………………………….. 30 4.2.1. RX MII Decoder……………………………………………………………………………………………………………… 31 4.2.2. RX CRC………………………………………………………………………………………………………………….. 31 4.2.3. RX Deskew……………………………………………………………………………………………………………….31 4.2.4. Yiyọ RX CW kuro…………………………………………………………………………………………………………………………… 32 4.2.5. F-Tile Serial Lite IV Intel FPGA IP Architecture Architecture………………………………………………………. 35 4.3. Tunto ati Ibẹrẹ Ọna asopọ …………………………………………………………………………………………..36 4.4. Atunto TX ati Ibẹrẹ Ibẹrẹ………………………………………………………………. 37 4.4.1. Atunto RX ati Ibẹrẹ Ibẹrẹ………………………………………………………………. 38 4.4.2. Oṣuwọn Ọna asopọ ati Iṣiro Iṣeṣe Bandiwidi……………………………………………………………………….. 39
5. Awọn paramita…………………………………………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Awọn ifihan agbara Ni wiwo……………………………………………………………………….. 44 6.1. Awọn ifihan agbara aago……………………………………………………………………………………………………………………………….44 6.2. Awọn ifihan agbara Tunto………………………………………………………………………………………………………………………………………………………… 44 6.3. Awọn ifihan agbara MAC ………………………………………………………………………………………………………………….. 45 6.4. Awọn ifihan agbara atunto Transceiver……………………………………………………………………………………… 48 6.5. Awọn ifihan agbara PMA………………………………………………………………………………………………………………………………………

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 2

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7. Apẹrẹ pẹlu F-Tile Serial Lite IV Intel FPGA IP………………………………………………………………………………… Awọn Itọsọna Tunto……………………………………………………………………………………………………….. 51 7.1. Awọn Itọsọna Mimu Aṣiṣe …………………………………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP Itọsọna Olumulo Awọn ile ifipamọ………………………………………………………. 52 9. Itan Atunyẹwo Iwe-ipamọ fun F-Tile Serial Lite IV Itọnisọna Olumulo IP Intel FPGA………53

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F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 3

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1. Nipa F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo

Iwe yii ṣe apejuwe awọn ẹya IP, apejuwe faaji, awọn igbesẹ lati ṣe ipilẹṣẹ, ati awọn itọnisọna lati ṣe apẹrẹ F-Tile Serial Lite IV Intel® FPGA IP ni lilo awọn transceivers F-tile ni awọn ẹrọ Intel AgilexTM.

Olugbo ti a pinnu

Iwe yii jẹ ipinnu fun awọn olumulo wọnyi:
· Awọn ayaworan ile apẹrẹ lati ṣe yiyan IP lakoko ipele igbero eto-ipele
· Hardware apẹẹrẹ nigba ti o ṣepọ awọn IP sinu wọn eto-ipele oniru
· Awọn onimọ-ẹrọ afọwọsi lakoko kikopa ipele-eto ati awọn ipele afọwọsi ohun elo

Awọn iwe aṣẹ ti o jọmọ

Tabili ti o tẹle ṣe atokọ awọn iwe itọkasi miiran ti o ni ibatan si F-Tile Serial Lite IV Intel FPGA IP.

Tabili 1.

Awọn iwe aṣẹ ti o jọmọ

Itọkasi

F-Tile Serial Lite IV Intel FPGA IP Design Eksample User Itọsọna

Intel Agilex Device Data Dì

Apejuwe
Iwe yii n pese iran, awọn itọnisọna lilo, ati apejuwe iṣẹ ti F-Tile Serial Lite IV Intel FPGA IP apẹrẹ examples ni Intel Agilex awọn ẹrọ.
Iwe yii ṣe apejuwe awọn abuda itanna, awọn abuda iyipada, awọn pato iṣeto, ati akoko fun awọn ẹrọ Intel Agilex.

Tabili 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms ati Gilosari Acronym Akojọ
Adape

Imugboroosi Iṣakoso Ọrọ Reed-Solomon Aṣiṣe Aṣiṣe Atunse Ti ara Alabọde Asomọ Olugba Olugba Pulse-Amplitude Modulation 4-Level Non-pada-si-odo

tesiwaju…

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

ISO 9001: 2015 forukọsilẹ

1. Nipa F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 683074 | 2022.04.28

PCS MII XGMII

Adape

Imugboroosi ti ara ifaminsi Sublayer Media Independent Interface 10 Gigabit Media olominira Interface

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F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 5

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2. F-Tile Serial Lite IV Intel FPGA IP Loriview

Olusin 1.

F-Tile Serial Lite IV Intel FPGA IP dara fun ibaraẹnisọrọ data bandiwidi giga fun chirún-si-chip, igbimọ-si-ọkọ, ati awọn ohun elo afẹyinti.

F-Tile Serial Lite IV Intel FPGA IP ṣafikun iṣakoso iwọle media (MAC), sublayer ifaminsi ti ara (PCS), ati asomọ media ti ara (PMA) awọn bulọọki. IP naa ṣe atilẹyin awọn iyara gbigbe data ti o to 56 Gbps fun ọna kan pẹlu iwọn ti awọn ọna PAM4 mẹrin tabi 28 Gbps fun ọna kan pẹlu iwọn awọn ọna 16 NRZ. IP yii nfunni ni bandiwidi giga, awọn fireemu ori kekere, kika I/O kekere, ati atilẹyin iwọn giga ni awọn nọmba mejeeji ti awọn ọna ati iyara. IP yii tun jẹ atunto ni irọrun pẹlu atilẹyin ti ọpọlọpọ awọn oṣuwọn data pẹlu ipo PCS Ethernet ti transceiver F-tile.

IP yii ṣe atilẹyin awọn ọna gbigbe meji:
· Ipo ipilẹ-Eyi jẹ ipo ṣiṣanwọle mimọ nibiti a ti fi data ranṣẹ laisi apo-ibẹrẹ, ọmọ sofo, ati apo-ipari lati mu bandiwidi pọ si. IP gba data to wulo akọkọ bi ibẹrẹ ti nwaye.
Ipo ni kikun-Eyi jẹ ipo gbigbe apo kan. Ni ipo yii, IP nfi fifẹ kan ranṣẹ ati iyipo amuṣiṣẹpọ ni ibẹrẹ ati ipari ti apo kan bi awọn alapin.

F-Tile Serial Lite IV High Ipele Àkọsílẹ aworan atọka

Avalon śiśanwọle Interface TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64*n awọn ọna opopona (ipo NRZ) / 2 * n awọn ọna die-die (ipo PAM4)

TX MAC

Adapter INSERT

MII ENCODE

PCS aṣa

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (ipo PAM4)/ n Awọn ọna Bits (ipo NRZ)
TX Serial Interface

Avalon śiśanwọle Interface RX
64*n awọn ọna opopona (ipo NRZ) / 2 * n awọn ọna die-die (ipo PAM4)

RX PCS

CW RMV

DESKEW

MII

& TUNTUN DECODE

RX MII

EMIB

DECODE BLOCK SYNC & FEC DESCRAMBLER

RX PMA

CSR

2n Awọn ọna Bits (ipo PAM4)/ n Awọn ọna Bits (ipo NRZ) RX Ni wiwo Serial
Avalon Memory-Mapped Interface Forukọsilẹ Config

Àlàyé

Asọ kannaa

Lile kannaa

ISO 9001: 2015 forukọsilẹ

2. F-Tile Serial Lite IV Intel FPGA IP Loriview 683074 | 2022.04.28

O le ṣe ina F-Tile Serial Lite IV Intel FPGA IP design examplati ni imọ siwaju sii nipa awọn ẹya IP. Tọkasi F-Tile Serial Lite IV Intel FPGA IP Design Example User Itọsọna.
Alaye ti o jọmọ · Apejuwe iṣẹ ṣiṣe loju iwe 19 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Itọsọna

2.1. Alaye Tu silẹ

Awọn ẹya Intel FPGA IP ibaamu awọn ẹya sọfitiwia Intel Quartus® Prime Design Suite titi di v19.1. Bibẹrẹ ni Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2, Intel FPGA IP ni ero ti ikede tuntun kan.

Nọmba Intel FPGA IP ẹya (XYZ) le yipada pẹlu ẹya sọfitiwia Intel Quartus Prime kọọkan. Iyipada ninu:

· X tọkasi atunyẹwo pataki ti IP. Ti o ba ṣe imudojuiwọn sọfitiwia Intel Quartus Prime, o gbọdọ tun IP ṣe.
· Y tọkasi IP pẹlu awọn ẹya tuntun. Tun IP rẹ ṣe lati ni awọn ẹya tuntun wọnyi.
· Z tọkasi IP pẹlu awọn ayipada kekere. Tun IP rẹ ṣe lati fi awọn ayipada wọnyi kun.

Tabili 3.

F-Tile Serial Lite IV Intel FPGA IP Tu Alaye

Nkan IP Version Intel Quartus Prime Version Tu Ọjọ Pipa koodu

5.0.0 22.1 2022.04.28 IP-SLITE4F

Apejuwe

2.2. Atilẹyin Awọn ẹya ara ẹrọ
Tabili atẹle yii ṣe atokọ awọn ẹya ti o wa ni F-Tile Serial Lite IV Intel FPGA IP:

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F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 7

2. F-Tile Serial Lite IV Intel FPGA IP Loriview 683074 | 2022.04.28

Tabili 4.

F-Tile Serial Lite IV Intel FPGA IP Awọn ẹya ara ẹrọ

Ẹya ara ẹrọ

Apejuwe

Data Gbigbe

Fun ipo PAM4:
- FHT ṣe atilẹyin nikan 56.1, 58, ati 116 Gbps fun ọna kan pẹlu iwọn awọn ọna 4 ti o pọju.
- FGT ṣe atilẹyin to 58 Gbps fun ọna kan pẹlu o pọju awọn ọna 12.
Tọkasi Tabili 18 loju iwe 42 fun awọn alaye diẹ sii lori awọn oṣuwọn data transceiver atilẹyin fun ipo PAM4.
Fun ipo NRZ:
- FHT ṣe atilẹyin nikan 28.05 ati 58 Gbps fun ọna kan pẹlu iwọn awọn ọna 4 ti o pọju.
- FGT n ṣe atilẹyin to 28.05 Gbps fun ọna kan pẹlu o pọju awọn ọna 16.
Tọkasi Tabili 18 loju iwe 42 fun awọn alaye diẹ sii lori awọn oṣuwọn data transceiver atilẹyin fun ipo NRZ.
· Atilẹyin lemọlemọfún sisanwọle (Ipilẹ) tabi soso (Full) igbe.
· Atilẹyin kekere lori fireemu awọn apo-iwe.
· Atilẹyin gbigbe granularity baiti fun gbogbo iwọn ti nwaye.
· Atilẹyin ti ipilẹṣẹ olumulo tabi titete ọna aladaaṣe.
· Ṣe atilẹyin akoko titete eto.

PCS

· Nlo lile IP kannaa ti o ni atọkun pẹlu Intel Agilex F-tile transceivers fun asọ kannaa awọn oluşewadi idinku.
Ṣe atilẹyin ipo iṣatunṣe PAM4 fun sipesifikesonu 100GBASE-KP4. RS-FEC ti ṣiṣẹ nigbagbogbo ni ipo awose yii.
· Atilẹyin NRZ pẹlu iyan RS-FEC modulation mode.
Ṣe atilẹyin 64b/66b fifi koodu iyipada.

Wiwa aṣiṣe ati mimu

Ṣe atilẹyin aṣiṣe CRC lori awọn ọna data TX ati RX. · Atilẹyin RX ọna asopọ aṣiṣe yiyewo. · Ṣe atilẹyin wiwa aṣiṣe RX PCS.

Awọn atọkun

· Atilẹyin nikan ni kikun ile oloke meji gbigbe soso pẹlu ominira ìjápọ.
· Nlo interconnect point-si-point si ọpọ awọn ẹrọ FPGA pẹlu lairi gbigbe kekere.
· Atilẹyin olumulo-telẹ ase.

2.3. IP Version Support Ipele

Sọfitiwia Intel Quartus Prime ati atilẹyin ẹrọ Intel FPGA fun F-Tile Serial Lite IV Intel FPGA IP jẹ atẹle yii:

Tabili 5.

Ẹya IP ati Ipele Atilẹyin

Intel Quartus NOMBA 22.1

Device Intel Agilex F-tile transceivers

IP Version Simulation Compilation Hardware Design

5.0.0

2.4. Device Iyara ite Support
F-Tile Serial Lite IV Intel FPGA IP ṣe atilẹyin awọn iwọn iyara wọnyi fun awọn ẹrọ Intel Agilex F-tile: · Iwọn iyara transceiver: -1, -2, ati -3 · Iwọn iyara Core: -1, -2, ati - 3

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 8

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2. F-Tile Serial Lite IV Intel FPGA IP Loriview 683074 | 2022.04.28

Alaye ti o jọmọ
Iwe Data Ohun elo Intel Agilex Alaye diẹ sii nipa iwọn data atilẹyin ni awọn transceivers Intel Agilex F-tile.

2.5. Lilo orisun ati Lairi

Awọn orisun ati lairi fun F-Tile Serial Lite IV Intel FPGA IP ni a gba lati ẹya sọfitiwia Intel Quartus Prime Pro Edition 22.1.

Tabili 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Resource iṣamulo
Iwọn airi naa da lori airi irin ajo yika lati titẹ sii mojuto TX si iṣelọpọ mojuto RX.

Transceiver Iru

Iyatọ

Nọmba ti Data Awọn ọna Ipo RS-FEC ALM

Lairi (Yipo aago TX mojuto)

FGT

28.05 Gbps NRZ 16

Alaabo ipilẹ 21,691 65

Alaabo kikun 22,135 65

Ipilẹ ṣiṣẹ 21,915 189

Ni kikun ṣiṣẹ 22,452 189

58 Gbps PAM4 12

Ipilẹ ṣiṣẹ 28,206 146

Ni kikun ṣiṣẹ 30,360 146

FHT

58 Gbps NRZ

Ipilẹ ṣiṣẹ 15,793 146

Ni kikun ṣiṣẹ 16,624 146

58 Gbps PAM4 4

Ipilẹ ṣiṣẹ 15,771 154

Ni kikun ṣiṣẹ 16,611 154

116 Gbps PAM4 4

Ipilẹ ṣiṣẹ 21,605 128

Ni kikun ṣiṣẹ 23,148 128

2.6. Ṣiṣe Bandiwidi

Tabili 7.

Ṣiṣe Bandiwidi

Iyipada Transceiver mode

PAM4

Sisanwọle mode RS-FEC

Ṣiṣẹ ni kikun

Ipilẹ Ṣiṣẹ

Oṣuwọn ni wiwo ni tẹlentẹle ni Gbps (RAW_RATE)
Iwọn ti nwaye ti gbigbe ni nọmba ọrọ (BURST_SIZE) (1)
Àkókò ìfisọ̀rọ̀ nínú àsìkò aago (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Eto

NRZ

Ni kikun

Alaabo

Ti ṣiṣẹ

28.0

2,048

4,096

Alaabo ipilẹ 28.0

Ṣiṣẹ 28.0

4,194,304

4,096

4,096 tẹsiwaju…

(1) BURST_SIZE fun ipo Ipilẹ n sunmọ ailopin, nitorinaa nọmba nla ti lo.

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F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 9

2. F-Tile Serial Lite IV Intel FPGA IP Loriview 683074 | 2022.04.28

Awọn oniyipada

Eto

64/66b koodu

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Lori iwọn ti nwaye ni nọmba ọrọ (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Àkókò títẹ̀síwájú 81,915 ní àsìkò aago (ALIGN_MARKER_PERIOD)

81,915

81,916

Iwọn asami isọdọtun ni 5

aago ọmọ

(ALIGN_MARKER_WIDTH)

Iṣiṣẹ bandiwidi (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Oṣuwọn ti o munadoko (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Igbohunsafẹfẹ aago olumulo ti o pọju (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Oṣuwọn Ọna asopọ Alaye ti o jọmọ ati Iṣiro Iṣiṣẹ Bandiwidi ni oju-iwe 40

(2) Ni ipo ni kikun, iwọn BURST_SIZE_OVHD jẹ pẹlu START/END Awọn Ọrọ Iṣakoso so pọ ninu ṣiṣan data kan.
(3) Fun ipo Ipilẹ, BURST_SIZE_OVHD jẹ 0 nitori ko si START/END lakoko ṣiṣanwọle.
(4) Tọkasi Oṣuwọn Ọna asopọ ati Iṣiro Iṣiṣẹ Bandiwidi fun iṣiro ṣiṣe bandiwidi.
(5) Tọkasi Iwọn Ọna asopọ ati Iṣiro Iṣiṣẹ Bandiwidi fun iṣiro oṣuwọn to munadoko.
(6) Tọkasi Iwọn Ọna asopọ ati Iṣiro Iṣiṣẹ Bandiwidi fun iṣiro igbohunsafẹfẹ olumulo ti o pọju.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 10

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3. Bibẹrẹ

3.1. Fifi ati asẹ ni Intel FPGA IP ohun kohun

Fifi sori sọfitiwia Intel Quartus Prime pẹlu ile-ikawe Intel FPGA IP. Ile-ikawe yii n pese ọpọlọpọ awọn ohun kohun IP ti o wulo fun lilo iṣelọpọ rẹ laisi iwulo fun iwe-aṣẹ afikun. Diẹ ninu awọn ohun kohun Intel FPGA IP nilo rira iwe-aṣẹ lọtọ fun lilo iṣelọpọ. Ipo Igbelewọn IP FPGA Intel gba ọ laaye lati ṣe iṣiro awọn ohun kohun Intel FPGA IP ti o ni iwe-aṣẹ ni kikopa ati ohun elo, ṣaaju ṣiṣe ipinnu lati ra iwe-aṣẹ ipilẹ IP iṣelọpọ ni kikun. Iwọ nikan nilo lati ra iwe-aṣẹ iṣelọpọ ni kikun fun awọn ohun kohun Intel IP ti o ni iwe-aṣẹ lẹhin ti o pari idanwo ohun elo ati pe o ti ṣetan lati lo IP ni iṣelọpọ.

Sọfitiwia Intel Quartus Prime n fi awọn ohun kohun IP sori awọn ipo atẹle nipasẹ aiyipada:

Olusin 2.

IP mojuto fifi sori ona
intelFPGA(_pro) quartus – Ni Intel Quartus Prime sọfitiwia ip – Ni ile-ikawe Intel FPGA IP ati awọn ohun kohun IP ẹni-kẹta – Ni koodu orisun ibi ikawe Intel FPGA IP - Ni orisun Intel FPGA IP files

Tabili 8.

Awọn ipo fifi sori mojuto IP

Ipo

Software

: intelFPGA_proquartusipaltera

Intel kuotisi NOMBA Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus NOMBA Pro Edition

Windows Platform* Linux*

Akiyesi:

Sọfitiwia Intel Quartus Prime ko ṣe atilẹyin awọn aye ni ọna fifi sori ẹrọ.

3.1.1. Intel FPGA IP Igbelewọn Ipo
Ipo Igbelewọn Intel FPGA IP ọfẹ gba ọ laaye lati ṣe iṣiro awọn ohun kohun Intel FPGA IP ti o ni iwe-aṣẹ ni kikopa ati ohun elo ṣaaju rira. Ipo Igbelewọn Intel FPGA IP ṣe atilẹyin awọn igbelewọn atẹle laisi iwe-aṣẹ afikun:
Ṣe afiwe ihuwasi ti Intel FPGA IP mojuto ti o ni iwe-aṣẹ ninu eto rẹ. · Daju iṣẹ ṣiṣe, iwọn, ati iyara ti ipilẹ IP ni iyara ati irọrun. Ṣe ina siseto ẹrọ to lopin akoko files fun awọn apẹrẹ ti o ni awọn ohun kohun IP. · Ṣeto ẹrọ kan pẹlu ipilẹ IP rẹ ati rii daju apẹrẹ rẹ ni ohun elo.

ISO 9001: 2015 forukọsilẹ

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Ipo Iṣiro IP FPGA Intel ṣe atilẹyin awọn ipo iṣẹ atẹle wọnyi:
Ti a somọ – Faye gba ṣiṣe apẹrẹ ti o ni iwe-aṣẹ Intel FPGA IP lainidii pẹlu asopọ laarin igbimọ rẹ ati kọnputa agbalejo. Ipo somọ nilo ẹgbẹ iṣe idanwo apapọ kan (JTAG) okun ti a ti sopọ laarin JTAG ibudo lori ọkọ rẹ ati kọnputa agbalejo, eyiti o nṣiṣẹ Intel Quartus Prime Programmer fun iye akoko igbelewọn ohun elo. Oluṣeto nikan nilo fifi sori ẹrọ ti o kere ju ti sọfitiwia Intel Quartus Prime, ko nilo iwe-aṣẹ Intel Quartus Prime. Kọmputa agbalejo n ṣakoso akoko igbelewọn nipa fifiranṣẹ ifihan igbakọọkan si ẹrọ nipasẹ JTAG ibudo. Ti gbogbo awọn ohun kohun IP ti o ni iwe-aṣẹ ninu apẹrẹ ṣe atilẹyin ipo somọ, akoko igbelewọn n ṣiṣẹ titi igbelewọn mojuto IP eyikeyi yoo pari. Ti gbogbo awọn ohun kohun IP ṣe atilẹyin akoko igbelewọn ailopin, ẹrọ naa ko ni akoko-akoko.
· Untethered – Gba laaye lati ṣiṣẹ apẹrẹ ti o ni IP ti o ni iwe-aṣẹ fun akoko to lopin. Ipilẹ mojuto IP tun pada si ipo ti a ko sopọ ti ẹrọ naa ba ge asopọ lati kọnputa agbalejo ti nṣiṣẹ sọfitiwia Intel Quartus Prime. Kokoro IP naa tun pada si ipo ti ko sopọ ti eyikeyi ipilẹ IP ti o ni iwe-aṣẹ ninu apẹrẹ ko ṣe atilẹyin ipo somọ.
Nigbati akoko igbelewọn ba pari fun eyikeyi Intel FPGA IP ti o ni iwe-aṣẹ ninu apẹrẹ, apẹrẹ naa da iṣẹ ṣiṣe duro. Gbogbo awọn ohun kohun IP ti o lo Intel FPGA IP Ipo Igbelewọn akoko jade ni nigbakannaa nigbati eyikeyi IP mojuto ninu awọn akoko apẹrẹ jade. Nigbati akoko igbelewọn ba pari, o gbọdọ tun ṣe ẹrọ FPGA ṣaaju ki o to tẹsiwaju ijẹrisi ohun elo. Lati faagun lilo ti ipilẹ IP fun iṣelọpọ, ra iwe-aṣẹ iṣelọpọ ni kikun fun ipilẹ IP.
O gbọdọ ra iwe-aṣẹ naa ki o ṣe ina bọtini iwe-aṣẹ iṣelọpọ ni kikun ṣaaju ki o to ṣe agbekalẹ siseto ẹrọ ti ko ni ihamọ file. Lakoko Ipo Igbelewọn IP FPGA IP, Alakojọ nikan n ṣe agbekalẹ siseto ẹrọ to lopin akoko file ( _time_limited.sof) ti o pari ni opin akoko.

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Olusin 3.

Intel FPGA IP Igbelewọn Ipo Sisan
Fi Intel Quartus Prime Software sori ẹrọ pẹlu Intel FPGA IP Library

Parameterize ati Instantiate a Licensed Intel FPGA IP Core

Daju IP ni Simulator Atilẹyin

Ṣe akopọ Oniru ni Intel Quartus Prime Software

Ṣe eto siseto ẹrọ ti o ni opin akoko kan File

Ṣe eto Ẹrọ FPGA Intel ati Ṣayẹwo Iṣẹ lori Igbimọ naa
Ko si IP Ṣetan fun Lilo iṣelọpọ?
Bẹẹni Ra iṣelọpọ ni kikun
IP iwe-ašẹ

Akiyesi:

Fi IP ti o ni iwe-aṣẹ sinu Awọn ọja Iṣowo
Tọkasi itọsọna olumulo IP mojuto kọọkan fun awọn igbesẹ paramita ati awọn alaye imuse.
Awọn iwe-aṣẹ Intel awọn ohun kohun IP lori ijoko-kọọkan, ipilẹ ayeraye. Ọya iwe-aṣẹ pẹlu itọju ọdun akọkọ ati atilẹyin. O gbọdọ tunse adehun itọju lati gba awọn imudojuiwọn, awọn atunṣe kokoro, ati atilẹyin imọ-ẹrọ ju ọdun akọkọ lọ. O gbọdọ ra iwe-aṣẹ iṣelọpọ ni kikun fun awọn ohun kohun Intel FPGA IP ti o nilo iwe-aṣẹ iṣelọpọ, ṣaaju ṣiṣe siseto files pe o le lo fun akoko ailopin. Lakoko Ipo Igbelewọn IP FPGA IP, Alakojọ nikan n ṣe agbekalẹ siseto ẹrọ to lopin akoko file ( _time_limited.sof) ti o pari ni opin akoko. Lati gba awọn bọtini iwe-aṣẹ iṣelọpọ rẹ, ṣabẹwo si Ile-iṣẹ Iwe-aṣẹ Iṣẹ-ara Intel FPGA.
Awọn Adehun Iwe-aṣẹ sọfitiwia Intel FPGA n ṣakoso fifi sori ẹrọ ati lilo awọn ohun kohun IP ti o ni iwe-aṣẹ, sọfitiwia apẹrẹ Intel Quartus Prime, ati gbogbo awọn ohun kohun IP ti ko ni iwe-aṣẹ.

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Alaye ti o jọmọ · Ile-iṣẹ Atilẹyin Iwe-aṣẹ Intel FPGA · Ifihan si fifi sori ẹrọ sọfitiwia Intel FPGA ati Iwe-aṣẹ
3.2. Pato awọn IP paramita ati awọn aṣayan
Olootu paramita IP gba ọ laaye lati tunto iyatọ aṣa aṣa rẹ ni kiakia. Lo awọn igbesẹ wọnyi lati tokasi awọn aṣayan IP ati awọn paramita ninu sọfitiwia Intel Quartus Prime Pro Edition.
1. Ti o ko ba ti ni iṣẹ akanṣe Intel Quartus Prime Pro Edition ninu eyiti o le ṣepọ F-Tile Serial Lite IV Intel FPGA IP rẹ, o gbọdọ ṣẹda ọkan. a. Ni Intel Quartus Prime Pro Edition, tẹ File Oluṣeto Iṣẹ Tuntun lati ṣẹda iṣẹ akanṣe Quartus Prime tuntun, tabi File Ṣii Project lati ṣii iṣẹ akanṣe Quartus Prime ti o wa tẹlẹ. Oluṣeto naa ta ọ lati pato ẹrọ kan. b. Pato ẹbi ẹrọ Intel Agilex ki o yan ẹrọ F-tile iṣelọpọ ti o pade awọn ibeere ite iyara fun IP. c. Tẹ Pari.
2. Ni awọn IP Catalog, wa ki o si yan F-Tile Serial Lite IV Intel FPGA IP. Ferese Iyipada IP Tuntun yoo han.
3. Pato orukọ oke-ipele fun iyatọ IP aṣa tuntun rẹ. Olootu paramita n fipamọ awọn eto iyatọ IP ni a file ti a npè ni .ip.
4. Tẹ O DARA. Olootu paramita yoo han. 5. Pato awọn paramita fun iyatọ IP rẹ. Tọkasi apakan Parameter fun
alaye nipa F-Tile Serial Lite IV Intel FPGA IP paramita. 6. Ni iyan, lati ṣe ina simulation testbench tabi akopọ ati apẹrẹ ohun elo
example, tẹle awọn ilana ni Design Example User Itọsọna. 7. Tẹ ina HDL. Apoti ajọṣọ Generation yoo han. 8. Pato o wu file iran awọn aṣayan, ati ki o si tẹ Ina. IP iyatọ
files ina ni ibamu si rẹ ni pato. 9. Tẹ Pari. Olootu paramita ṣafikun ipele-oke .ip file si lọwọlọwọ
ise agbese laifọwọyi. Ti o ba ti ṣetan lati fi .ip kun pẹlu ọwọ file si ise agbese, tẹ Project Fikun-un / Yọ Files ni Project lati fi awọn file. 10. Lẹhin ti o npese ati instantiating rẹ IP iyatọ, ṣe yẹ pin iyansilẹ lati so ebute oko ati ṣeto eyikeyi yẹ fun-apeere RTL sile.
Awọn paramita Alaye ti o jọmọ loju iwe 42
3.3. Ti ipilẹṣẹ File Ilana
Sọfitiwia Intel Quartus Prime Pro Edition ṣe ipilẹṣẹ iṣelọpọ IP atẹle file igbekale.
Fun alaye nipa awọn file be ti awọn oniru example, tọka si F-Tile Serial Lite IV Intel FPGA IP Design Eksample User Itọsọna.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 14

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olusin 4. F-Tile Serial Lite IV Intel FPGA IP ti ipilẹṣẹ Files
.ip – IP Integration file

IP iyatọ files

_ IP iyatọ files

example_apẹrẹ

.cmp - VHDL paati ìkéde file _bb.v - Verilog HDL dudu apoti EDA kolaginni file _inst.v ati .vhd – Sample instantiation awọn awoṣe .xml- Iroyin XML file

Example ipo fun IP mojuto oniru rẹ example files. Ipo aiyipada jẹ example_design, ṣugbọn o ti ṣetan lati pato ọna ti o yatọ.

.qgsimc – Awọn atokọ kikopa atokọ lati ṣe atilẹyin isọdọtun ti afikun .qgsynthc – Awọn atokọ akojọpọ awọn aye lati ṣe atilẹyin isọdọtun ti afikun

.qip - Awọn akojọ IP kolaginni files

_generation.rpt- IP iran Iroyin

.sopcinfo- Software ọpa-pq Integration file .html- Asopọmọra ati data map iranti

.csv - Pin iṣẹ iyansilẹ file

.spd - Darapọ awọn iwe afọwọkọ kikopa olukuluku

Simulation Simulation files

synth IP kolaginni files

.v Top-ipele kikopa file

.v Top-ipele IP kolaginni file

Awọn iwe afọwọkọ Simulator

Subcore ikawe

synth
Subcore kolaginni files

SIM
Subcore Simulation files

Tabili 9.

F-Tile Serial Lite IV Intel FPGA IP ti ipilẹṣẹ Files

File Oruko

Apejuwe

.ip

Awọn Platform Onise eto tabi oke-ipele IP iyatọ file. ni orukọ ti o fun ni iyatọ IP rẹ.

.cmp

Ìkéde paati VHDL (.cmp) file jẹ ọrọ kan file ti o ni jeneriki agbegbe ati awọn asọye ibudo ti o le lo ninu apẹrẹ VHDL files.

.html

Ijabọ ti o ni alaye asopọ ninu, maapu iranti kan ti o nfihan adirẹsi ti ẹrú kọọkan pẹlu ọwọ si ọga kọọkan ti o sopọ mọ, ati awọn iṣẹ iyansilẹ paramita.

_generation.rpt

IP tabi Platform Apẹrẹ iran log file. Akopọ ti awọn ifiranṣẹ lakoko iran IP.

.qgsimc

Awọn atokọ kikopa lati ṣe atilẹyin isọdọtun ti afikun.

.qgsynthc

Ṣe atokọ awọn paramita iṣelọpọ lati ṣe atilẹyin isọdọtun ti afikun.

.qip

Ni gbogbo alaye ti a beere fun nipa paati IP lati ṣepọ ati ṣajọ paati IP ninu sọfitiwia Intel Quartus Prime.
tesiwaju…

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File Oruko .sopcinfo
.csv .spd _bb.v _inst.v tabi _inst.vhd .regmap
.svd
.v tabi .vhd olutojueni/ synopsys/vcs/ synopsys/vcsmx/ xcelium/ submodules/ /

Apejuwe
Apejuwe awọn asopọ ati awọn parameterizations paati IP ninu rẹ Platform Onise eto. O le ṣe itupalẹ awọn akoonu rẹ lati gba awọn ibeere nigbati o ba ṣe agbekalẹ awakọ sọfitiwia fun awọn paati IP. Awọn irinṣẹ isalẹ bi pq irinṣẹ Nios® II lo eyi file. Awọn .sopcinfo file ati eto.h file ti ipilẹṣẹ fun pq irinṣẹ Nios II pẹlu alaye maapu adirẹsi fun ẹru kọọkan ibatan si ọga kọọkan ti o wọle si ẹrú naa. Awọn oluwa oriṣiriṣi le ni maapu adirẹsi ti o yatọ lati wọle si paati ẹrú kan pato.
Ni alaye ninu nipa ipo igbesoke ti paati IP.
Ti beere fun titẹ sii file fun ip-make-simscript lati ṣe agbekalẹ awọn iwe afọwọkọ simulation fun awọn simulators atilẹyin. Awọn .spd file ni akojọ kan ti files ti ipilẹṣẹ fun kikopa, pẹlu alaye nipa awọn iranti ti o le initialize.
O le lo apoti dudu Verilog (_bb.v) file bi ohun ṣofo module ìkéde fun lilo bi dudu apoti.
HDL fun apẹẹrẹample instantiation awoṣe. O le daakọ ati lẹẹmọ awọn akoonu inu eyi file sinu HDL rẹ file lati instantiate awọn IP iyatọ.
Ti IP ba ni alaye iforukọsilẹ, .regmap file ipilẹṣẹ. The .regmap file ṣe apejuwe alaye maapu iforukọsilẹ ti oluwa ati awọn atọkun ẹrú. Eyi file complements awọn .sopcinfo file nipa fifun alaye iforukọsilẹ alaye diẹ sii nipa eto naa. Eyi jẹ ki ifihan iforukọsilẹ ṣiṣẹ views ati awọn iṣiro isọdi olumulo ni Eto Console.
Faye gba eto ero isise lile (HPS) Awọn irinṣẹ yokokoro eto lati view awọn maapu iforukọsilẹ ti awọn agbeegbe ti o sopọ si HPS ni eto Onise Platform. Lakoko iṣelọpọ, .svd files fun awọn atọkun ẹrú ti o han si awọn oluwa System Console ti wa ni ipamọ ninu .sof file ni apakan yokokoro. Console System ka abala yii, eyiti Apẹrẹ Platform le beere fun alaye maapu iforukọsilẹ. Fun awọn ẹrú eto, Apẹrẹ Platform le wọle si awọn iforukọsilẹ nipasẹ orukọ.
HDL files ti o instantiate kọọkan submodule tabi ọmọ IP fun kolaginni tabi kikopa.
Ni ModelSim*/QuestaSim* iwe afọwọkọ msim_setup.tcl lati ṣeto ati ṣiṣẹ kikopa kan.
Ni iwe afọwọkọ ikarahun vcs_setup.sh lati ṣeto ati ṣiṣe iṣeṣiro VCS* kan. Ni ninu iwe afọwọkọ ikarahun vcsmx_setup.sh ati synopsys_sim.setup file lati ṣeto ati ṣiṣẹ kikopa VCS MX kan.
Ni iwe afọwọkọ ikarahun kan xcelium_setup.sh ati iṣeto miiran files lati ṣeto ati ṣiṣe Xcelium * kikopa.
HDL ni ninu files fun awọn IP submodules.
Fun kọọkan ti ipilẹṣẹ ọmọ IP liana, Platform Designer gbogbo synth / ati SIM / iha-ilana.

3.4. Simulating Intel FPGA IP ohun kohun
Sọfitiwia Intel Quartus Prime ṣe atilẹyin kikopa IP mojuto RTL ni awọn simulators EDA kan pato. IP iran optionally ṣẹda kikopa files, pẹlu awoṣe kikopa iṣẹ, eyikeyi testbench (tabi example design), ati ataja-kan pato awọn iwe afọwọkọ oso simulator fun kọọkan IP mojuto. O le lo awoṣe kikopa iṣẹ-ṣiṣe ati eyikeyi testbench tabi example apẹrẹ fun kikopa. Ijade iran IP le tun pẹlu awọn iwe afọwọkọ lati ṣajọ ati ṣiṣe eyikeyi testbench. Awọn iwe afọwọkọ ṣe atokọ gbogbo awọn awoṣe tabi awọn ile-ikawe ti o nilo lati ṣe afarawe ipilẹ IP rẹ.

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Sọfitiwia Intel Quartus Prime n pese isọpọ pẹlu ọpọlọpọ awọn simulators ati ṣe atilẹyin awọn ṣiṣan kikopa pupọ, pẹlu iwe afọwọkọ tirẹ ati awọn ṣiṣan kikopa aṣa. Eyikeyi sisan ti o yan, kikopa ipilẹ IP ni awọn igbesẹ wọnyi:
1. Ṣe ina IP HDL, testbench (tabi example design), ati simulator oso akosile files.
2. Ṣeto rẹ soke simulator ayika ati eyikeyi kikopa iwe afọwọkọ.
3. Ṣajọ awọn ile-ikawe awoṣe kikopa.
4. Ṣiṣe rẹ labeabo.

3.4.1. Simulating ati Ṣiṣayẹwo Oniru naa

Nipa aiyipada, olootu paramita n ṣe agbekalẹ awọn iwe afọwọkọ-simulator kan pato ti o ni awọn aṣẹ ti o ni awọn aṣẹ lati ṣajọ, ṣe alaye, ati ṣe afiwe awọn awoṣe IP FPGA IP ati ile ikawe awoṣe kikopa files. O le daakọ awọn aṣẹ sinu iwe afọwọkọ testbench kikopa rẹ, tabi ṣatunkọ awọn wọnyi files lati ṣafikun awọn aṣẹ fun iṣakojọpọ, ṣiṣe alaye, ati simulating apẹrẹ ati testbench rẹ.

Table 10. Intel FPGA IP mojuto Simulation awọn iwe afọwọkọ

Simulator

File Itọsọna

AwoṣeSim

_sim / olutojueni

QuestaSim

VCS

_sim / synopsys / vcs

VCS MX

_sim / synopsys / vcsmx

Xcelium

_sim / xcelium

Iwe afọwọkọ msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Ṣiṣẹpọ Awọn ohun kohun IP ni Awọn irinṣẹ EDA miiran
Ni yiyan, lo ohun elo EDA miiran ti o ni atilẹyin lati ṣajọpọ apẹrẹ kan ti o pẹlu awọn ohun kohun Intel FPGA IP. Nigba ti o ba se ina awọn IP mojuto kolaginni files fun lilo pẹlu awọn irinṣẹ iṣelọpọ EDA ẹni-kẹta, o le ṣẹda agbegbe kan ati nẹtiwọọki iṣiro akoko. Lati mu iran ṣiṣẹ, tan-an Ṣẹda akoko ati awọn iṣiro orisun fun awọn irinṣẹ iṣelọpọ EDA ẹni-kẹta nigbati o ba n ṣatunṣe iyatọ IP rẹ.
Agbegbe ati atokọ nẹtiwọọki iṣiro akoko ṣe apejuwe Asopọmọra mojuto IP ati faaji, ṣugbọn ko pẹlu awọn alaye nipa iṣẹ ṣiṣe tootọ. Alaye yii ngbanilaaye awọn irinṣẹ iṣelọpọ ẹni-kẹta kan lati ṣe ijabọ agbegbe to dara julọ ati awọn iṣiro akoko. Ni afikun, awọn irinṣẹ iṣelọpọ le lo alaye akoko lati ṣaṣeyọri awọn iṣapeye-akoko ati mu didara awọn abajade dara si.
Intel Quartus Prime software gbogbo awọn _syn.v netlist file ni ọna kika Verilog HDL, laibikita abajade file kika ti o pato. Ti o ba lo nẹtiwọọki yii fun iṣelọpọ, o gbọdọ pẹlu murasilẹ mojuto IP file .v tabi .vhd ninu rẹ Intel Quartus Prime ise agbese.

(7) Ti o ko ba ṣeto aṣayan irinṣẹ EDA - eyiti o fun ọ laaye lati bẹrẹ awọn simulators EDA ẹni-kẹta lati sọfitiwia Intel Quartus Prime – ṣiṣe iwe afọwọkọ yii ni ModelSim tabi QuestaSim simulator Tcl console (kii ṣe ninu sọfitiwia Intel Quartus Prime). Tcl console) lati yago fun eyikeyi awọn aṣiṣe.

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3.6. Iṣakojọpọ Apẹrẹ ni kikun
O le lo aṣẹ Ibẹrẹ Ikojọpọ lori akojọ aṣayan ṣiṣe ni sọfitiwia Intel Quartus Prime Pro Edition lati ṣajọ apẹrẹ rẹ.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 18

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4. Apejuwe iṣẹ

Olusin 5.

F-Tile Serial Lite IV Intel FPGA IP oriširiši MAC ati àjọlò PCS. MAC ṣe ibaraẹnisọrọ pẹlu PCS aṣa nipasẹ awọn atọkun MII.

IP naa ṣe atilẹyin awọn ipo iṣatunṣe meji:
PAM4 – Pese 1 si 12 nọmba awọn ọna fun yiyan. IP nigbagbogbo n ṣe awọn ikanni PCS meji fun ọna kọọkan ni ipo iṣatunṣe PAM4.
NRZ – Pese nọmba awọn ọna 1 si 16 fun yiyan.

Ipo iṣatunṣe kọọkan ṣe atilẹyin awọn ipo data meji:
· Ipo ipilẹ-Eyi jẹ ipo ṣiṣanwọle mimọ nibiti a ti fi data ranṣẹ laisi apo-ibẹrẹ, ọmọ sofo, ati apo-ipari lati mu bandiwidi pọ si. IP gba data to wulo akọkọ bi ibẹrẹ ti nwaye.

Gbigbe Data Ipo Ipilẹ tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001: 2015 forukọsilẹ

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Olusin 6.

Ipo ni kikun - Eyi ni gbigbe data ipo apo. Ni ipo yii, IP naa nfiranṣẹ ti nwaye ati eto amuṣiṣẹpọ ni ibẹrẹ ati ipari ti apo kan bi awọn alapin.

Gbigbe Data Ipo ni kikun tx_core_klout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Alaye jẹmọ · F-Tile Serial Lite IV Intel FPGA IP Loriview loju iwe 6 · F-Tile Serial Lite IV Intel FPGA IP Design Eksample User Itọsọna

4.1. Ọna data TX
Ọna data TX ni awọn paati wọnyi: · Ohun ti nmu badọgba Mac · Iṣakoso ifibọ ọrọ Àkọsílẹ · CRC · MII koodu · Àkọsílẹ PCS · PMA Àkọsílẹ

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 20

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olusin 7. TX Datapath

Lati olumulo kannaa

TX MAC

Avalon śiśanwọle Interface

MAC Adapter

Iṣakoso Ọrọ ifibọ

CRC

MII kooduopo

MII Interface Aṣa PCS
PCS ati PMA

TX Serial Interface To Miiran FPGA Device

4.1.1. TX MAC Adapter
Ohun ti nmu badọgba TX MAC n ṣakoso gbigbe data si ọgbọn olumulo nipa lilo wiwo ṣiṣanwọle Avalon®. Àkọsílẹ yii ṣe atilẹyin gbigbe alaye ti olumulo-telẹ ati iṣakoso sisan.

Gbigbe Alaye asọye olumulo

Ni ipo ni kikun, IP n pese ifihan tx_is_usr_cmd ti o le lo lati pilẹṣẹ ọna alaye asọye olumulo gẹgẹbi gbigbe XOFF/XON si ọgbọn olumulo. O le pilẹṣẹ ti olumulo-telẹ alaye gbigbe ọmọ nipa a atẹnumọ yi ifihan agbara ati ki o gbe awọn alaye lilo tx_avs_data pẹlú pẹlu awọn itenumo ti tx_avs_startofpacket ati tx_avs_valid awọn ifihan agbara. Awọn Àkọsílẹ ki o si deasserts tx_avs_ready fun meji waye.

Akiyesi:

Ẹya alaye asọye olumulo wa ni ipo Kikun nikan.

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Olusin 8.

Iṣakoso sisan

Awọn ipo wa nibiti TX MAC ko ti ṣetan lati gba data lati inu ọgbọn olumulo gẹgẹbi lakoko ilana isọdọtun ọna asopọ tabi nigbati ko ba si data ti o wa fun gbigbe lati ọgbọn olumulo. Lati yago fun pipadanu data nitori awọn ipo wọnyi, IP nlo ifihan agbara tx_avs_ready lati ṣakoso sisan data lati inu ọgbọn olumulo. IP deassert ifihan agbara nigbati awọn ipo atẹle ba waye:
Nigba ti tx_avs_startofpacket ti fi idi rẹ mulẹ, tx_avs_ready jẹ deasserted fun akoko aago kan.
Nigba ti tx_avs_endofpacket ti fi idi rẹ mulẹ, tx_avs_ready jẹ deaserted fun akoko aago kan.
Nigba ti eyikeyi ti so pọ CWs ti wa ni itenumo tx_avs_ready jẹ deaserted fun meji aago iyika.
Nigba ti RS-FEC titete asami ifibọ waye ni aṣa PCS ni wiwo, tx_avs_ready jẹ deasserted fun mẹrin aago iyika.
· Gbogbo 17 àjọlò mojuto aago iyika ni PAM4 modulation mode ati gbogbo 33 àjọlò mojuto aago iyipo ni NRZ modulation mode. tx_avs_ready ti wa ni deasserted fun ọkan aago ọmọ.
Nigba ti olumulo kannaa deasserts tx_avs_valid nigba ti ko si data gbigbe.

Awọn aworan akoko atẹle wọnyi jẹ examples ti TX MAC ohun ti nmu badọgba lilo tx_avs_ready fun iṣakoso sisan data.

Iṣakoso sisan pẹlu tx_avs_valid Deassertion ati START/END CWs

tx_core_klout

tx_avs_valid tx_avs_data

D1 D2 D3

Wulo ifihan agbara deasserts

D5 D6

tx_avs_ready tx_avs_startofpacket

Awọn deasserts ifihan agbara ti ṣetan fun awọn iyipo meji lati fi END-STRT CW sii

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

DN OPIN STRT D0 D1 D2 D3 EMPTY D4

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 22

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Olusin 9.

Iṣakoso sisan pẹlu Titete asami ifibọ
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN DN-1 DN-1 DN-1 DN-DN DN DN DN DN

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Olusin 10.

Iṣakoso sisan pẹlu START/END Awọn CW ti o so pọ ni ibamu pẹlu Iṣafihan Iṣatunṣe

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ṣetan

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 OPIN STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 OPIN STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 OPIN STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 OPIN STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

Ipari STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Iṣakoso Ọrọ (CW) ifibọ
F-Tile Serial Lite IV Intel FPGA IP n ṣe awọn CW ti o da lori awọn ifihan agbara titẹ sii lati ọgbọn olumulo. Awọn CW tọkasi awọn apinpin apo, alaye ipo gbigbe tabi data olumulo si bulọọki PCS ati pe wọn wa lati awọn koodu iṣakoso XGMII.
Tabili ti o tẹle n ṣe afihan apejuwe ti awọn CW ti o ni atilẹyin:

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Tabili 11.
BERE IPADE OPIN

Apejuwe ti Awọn atilẹyin CWs

Nọmba awọn Ọrọ (ọrọ 1

= 64 die-die)

Bẹẹni

EMPTY_CYC

Bẹẹni

IDLE

Rara

DATA

Bẹẹni

Ni-iye

Apejuwe
Bẹrẹ apinpin data. Opin ti data delimiter. Ọrọ iṣakoso (CW) fun titete RX. Sofo ọmọ ni a data gbigbe. IDLE (jade kuro ninu ẹgbẹ). Isanwo.

Table 12. CW Field Apejuwe
Aaye RSVD num_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Apejuwe
Aaye ipamọ. Le ṣee lo fun itẹsiwaju iwaju. Ti so mọ 0.
Nọmba awọn baiti to wulo ni ọrọ ikẹhin (64-bit). Eyi jẹ iye 3bit kan. · 3'b000: 8 baiti · 3'b001: 1 baiti · 3'b010: 2 baiti · 3'b011: 3 baiti · 3'b100: 4 baiti · 3'b101: 5 baiti · 3'b110: 6 baiti · 3'b111:7 baiti
Nọmba awọn ọrọ ti ko wulo ni ipari ti nwaye kan.
Tọkasi wiwo ṣiṣanwọle RX Avalon lati sọ ami ifihan ipari-packet kan.
Tọkasi wiwo sisanwọle RX Avalon lati sọ ami ifihan ibẹrẹ-ti-packet.
Tọkasi wiwo ṣiṣanwọle RX Avalon lati fi idi ibẹrẹ-ti-packet ati ipari-packet kan ni ọna kanna.
Ṣayẹwo titete RX.
Awọn iye ti CRC iṣiro.
Tọkasi pe ọrọ iṣakoso (CW) ni alaye asọye-olumulo ninu.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 24

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4.1.2.1. Ibẹrẹ-ti-ti nwaye CW

olusin 11. Ibẹrẹ-ti-ti nwaye CW kika

BERE

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop usr align = 0 seop

15:8

ikanni

7:0

'hFB(Bẹrẹ)

Iṣakoso 7:0

Tabili 13.

Ni ipo ni kikun, o le fi START CW sii nipa didaduro ifihan agbara tx_avs_startofpacket. Nigba ti o ba so nikan tx_avs_startofpacket ifihan agbara, sop bit ti ṣeto. Nigba ti o ba so mejeji tx_avs_startofpacket ati tx_avs_endofpacket awọn ifihan agbara, seop bit ti ṣeto.

Bẹrẹ CW Field iye
Aaye sop / seop
USr (8)
mö

Iye

Da lori ifihan tx_is_usr_cmd:

1: Nigbati tx_is_usr_cmd = 1

0: Nigbati tx_is_usr_cmd = 0

Ni ipo Ipilẹ, MAC fi START CW ranṣẹ lẹhin atunto ti jẹ deaserted. Ti ko ba si data, MAC nfiranṣẹ nigbagbogbo EMPTY_CYC ni idapo pelu END ati START CWs titi ti o fi bẹrẹ fifiranṣẹ data.

4.1.2.2. Ipari-ti-ti nwaye CW

Nọmba 12. Ipari-ti-ti nwaye CW kika

OPIN

63:56

hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

data 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

OFO

7:0

RSVD

num_valid_bytes_eob

iṣakoso

7:0

(8) Eyi ni atilẹyin nikan ni Ipo kikun.
Fi esi ranṣẹ

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Tabili 14.

MAC fi END CW sii nigbati tx_avs_endofpacket ti fi idi rẹ mulẹ. END CW ni nọmba awọn baiti to wulo ni ọrọ data to kẹhin ati alaye CRC naa.

Iye CRC jẹ abajade CRC 32-bit fun data laarin START CW ati ọrọ data ṣaaju END CW.

Tabili ti o tẹle n ṣe afihan awọn iye ti awọn aaye ni END CW.

OPIN CW Field iye
Aaye eop CRC32 num_valid_bytes_eob

Iye 1
CRC32 iṣiro iye. Nọmba awọn baiti to wulo ni ọrọ data to kẹhin.

4.1.2.3. Titete Sopọ CW

olusin 13. Titete Paired CW kika

DARA CW PẸLU PẸLU Ibẹrẹ/opin

64 + 8bits XGMII Interface

BERE

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop = 0 sop = 0 usr = 0 align = 1 seop = 0

15:8

RSVD

7:0

hFB

Iṣakoso 7:0

64 + 8bits XGMII Interface

OPIN

63:56

hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

Iṣakoso 7:0

ALIGN CW jẹ CW ti a so pọ pẹlu START/END tabi END/Bẹrẹ CWs. O le fi ALIGN ti o so pọ CW sii nipa boya fifihan ifihan tx_link_reinit, ṣeto counter Akoko Iṣatunṣe, tabi pilẹṣẹ ipilẹ. Nigbati ALIGN ti o so pọ CW ti fi sii, aaye titọpọ ti ṣeto si 1 lati pilẹṣẹ bulọọki titete olugba lati ṣayẹwo titete data ni gbogbo awọn ọna.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 26

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Tabili 15.

ALIGN CW Field iye
Atopọ aaye
eop sop usr seop

Iye 1 0 0 0 0

4.1.2.4. Ofo-ọmọ CW

olusin 14. Ofo-cycle CW kika

EMPTY_CYC Pelu END/START

64 + 8bits XGMII Interface

OPIN

63:56

hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

Iṣakoso 7:0

64 + 8bits XGMII Interface

BERE

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop = 0 usr = 0 align = 0 seop = 0

15:8

RSVD

7:0

hFB

Iṣakoso 7:0

Tabili 16.

Nigbati o ba deassert tx_avs_valid fun aago meji nigba ti nwaye, MAC fi EMPTY_CYC CW kan sii pẹlu END/START CWs. O le lo CW yii nigbati ko si data wa fun gbigbe ni akoko kan.

Nigbati o ba deassert tx_avs_valid fun akoko kan, IP deassert tx_avs_valid fun igba meji akoko tx_avs_valid deassertion lati se ina kan bata ti END/START CWs.

EMPTY_CYC CW Field iye
Atopọ aaye
eop

Iye 0

tesiwaju…

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Aaye sop usr seop

Iye 0 0 0

4.1.2.5. CW laišišẹ

olusin 15. Idle CW kika

IDLE CW

63:56

h07

55:48

h07

47:40

h07

data

39:32 31:24

07 'h07

23:16

h07

15:8

h07

7:0

h07

Iṣakoso 7:0

MAC fi IDLE CW sii nigbati ko ba si gbigbe. Lakoko yii, ifihan tx_avs_valid ti lọ silẹ.
O le lo IDLE CW nigbati gbigbe ti nwaye ba ti pari tabi gbigbe wa ni ipo aiṣiṣẹ.

4.1.2.6. Ọrọ Data

Ọrọ data jẹ sisanwo ti apo kan. Awọn iwọn iṣakoso XGMII ti wa ni gbogbo ṣeto si 0 ni ọna kika ọrọ data.

olusin 16. Data Ọrọ kika

64 + 8 die-die XGMII Interface

ỌRỌ DATA

63:56

data olumulo 7

55:48

data olumulo 6

47:40

data olumulo 5

data

39:32 31:24

data olumulo 4 data olumulo 3

23:16

data olumulo 2

15:8

data olumulo 1

7:0

data olumulo 0

Iṣakoso 7:0

4.1.3. TX CRC
O le mu ohun amorindun TX CRC ṣiṣẹ nipa lilo paramita Mu CRC ṣiṣẹ ninu Olootu Parameter IP. Ẹya yii ni atilẹyin ni ipilẹ ati awọn ipo Kikun.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 28

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MAC ṣe afikun iye CRC si END CW nipa sisọ ami ifihan tx_avs_endofpacket. Ni ipo BASIC, ALIGN CW nikan ni so pọ pẹlu END CW ni aaye CRC to wulo.
Awọn atọkun Àkọsílẹ TX CRC pẹlu fifi sii Ọrọ Iṣakoso TX ati Àkọsílẹ koodu TX MII. Àkọsílẹ TX CRC ṣe iṣiro iye CRC fun iye 64-bit fun data-ọmọ ti o bẹrẹ lati START CW titi de END CW.
O le fi ami ami crc_error_inject han si awọn imomose data ibajẹ ni ọna kan pato lati ṣẹda awọn aṣiṣe CRC.

4.1.4. TX MII kooduopo

TX MII kooduopo n kapa gbigbe soso lati MAC si TX PCS.

Nọmba ti o tẹle yii fihan ilana data lori ọkọ akero 8-bit MII ni ipo awose PAM4. START ati END CW han ni ẹẹkan ni gbogbo awọn ọna MII meji.

olusin 17. PAM4 Modulation Mode MII Data Àpẹẹrẹ

ILE 1

ILE 2

ILE 3

ILE 4

ILE 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Nọmba atẹle yii fihan ilana data lori ọkọ akero MII 8-bit ni ipo awose NRZ. START ati END CW han ni gbogbo awọn ọna MII.

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olusin 18. NRZ Modulation Mode MII Data Àpẹẹrẹ

ILE 1

ILE 2

ILE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS ati PMA
F-Tile Serial Lite IV Intel FPGA IP tunto transceiver F-tile si ipo PCS Ethernet.

4.2. RX Datapath
Ọna data RX ni awọn paati wọnyi: · Àkọsílẹ PMA · Àkọsílẹ PCS · MII decoder · CRC · Deskew Àkọsílẹ · Iṣakoso yiyọ Ọrọ kuro

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 30

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olusin 19. RX Datapath

Lati olumulo kannaa Avalon Streaming Interface
RX MAC
Yiyọ Ọrọ Iṣakoso
Deskew

CRC

MII Decoder

MII Interface Aṣa PCS
PCS ati PMA

RX Serial Interface Lati Miiran FPGA Device
4.2.1. RX PCS ati PMA
F-Tile Serial Lite IV Intel FPGA IP tunto transceiver F-tile si ipo PCS Ethernet.
4.2.2. RX MII Decoder
Àkọsílẹ yii n ṣe idanimọ ti data ti nwọle ba ni ọrọ iṣakoso ati awọn asami titete. RX MII decoder ṣe agbejade data ni irisi 1-bit wulo, atọka asami 1-bit, atọka iṣakoso 1bit, ati data 64-bit fun ọna kan.
4.2.3. RX CRC
O le mu ohun amorindun TX CRC ṣiṣẹ nipa lilo paramita Mu CRC ṣiṣẹ ninu Olootu Parameter IP. Ẹya yii ni atilẹyin ni ipilẹ ati awọn ipo Kikun. Awọn atọkun idinamọ RX CRC pẹlu Yiyọ Ọrọ Iṣakoso RX ati awọn bulọọki Decoder RX MII. IP naa sọ ami ifihan rx_crc_error nigbati aṣiṣe CRC ba waye.

Fi esi ranṣẹ

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 31

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IP deassert rx_crc_error ni gbogbo titun ti nwaye. O jẹ iṣẹjade si ọgbọn olumulo fun mimu aṣiṣe aṣiṣe olumulo.
4.2.4. RX Deskew
Àkọsílẹ RX deskew ṣe awari awọn asami titete fun ọna kọọkan ati tun ṣe deede data naa ṣaaju fifiranṣẹ si bulọki yiyọ RX CW.
O le yan lati jẹ ki ipilẹ IP lati ṣe deede data naa fun ọna kọọkan laifọwọyi nigbati aṣiṣe titete ba waye nipa tito Mu paramita Alignment Auto ṣiṣẹ ni Olootu paramita IP. Ti o ba mu ẹya titete laifọwọyi ṣiṣẹ, ipilẹ IP n ṣe afihan ami rx_error lati tọka aṣiṣe titete. O gbọdọ sọ rx_link_reinit lati bẹrẹ ilana titete ọna nigbati aṣiṣe titete ọna ba waye.
RX deskew ṣe awari awọn ami titete ti o da lori ẹrọ ipinlẹ kan. Aworan atọka atẹle yii fihan awọn ipinlẹ ni bulọọki deskew RX.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 32

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Olusin 20.

RX Deskew Lane Alignment State Machine pẹlu Auto titete sise Sisan Chart
Bẹrẹ

IDLE

Tunto = 1 bẹẹni rara

Gbogbo PCS

rara

ona setan?

beeni

DURO

Gbogbo awọn asami amuṣiṣẹpọ No
ri?
beeni
ALIGE

rara
bẹẹni Akoko Ipari?

beeni
Ti sọnu titete?
ko si Ipari

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Olusin 21.

RX Deskew Lane Alignment State Machine with Auto Alignment Disabled Flow Chart
Bẹrẹ

IDLE

Tunto = 1 bẹẹni rara

Gbogbo PCS

rara

ona setan?

beeni

beeni
rx_link_reinit = 1
ko si Asise

rara beeni Akoko Ipari?

DURO
ko si Gbogbo amuṣiṣẹpọ asami
ri?
bẹẹni ALIGN

beeni
Ti sọnu titete?
rara
Ipari
1. Ilana titete bẹrẹ pẹlu IDLE ipinle. Bulọọki naa n lọ si ipo WAIT nigbati gbogbo awọn ọna PCS ti ṣetan ati rx_link_reinit ti jẹ desasert.
2. Ni ipinle WAIT, awọn sọwedowo Àkọsílẹ gbogbo awọn asami-ri ti wa ni idaniloju laarin awọn kanna ọmọ. Ti ipo yii ba jẹ otitọ, bulọki naa gbe lọ si ipo ALIGNED.
3. Nigbati bulọọki ba wa ni ipo ALIGNED, o tọkasi awọn ọna ti o wa ni ibamu. Ni ipinlẹ yii, bulọọki naa tẹsiwaju lati ṣe atẹle titete ọna ati ṣayẹwo boya gbogbo awọn asami wa laarin iwọn kanna. Ti o ba jẹ pe o kere ju ami ami kan ko si ni ọna kanna ati pe o ti ṣeto paramita Alignment Auto, bulọki naa lọ si

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Ipo IDLE lati tun bẹrẹ ilana titete. Ti ko ba ṣeto Iṣatunṣe Aifọwọyi ati pe o kere ju aami kan ko si ni ọna kanna, bulọọki naa lọ si ipo ERROR ati duro fun ọgbọn olumulo lati sọ ami rx_link_reinit lati bẹrẹ ilana titete ọna.

Ṣe nọmba 22. Iṣatunṣe Lane pẹlu Muu ṣiṣẹ titete laifọwọyi ṣiṣẹ rx_core_clk

rx_link_up

rx_link_reinit

ati_gbogbo_ami

Ipinle Deskew

ALGNED

IDLE

DURO

ALGNED

AUTO_ALIGN = 1

Nọmba 23. Iṣatunṣe Lane pẹlu Muu ṣiṣẹ titete laifọwọyi Alaabo rx_core_clk

rx_link_up

rx_link_reinit

ati_gbogbo_ami

Ipinle Deskew

ALGNED

Asise

IDLE

DURO

ALGNED

AUTO_ALIGN = 0
4.2.5. RX CW yiyọ
Yi Àkọsílẹ decodes awọn CWs ati ki o rán data si awọn olumulo kannaa lilo awọn Avalon ni wiwo sisanwọle lẹhin yiyọ ti awọn CWs.
Nigbati ko ba si wulo data wa, RX CW Àkọsílẹ deassert deassert rx_avs_valid ifihan agbara.
Ni ipo FULL, ti o ba ṣeto bit olumulo, bulọọki yii ṣe afihan ifihan rx_is_usr_cmd ati pe data ni akoko aago akọkọ ti lo bi alaye asọye olumulo tabi aṣẹ.
Nigba ti rx_avs_ready deasserts ati rx_avs_valid asserts, awọn RX CW yiyọ Àkọsílẹ gbogbo aṣiṣe majemu si olumulo kannaa.
Awọn ifihan agbara ṣiṣanwọle Avalon ti o ni ibatan si bulọọki yii jẹ atẹle yii: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (nikan wa ni ipo kikun)
4.3. F-Tile Serial Lite IV Intel FPGA IP Aago Architecture
F-Tile Serial Lite IV Intel FPGA IP ni awọn igbewọle aago mẹrin eyiti o ṣe agbejade awọn aago si awọn bulọọki oriṣiriṣi: · Aago itọkasi transceiver (xcvr_ref_clk) – Aago titẹ sii lati aago ita
awọn eerun igi tabi awọn oscillators eyiti o ṣe agbejade awọn aago fun TX MAC, RX MAC, ati TX ati awọn bulọọki PCS aṣa RX. Tọkasi Awọn paramita fun iwọn igbohunsafẹfẹ atilẹyin. · TX mojuto aago (tx_core_clk) – Aago yi wa lati transceiver PLL ti a lo fun TX MAC. Aago yii tun jẹ aago iṣejade lati transceiver F-tile lati sopọ si ọgbọn olumulo TX. · Aago mojuto RX (rx_core_clk) – Aago yii jẹ lati inu transceiver PLL ti a lo fun RX deskew FIFO ati RX MAC. Aago yii tun jẹ aago iṣejade lati transceiver F-tile lati sopọ si ọgbọn olumulo RX. · Aago fun wiwo atunto transceiver (reconfig_clk) – aago titẹ sii lati awọn iyika aago itagbangba tabi awọn oscillators eyiti o ṣe agbejade awọn aago fun wiwo atunto transceiver F-tile ni mejeeji TX ati awọn ọna data RX. Igbohunsafẹfẹ aago jẹ 100 si 162 MHz.
Aworan atọka bulọọki atẹle yii fihan awọn ibugbe aago F-Tile Serial Lite IV Intel FPGA IP ati awọn asopọ laarin IP.

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Olusin 24.

F-Tile Serial Lite IV Intel FPGA IP Aago Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Aago
(reconfig_clk)

tx_core_clkout (so si ọgbọn olumulo)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Aago Interface Atunto Transceiver

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (so si ọgbọn olumulo)

clk_pll_div64[mid_ch] clk_pll_div64 [n-1:0]

Avalon śiśanwọle Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon śiśanwọle Interface RX Data RX MAC

Avalon śiśanwọle Interface RX Data
RX MAC

Deskew FIFO

rx_core_clkout (so si ọgbọn olumulo)

rx_core_clk= clk_pll_div64[mid_ch]

PCS aṣa

serial_link[n-1:0]

TX MAC

Avalon śiśanwọle Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (so si ọgbọn olumulo)

Aago Ref Transceiver (xcvr_ref_clk)
Aago Ref Transceiver (xcvr_ref_clk)

Oscillator*

Àlàyé

FPGA ẹrọ
TX mojuto aago domain
ašẹ aago mojuto RX
Transceiver itọkasi aago ase Ita ẹrọ Data awọn ifihan agbara

4.4. Tun ati Ibẹrẹ Ọna asopọ
MAC, F-tile Hard IP, ati awọn bulọọki atunto ni oriṣiriṣi awọn ifihan agbara atunto: · TX ati awọn bulọọki MAC RX lo tx_core_rst_n ati awọn ami atunto rx_core_rst_n. tx_pcs_fec_phy_reset_n ati rx_pcs_fec_phy_reset_n wakọ awọn ifihan agbara atunto
olutọsọna atunto asọ lati tun F-tile Lile IP tunto. · Atunto Àkọsílẹ nlo reconfig_reset ifihan agbara.

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olusin 25. Tun Architecture
Avalon śiśanwọle Interface TX Data
MAC
Avalon śiśanwọle SYNC Interface RX Data

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ṣetan phy_rx_pcs_ready

F-tile Lile IP

TX Serial Data RX Serial Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Tun Logic
Alaye ti o jọmọ · Awọn Itọsọna Tunto loju iwe 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Itọsọna
4.4.1. TX Tunto ati Ibẹrẹ Ibẹrẹ
Ilana atunto TX fun F-Tile Serial Lite IV Intel FPGA IP jẹ atẹle yii: 1. Sọ tx_pcs_fec_phy_reset_n, tx_core_rst_n, ati atunto_reset
nigbakanna lati tun F-tile lile IP, MAC, ati awọn bulọọki atunto. Tu tx_pcs_fec_phy_reset_n silẹ ati atunto atunto lẹhin ti nduro fun tx_reset_ack lati rii daju pe awọn bulọọki ti tunto daradara. 2. IP naa tun sọ pe phy_tx_lanes_stable, tx_pll_locked, ati awọn ifihan agbara phy_ehip_ready lẹhin atunto tx_pcs_fec_phy_reset_n ti tu silẹ, lati fihan pe TX PHY ti ṣetan fun gbigbe. 3. Tx_core_rst_n ifihan agbara deasserts lẹhin phy_ehip_ready ifihan agbara ga. 4. IP bẹrẹ gbigbe awọn ohun kikọ IDLE lori wiwo MII ni kete ti MAC ti jade ni ipilẹ. Ko si ibeere fun titete ọna TX ati skewing nitori gbogbo awọn ọna lo aago kanna. 5. Lakoko gbigbe awọn ohun kikọ IDLE, MAC sọ ami ifihan tx_link_up. 6. MAC naa bẹrẹ gbigbe ALIGN ti o so pọ pẹlu START/END tabi END/START CW ni aarin aarin lati bẹrẹ ilana titete ọna ti olugba ti o sopọ.

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Olusin 26.

Atunto TX ati Aworan Ibẹrẹ akoko
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _titiipa

phy_tx_lanes_stable

phy_ehip_setan

tx_li nk_up

7
5 6 8

4.4.2. Atunto RX ati Ibẹrẹ Ibẹrẹ
Ilana atunto RX fun F-Tile Serial Lite IV Intel FPGA IP jẹ bi atẹle:
1. Sọ rx_pcs_fec_phy_reset_n, rx_core_rst_n, ati reconfig_reset nigbakanna lati tun F-tile lile IP, MAC, ati awọn bulọọki atunto. Tu rx_pcs_fec_phy_reset_n silẹ ati atunto atunto lẹhin ti nduro fun rx_reset_ack lati rii daju pe awọn ohun amorindun ti tunto daradara.
2. IP naa lẹhinna sọ ami ifihan phy_rx_pcs_ready lẹhin atunto PCS aṣa ti tu silẹ, lati fihan RX PHY ti ṣetan fun gbigbe.
3. The rx_core_rst_n ifihan agbara deasserts lẹhin phy_rx_pcs_ready ifihan agbara ga.
4. IP naa bẹrẹ ilana titete ọna lẹyin ti a ti tu atunto RX MAC silẹ ati lori gbigba ALIGN ti a so pọ pẹlu START/END tabi END/START CW.
5. RX deskew Àkọsílẹ sọ ifihan rx_link_up ni kete ti titete fun gbogbo awọn ọna ti pari.
6. IP naa lẹhinna sọ ami ifihan rx_link_up si ọgbọn olumulo lati fihan pe ọna asopọ RX ti ṣetan lati bẹrẹ gbigba data.

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Ṣe nọmba 27. Atunto RX ati Ibẹrẹ Aago Ibẹrẹ
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ṣetan

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Oṣuwọn Ọna asopọ ati Iṣiro Ṣiṣe Bandiwidi

F-Tile Serial Lite IV Intel FPGA IP iṣiro ṣiṣe bandiwidi jẹ bi isalẹ:

Iṣiṣẹ bandiwidi = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2)_ / srl4_align

Table 17. Bandiwidi ṣiṣe oniyipada Apejuwe

Ayípadà

Apejuwe

raw_rate burst_size

Eleyi jẹ awọn bit oṣuwọn waye nipasẹ awọn ni tẹlentẹle ni wiwo. raw_rate = SERDES iwọn * transceiver aago igbohunsafẹfẹ Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Iye ti nwaye iwọn. Lati ṣe iṣiro apapọ bandiwidi ṣiṣe, lo iye iwọn ti nwaye wọpọ. Fun o pọju oṣuwọn, lo o pọju ti nwaye iwọn iye.

burst_size_ovhd

Iwọn ti nwaye loke iye.
Ni ipo kikun, iye burst_size_ovhd n tọka si START ati END CW ti o so pọ.
Ni ipo Ipilẹ, ko si burst_size_ovhd nitoripe ko si START ati END CWs ti a so pọ.

align_marker_period

Iye akoko ti o ti fi aami titete sii. Awọn iye ti wa ni 81920 aago ọmọ fun akopo ati 1280 fun sare kikopa. Yi iye ti wa ni gba lati PCS lile kannaa.

align_marker_width srl4_align_period

Nọmba awọn iyipo aago nibiti ami ami isamisi to wulo ti waye ga.
Nọmba awọn iyipo aago laarin awọn asami titete meji. O le ṣeto iye yii nipa lilo paramita Akoko Iṣatunṣe ni Olootu IP Parameter.

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Awọn iṣiro oṣuwọn ọna asopọ jẹ bi isalẹ: Oṣuwọn ti o munadoko = ṣiṣe bandiwidi * raw_rate O le gba igbohunsafẹfẹ aago olumulo ti o pọju pẹlu idogba atẹle. Iṣiro igbohunsafẹfẹ olumulo ti o pọju dawọle ṣiṣanwọle data lemọlemọfún ko si si ọmọ IDLE ti o waye ni ọgbọn olumulo. Oṣuwọn yii ṣe pataki nigbati o n ṣe apẹrẹ ọgbọn olumulo FIFO lati yago fun apọju FIFO. Igbohunsafẹfẹ aago olumulo ti o pọju = oṣuwọn to munadoko / 64

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5. Awọn ipin

Table 18. F-Tile Serial Lite IV Intel FPGA IP paramita Apejuwe

Paramita

Iye

Aiyipada

Apejuwe

Gbogbogbo Design Aw

PMA awose iru

PAM4 · NRZ

PAM4

Yan ipo awose PCS.

PMA Iru

· FHT · FGT

FGT

Yan iru transceiver.

Oṣuwọn data PMA

Fun ipo PAM4:
- FGT transceiver iru: 20 Gbps 58 Gbps
- FHT transceiver iru: 56.1 Gbps, 58 Gbps, 116 Gbps
Fun ipo NRZ:
- FGT transceiver iru: 10 Gbps 28.05 Gbps
- FHT transceiver iru: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Ṣe alaye oṣuwọn data ti o munadoko ni iṣelọpọ ti transceiver ti n ṣakopọ gbigbe ati awọn oke-ori miiran. Iye naa jẹ iṣiro nipasẹ IP nipasẹ yiyi to aaye eleemewa 1 ni ẹyọ Gbps.

Ipo PMA

· Ile oloke meji · Tx · Rx

Duplex

Fun iru transceiver FHT, itọsọna atilẹyin jẹ duplex nikan. Fun iru transceiver FGT, itọsọna atilẹyin jẹ Duplex, Tx, ati Rx.

Nọmba ti PMA

Fun ipo PAM4:

ona

- 1 si 12

Fun ipo NRZ:

- 1 si 16

Yan nọmba awọn ọna. Fun apẹrẹ simplex, nọmba atilẹyin ti awọn ọna jẹ 1.

PLL itọkasi aago igbohunsafẹfẹ

· Fun FHT transceiver iru: 156.25 MHz
· Fun FGT transceiver iru: 27.5 MHz 379.84375 MHz, da lori awọn ti o yan transceiver data oṣuwọn.

· Fun FHT transceiver iru: 156.25 MHz
· Fun FGT transceiver iru: 165 MHz

Sọtọka igbohunsafẹfẹ aago itọkasi ti transceiver.

Eto PLL

—

aago itọkasi

igbohunsafẹfẹ

170 MHz

Nikan wa fun FHT transceiver iru. Ni pato aago itọkasi PLL System ati pe yoo ṣee lo bi titẹ sii ti Itọkasi Tile F-Tile ati Eto PLL Awọn aago Intel FPGA IP lati ṣe ina aago PLL System.

Eto igbohunsafẹfẹ PLL
Akoko Iṣatunṣe

— 128 65536

Mu RS-FEC ṣiṣẹ

Mu ṣiṣẹ

876.5625 MHz 128 Muu ṣiṣẹ

So eto PLL aago igbohunsafẹfẹ.
Ni pato akoko asami titete. Iye gbọdọ jẹ x2. Tan-an lati mu ẹya RS-FEC ṣiṣẹ.
tesiwaju…

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Paramita

Iye

Aiyipada

Apejuwe

Pa a

Fun ipo iṣatunṣe PAM4 PCS, RS-FEC ti ṣiṣẹ nigbagbogbo.

Olumulo Interface

Ipo ṣiṣanwọle

· FULL · Ipilẹ

Ni kikun

Yan sisanwọle data fun IP.

Ni kikun: Ipo yii nfi ibere-packet ranṣẹ ati ipari-ti-packet ọmọ laarin fireemu kan.

Ipilẹ: Eyi jẹ ipo ṣiṣanwọle mimọ nibiti a ti fi data ranṣẹ laisi apo-ibẹrẹ, ofo, ati apo-ipari lati mu bandiwidi pọ si.

Mu CRC ṣiṣẹ

Mu Muu ṣiṣẹ

Pa a

Tan-an lati mu wiwa aṣiṣe CRC ṣiṣẹ ati atunse.

Mu titete laifọwọyi ṣiṣẹ

Mu Muu ṣiṣẹ

Pa a

Tan-an lati mu ẹya titete ọna aladaaṣe ṣiṣẹ.

Mu aaye ipari yokokoro ṣiṣẹ

Mu Muu ṣiṣẹ

Pa a

Nigbati ON, F-Tile Serial Lite IV Intel FPGA IP pẹlu ohun ifibọ Debug Endpoint ti o so inu inu si wiwo Avalon iranti-mapped ni wiwo. IP le ṣe awọn idanwo kan ati awọn iṣẹ yokokoro nipasẹ JTAG lilo System Console. Iye aiyipada ni Pa a.

Isopọpọ Simplex (Eto paramita yii wa nikan nigbati o yan apẹrẹ rọrun meji FGT.)

RSFEC ṣiṣẹ lori Serial Lite IV Simplex IP miiran ti a gbe si awọn ikanni FGT kanna

Mu Muu ṣiṣẹ

Pa a

Tan aṣayan yii ti o ba nilo atunto atunto pẹlu RS-FEC ṣiṣẹ ati alaabo fun F-Tile Serial Lite IV Intel FPGA IP ni apẹrẹ rọrun meji fun ipo transceiver NRZ, nibiti TX ati RX ti gbe sori FGT kanna. ikanni (awọn).

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Awọn ifihan agbara

6.1. Awọn ifihan agbara aago

Table 19. aago awọn ifihan agbara

Oruko

Iwọn Itọsọna

Apejuwe

tx_core_klout

Aago mojuto TX ti njade fun wiwo PCS aṣa TX, TX MAC ati awọn iṣiro olumulo wọle

ọna data TX.

Aago yii jẹ ipilẹṣẹ lati bulọọki PCS aṣa.

rx_core_klout

Aago mojuto RX jade fun wiwo PCS aṣa RX, RX deskew FIFO, RX MAC

ati awọn iṣiro olumulo ni ọna data RX.

Aago yii jẹ ipilẹṣẹ lati bulọọki PCS aṣa.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Aago itọkasi Transceiver ti nwọle.

Nigbati a ba ṣeto iru transceiver si FGT, so aago yii pọ si ifihan agbara ti o wu jade (out_refclk_fgt_0) ti itọkasi F-Tile ati Awọn iṣọ eto PLL Intel FPGA IP. Nigbati iru transceiver ti ṣeto si FHT, sopọ

aago yii si ifihan agbara ti o wu (out_fht_cmmpll_clk_0) ti Itọkasi Tile F-Tile ati Awọn Aago Eto PLL Intel FPGA IP.

Tọkasi Awọn paramita fun iwọn igbohunsafẹfẹ atilẹyin.

Aago igbewọle titẹ sii fun wiwo atunto transceiver.

Igbohunsafẹfẹ aago jẹ 100 si 162 MHz.

So ifihan aago titẹ sii pọ si awọn iyika aago ita tabi awọn oscillators.

Aago igbewọle titẹ sii fun wiwo atunto transceiver.

Igbohunsafẹfẹ aago jẹ 100 si 162 MHz.

So ifihan aago titẹ sii pọ si awọn iyika aago ita tabi awọn oscillators.

jade_systempll_clk_ 1

Iṣawọle

Aago PLL eto.
So aago yii pọ si ifihan agbara ti o wu (out_systempll_clk_0) ti Itọkasi Tile F-Tile ati Awọn Aago Eto PLL Intel FPGA IP.

Awọn paramita Alaye ti o jọmọ loju iwe 42

6.2. Tun awọn ifihan agbara

Table 20. Tun awọn ifihan agbara

Oruko

Iwọn Itọsọna

tx_core_rst_n

Iṣawọle

Aago ase Asynchronous

rx_core_rst_n

Iṣawọle

Asynchronous

tx_pcs_fec_phy_reset_n 1

Iṣawọle

Asynchronous

Apejuwe

Ifihan agbara-kekere atunto. Tun F-Tile Serial Lite IV TX MAC tunto.

Ifihan agbara-kekere atunto. Tun F-Tile Serial Lite IV RX MAC tunto.

Ifihan agbara-kekere atunto.

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Oruko

Ibugbe Itọnisọna aago ase

Apejuwe

Tun awọn F-Tile Serial Lite IV TX PCS aṣa.

rx_pcs_fec_phy_reset_n 1

Iṣawọle

Asynchronous

Ifihan agbara-kekere atunto. Tun awọn F-Tile Serial Lite IV RX PCS aṣa.

reconfig_reset

Iṣawọle

reconfig_clk Active-ga atunto ifihan agbara.

Tun Avalon iranti-mapped ni wiwo atunto Àkọsílẹ.

reconfig_sl_reset

Iṣagbewọle reconfig_sl_clk Ifihan agbara-giga atunto.

Tun Avalon iranti-mapped ni wiwo atunto Àkọsílẹ.

6.3. Awọn ifihan agbara MAC

Tabili 21.

Awọn ifihan agbara TX MAC
Ninu tabili yii, N ṣe aṣoju nọmba awọn ọna ti a ṣeto sinu olootu paramita IP.

Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

tx_avs_ṣetan

Ijade tx_core_clkout Avalon ṣiṣanwọle ifihan agbara.

Nigbati a ba fi idi rẹ mulẹ, tọkasi pe TX MAC ti ṣetan lati gba data.

tx_avs_data

· (64*N)*2 (ipo PAM4)
· 64*N (ipo NRZ)

Iṣawọle

tx_core_klout Avalon ifihan agbara sisanwọle. data TX.

tx_avs_ikanni

Input tx_core_clkout Avalon ifihan agbara sisanwọle.

Nọmba ikanni fun gbigbe data lori ọmọ ti isiyi.

Yi ifihan agbara ko si ni Ipilẹ mode.

tx_avs_wulo

Input tx_core_clkout Avalon ifihan agbara sisanwọle.

Nigbati a ba fi idi rẹ mulẹ, tọkasi ifihan data TX wulo.

tx_avs_startofpacket

Input tx_core_clkout Avalon ifihan agbara sisanwọle.

Nigbati a ba fi idi rẹ mulẹ, tọkasi ibẹrẹ ti apo data TX kan.

So fun nikan kan nikan aago ọmọ fun kọọkan soso.

Yi ifihan agbara ko si ni Ipilẹ mode.

tx_avs_endofpacket

Input tx_core_clkout Avalon ifihan agbara sisanwọle.

Nigbati o ba fi idi rẹ mulẹ, tọkasi opin apo data TX kan.

So fun nikan kan nikan aago ọmọ fun kọọkan soso.

Yi ifihan agbara ko si ni Ipilẹ mode.

tx_avs_ofo

Input tx_core_clkout Avalon ifihan agbara sisanwọle.

Tọkasi nọmba ti awọn ọrọ ti ko wulo ni fifọ ikẹhin ti data TX.

Yi ifihan agbara ko si ni Ipilẹ mode.

tx_num_valid_bytes_eob

Iṣawọle

tx_core_klout

Tọkasi awọn nọmba ti wulo baiti ni awọn ti o kẹhin ọrọ ti awọn ik ti nwaye. Yi ifihan agbara ko si ni Ipilẹ mode.
tesiwaju…

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Orukọ tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Ìbú 1
1 1
N 5

Aago itọsọna itọsọna

Apejuwe

Iṣawọle

tx_core_klout

Nigbati a ba fi idi rẹ mulẹ, ifihan agbara yii bẹrẹ iwifun alaye asọye olumulo kan.
So ifihan agbara yii han ni akoko aago kanna gẹgẹbi itẹnumọ tx_startofpacket.
Yi ifihan agbara ko si ni Ipilẹ mode.

Ijade tx_core_clkout Nigbati o ba fi idi rẹ mulẹ, tọkasi ọna asopọ data TX ti ṣetan fun gbigbe data.

Abajade

tx_core_klout

Nigbati a ba fi idi rẹ mulẹ, ifihan agbara yii bẹrẹ awọn ọna tito tun-titete.
So ifihan agbara yii fun aago kan lati ṣe okunfa MAC lati firanṣẹ ALIGN CW.

Iṣawọle

tx_core_clkout Nigbati o ba fi idi rẹ mulẹ, MAC fi aṣiṣe CRC32 si awọn ọna ti o yan.

Ijade tx_core_clkout Ko lo.

Awọn wọnyi ìlà aworan atọka fihan ohun Mofiample ti TX data gbigbe ti 10 ọrọ lati olumulo kannaa kọja 10 TX ni tẹlentẹle ona.

Olusin 28.

Aworan akoko Gbigbe Data TX
tx_core_klout

tx_avs_wulo

tx_avs_ṣetan

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1...,19 10,11…19 …… N-10..

0,1,2,…,9

N-10..

Ọna 0

…………

STRT 0 10

N-10 OPIN STRT 0

Ọna 1

…………

STRT 1 11

N-9 OPIN STRT 1

N-10 OPIN IDLE N-9 OPIN IDLE

Ọna 9

…………

STRT 9 19

N-1 OPIN STRT 9

N-1 OPIN IDLE IDLE

Tabili 22.

Awọn ifihan agbara RX MAC
Ninu tabili yii, N ṣe aṣoju nọmba awọn ọna ti a ṣeto sinu olootu paramita IP.

Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

rx_avs_setan

Input rx_core_clkout Avalon ifihan agbara sisanwọle.

Nigbati a ba fi idi rẹ mulẹ, tọkasi pe ọgbọn olumulo ti ṣetan lati gba data.

rx_avs_data

(64*N)*2 (ipo PAM4)
64*N (Ipo NRZ)

Abajade

rx_core_klout Avalon ifihan agbara sisanwọle. RX data.

rx_avs_ikanni

Ijade rx_core_clkout Avalon ifihan agbara ṣiṣanwọle.

Nọmba ikanni fun data jije

gba lori lọwọlọwọ ọmọ.

Yi ifihan agbara ko si ni Ipilẹ mode.

rx_avs_wulo

Ijade rx_core_clkout Avalon ifihan agbara ṣiṣanwọle.

tesiwaju…

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Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

Nigbati a ba fi idi rẹ mulẹ, tọkasi ifihan data RX wulo.

rx_avs_startofpacket

Ijade rx_core_clkout Avalon ifihan agbara ṣiṣanwọle.

Nigbati a ba fi idi rẹ mulẹ, tọkasi ibẹrẹ ti apo data RX kan.

So fun nikan kan nikan aago ọmọ fun kọọkan soso.

Yi ifihan agbara ko si ni Ipilẹ mode.

rx_avs_endofpacket

Ijade rx_core_clkout Avalon ifihan agbara ṣiṣanwọle.

Nigbati a ba fi idi rẹ mulẹ, tọkasi opin apo data RX kan.

So fun nikan kan nikan aago ọmọ fun kọọkan soso.

Yi ifihan agbara ko si ni Ipilẹ mode.

rx_avs_ofo

Ijade rx_core_clkout Avalon ifihan agbara ṣiṣanwọle.

Tọkasi nọmba ti awọn ọrọ ti ko wulo ni fifọ ikẹhin ti data RX.

Yi ifihan agbara ko si ni Ipilẹ mode.

rx_num_valid_bytes_eob

Abajade

rx_core_clkout Tọkasi awọn nọmba ti wulo baiti ni awọn ti o kẹhin ọrọ ti awọn ik ti nwaye.
Yi ifihan agbara ko si ni Ipilẹ mode.

rx_is_usr_cmd

Ijade rx_core_clkout Nigbati a ba fi idi rẹ mulẹ, ifihan agbara yii bẹrẹ olumulo kan-

telẹ alaye ọmọ.

So ifihan agbara yii han ni akoko aago kanna gẹgẹbi itẹnumọ tx_startofpacket.

Yi ifihan agbara ko si ni Ipilẹ mode.

rx_link_up

Ijade rx_core_clkout Nigbati o ba fi idi rẹ mulẹ, tọkasi ọna asopọ data RX

ti šetan fun gbigba data.

rx_link_reinit

Input rx_core_clkout Nigbati o ba fi idi rẹ mulẹ, ifihan agbara yii bẹrẹ awọn ọna

tun-titete.

Ti o ba mu Muu ṣiṣẹ Alignment laifọwọyi, sọ ami ifihan yii fun aago kan lati ma nfa MAC lati tun awọn ọna. Ti o ba ṣeto Iṣatunṣe Aifọwọyi, MAC tun-ṣe awọn ọna naa laifọwọyi.

Ma ṣe fi ifihan agbara yi han nigbati Mu ṣiṣẹ titete laifọwọyi.

rx_aṣiṣe

(N*2*2)+3 (ipo PAM4)
(N*2)*3 (Ipo NRZ)

Abajade

rx_core_klout

Nigbati a ba fi idi rẹ mulẹ, tọkasi awọn ipo aṣiṣe waye ni ọna data RX.
· [(N*2+2):N+3] = Tọkasi aṣiṣe PCS fun ọna kan pato.
· [N+2] = Tọkasi aṣiṣe titete. Ṣe atunto titete ọna ti o ba jẹ pe nkan yii ni idaniloju.
· [N+1]= Tọkasi pe a ti fi data ranṣẹ si ọgbọn olumulo nigbati ọgbọn olumulo ko ba ṣetan.
· [N] = Tọkasi ipadanu titete.
· [(N-1):0] = Tọkasi data ninu aṣiṣe CRC ninu.

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6.4. Awọn ifihan agbara atunto Transceiver

Tabili 23.

Awọn ifihan agbara atunto PCS
Ninu tabili yii, N ṣe aṣoju nọmba awọn ọna ti a ṣeto sinu olootu paramita IP.

Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

reconfig_sl_read

Input reconfig_sl_ PCS atunto atunto ka pipaṣẹ

clk

awọn ifihan agbara.

reconfig_sl_write

Input reconfig_sl_ PCS atunto atunto kọ

clk

awọn ifihan agbara aṣẹ.

reconfig_sl_adirẹsi

14 die-die + clogb2N

Iṣawọle

reconfig_sl_ clk

Pato atunto PCS Avalon ni wiwo wiwo ti o ya iranti ni ọna ti o yan.
Laini kọọkan ni awọn die-die 14 ati awọn die-die oke tọka si aiṣedeede ọna.
Example, fun apẹrẹ 4-ọna NRZ/PAM4, pẹlu reconfig_sl_address[13:0] ti o tọka si iye adirẹsi:
· reconfig_sl_address[15:1 4] ṣeto si 00 = adirẹsi fun ona 0.
· reconfig_sl_address[15:1 4] ṣeto si 01 = adirẹsi fun ona 1.
· reconfig_sl_address[15:1 4] ṣeto si 10 = adirẹsi fun ona 2.
· reconfig_sl_address[15:1 4] ṣeto si 11 = adirẹsi fun ona 3.

reconfig_sl_readata

Ijade reconfig_sl_ Sọtọ data atunto PCS

clk

lati wa ni ka nipa a setan ọmọ ni a

ti a ti yan ona.

reconfig_sl_waitrequest

Ijade reconfig_sl_ Ṣe aṣoju atunto PCS

clk

Avalon iranti-mapped ni wiwo

ifihan agbara idaduro ni ọna ti o yan.

reconfig_sl_writedata

Input reconfig_sl_ Sọtọ data atunto PCS

clk

lati wa ni kikọ lori a Kọ ọmọ ni a

ti a ti yan ona.

reconfig_sl_readdata_vali

Abajade

reconfig_sl_ Ṣeto atunto PCS

clk

data ti o gba wulo ni yiyan

ona.

Tabili 24.

Awọn ifihan agbara atunto F-Tile Lile IP
Ninu tabili yii, N ṣe aṣoju nọmba awọn ọna ti a ṣeto sinu olootu paramita IP.

Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

reconfig_read

Input reconfig_clk PMA atunto atunto ka

awọn ifihan agbara aṣẹ.

reconfig_write

Input reconfig_clk PMA atunto atunto Kọ

awọn ifihan agbara aṣẹ.

reconfig_address

18 die-die + clog2bN

Iṣawọle

reconfig_clk

Pato PMA Avalon adirẹsi wiwo iranti ti iranti ni ọna ti o yan.
tesiwaju…

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Oruko
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Ìbú
32 1 32 1

Aago itọsọna itọsọna

Apejuwe

Ni awọn ipo PAM4 ad NRZ mejeeji, ọna kọọkan ni awọn die-die 18 ati awọn iwọn oke ti o ku n tọka si aiṣedeede ọna.
Example, fun apẹrẹ ọna 4:
· reconfig_address[19:18] ṣeto si 00 = adirẹsi fun ona 0.
· reconfig_address[19:18] ṣeto si 01 = adirẹsi fun ona 1.
· reconfig_address[19:18] ṣeto si 10 = adirẹsi fun ona 2.
· reconfig_address[19:18] ṣeto si 11 = adirẹsi fun ona 3.

Abajade

reconfig_clk Ṣe alaye data PMA lati ka nipasẹ ọmọ ti o ṣetan ni ọna ti o yan.

Abajade

reconfig_clk Ṣe aṣoju PMA Avalon memorymapped ni wiwo stalling ifihan agbara ni a yan ona.

Iṣawọle

reconfig_clk Ṣe alaye data PMA lati kọ sori ọmọ kikọ ni ọna ti o yan.

Abajade

reconfig_clk Ṣe alaye atunto PMA ti o gba data wulo ni ọna ti o yan.

6.5. Awọn ifihan agbara PMA

Tabili 25.

Awọn ifihan agbara PMA
Ninu tabili yii, N ṣe aṣoju nọmba awọn ọna ti a ṣeto sinu olootu paramita IP.

Oruko

Ìbú

Aago itọsọna itọsọna

Apejuwe

phy_tx_lanes_stable

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous Nigbati o ba fi idi rẹ mulẹ, tọkasi ọna data TX ti ṣetan lati fi data ranṣẹ.

tx_pll_locked

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous Nigbati o ba fi idi rẹ mulẹ, tọkasi TX PLL ti ṣaṣeyọri ipo titiipa.

phy_ehip_setan

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous

Nigbati a ba fi idi rẹ mulẹ, tọka pe PCS aṣa ti pari ipilẹṣẹ inu ati ṣetan fun gbigbe.
Yi ifihan agbara asserts lẹhin tx_pcs_fec_phy_reset_n ati tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

O wu TX ni tẹlentẹle aago TX ni tẹlentẹle awọn pinni.

rx_serial_data

Input RX ni tẹlentẹle aago RX ni tẹlentẹle awọn pinni.

phy_rx_block_lock

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous Nigbati a ba fi idi rẹ mulẹ, tọkasi pe titete bulọki 66b ti pari fun awọn ọna.

rx_cdr_lock

N*2 (ipo PAM4)

Abajade

Asynchronous

Nigbati a ba fi idi rẹ mulẹ, tọkasi pe awọn aago ti o gba pada wa ni titiipa si data.
tesiwaju…

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Orukọ phy_rx_pcs_ready phy_rx_hi_ber

Ìbú

Aago itọsọna itọsọna

Apejuwe

N (Ipo NRZ)

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous

Nigbati a ba fi idi rẹ mulẹ, tọkasi pe awọn ọna RX ti ikanni Ethernet ti o baamu ni ibamu ni kikun ati ṣetan lati gba data.

N*2 (ipo PAM4)
N (Ipo NRZ)

Abajade

Asynchronous

Nigbati a ba fi idi rẹ mulẹ, tọkasi pe RX PCS ti ikanni Ethernet ti o baamu wa ni ipo HI BER kan.

F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo 50

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7. Ṣiṣe pẹlu F-Tile Serial Lite IV Intel FPGA IP

7.1. Awọn Itọsọna Tunto
Tẹle awọn itọsona atunto wọnyi lati ṣe atunto ipele eto rẹ.
Di tx_pcs_fec_phy_reset_n ati awọn ifihan agbara rx_pcs_fec_phy_reset_n papo lori ipele eto lati tun TX ati RX PCS pada nigbakanna.
· Sọ tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, ati awọn ifihan agbara atunto_reset ni akoko kanna. Tọkasi Tunto ati Ibẹrẹ Ọna asopọ fun alaye diẹ sii nipa atunto IP ati awọn ilana ibẹrẹ.
Mu tx_pcs_fec_phy_reset_n, ati awọn ifihan agbara rx_pcs_fec_phy_reset_n kekere, ati ifihan agbara reconfig_reset ga ati duro de tx_reset_ack ati rx_reset_ack lati tun IP lile F-tile daradara ati awọn bulọọki atunto.
Lati ṣaṣeyọri ọna asopọ iyara laarin awọn ẹrọ FPGA, tunto F-Tile Serial Lite IV Intel FPGA IPs ti a ti sopọ ni akoko kanna. Tọkasi F-Tile Serial Lite IV Intel FPGA IP Design Example Itọsọna Olumulo fun alaye nipa mimojuto IP TX ati ọna asopọ RX nipa lilo ohun elo irinṣẹ.
Alaye ti o jọmọ
· Tunto ati Ibẹrẹ Ọna asopọ ni oju-iwe 37
· F-Tile Serial Lite IV Intel FPGA IP Design Eksample User Itọsọna

7.2. Awọn Itọsọna Mimu Aṣiṣe

Tabili ti o tẹle ṣe atokọ awọn itọnisọna mimu aṣiṣe fun awọn ipo aṣiṣe eyiti o le waye pẹlu apẹrẹ F-Tile Serial Lite IV Intel FPGA IP apẹrẹ.

Table 26. Aṣiṣe Ipò ati mimu Awọn Itọsọna

Ipo aṣiṣe
Ọna kan tabi diẹ ẹ sii ko le fi idi ibaraẹnisọrọ mulẹ lẹhin fireemu akoko ti a fun.

Awọn itọnisọna
Ṣiṣe eto akoko-akoko lati tun ọna asopọ pada ni ipele ohun elo.

Ọna kan padanu ibaraẹnisọrọ lẹhin ibaraẹnisọrọ ti iṣeto.
Ọna kan padanu ibaraẹnisọrọ lakoko ilana deskew.

Eyi le ṣẹlẹ lẹhin tabi lakoko awọn ipele gbigbe data. Ṣiṣe wiwa ipadanu ọna asopọ ni ipele ohun elo ati tun ọna asopọ naa.
Ṣiṣe ilana isọdọtun ọna asopọ fun ọna asise. O gbọdọ rii daju pe ipa-ọna igbimọ ko kọja 320 UI.

Titete ọna ipadanu lẹhin ti gbogbo awọn ọna ti wa ni deedee.

Eyi le ṣẹlẹ lẹhin tabi lakoko awọn ipele gbigbe data. Ṣe iṣawari ipadanu titete ọna ọna ni ipele ohun elo lati tun bẹrẹ ilana titete ọna.

ISO 9001: 2015 forukọsilẹ

683074 | 2022.04.28 Firanṣẹ esi

8. F-Tile Serial Lite IV Intel FPGA IP Itọsọna olumulo Archives

Awọn ẹya IP jẹ kanna bi awọn ẹya sọfitiwia Intel Quartus Prime Design Suite to v19.1. Lati Intel Quartus Prime Design Suite sọfitiwia ẹya 19.2 tabi nigbamii, awọn ohun kohun IP ni ero ikede IP tuntun kan.

Ti ẹya IP mojuto ko ba ṣe akojọ, itọsọna olumulo fun ẹya IP mojuto ti tẹlẹ kan.

Intel Quartus NOMBA Version
21.3

IP Core Version 3.0.0

Itọsọna olumulo F-Tile Serial Lite IV Intel® FPGA IP Itọsọna olumulo

ISO 9001: 2015 forukọsilẹ

683074 | 2022.04.28 Firanṣẹ esi

9. Itan Atunyẹwo iwe fun F-Tile Serial Lite IV Intel FPGA IP Itọsọna olumulo

Iwe ikede 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus NOMBA Version
22.1
21.3 21.3 21.2

Ẹya IP 5.0.0
3.0.0 3.0.0 2.0.0

Awọn iyipada
Tabili ti a ṣe imudojuiwọn: F-Tile Serial Lite IV Awọn ẹya Intel FPGA IP - Apejuwe Gbigbe data imudojuiwọn pẹlu afikun atilẹyin oṣuwọn transceiver FHT: 58G NRZ, 58G PAM4, ati 116G PAM4
Tabili ti a ṣe imudojuiwọn: F-Tile Serial Lite IV Intel FPGA IP Parameter Apejuwe - Fikun paramita tuntun · Eto igbohunsafẹfẹ aago ọna kika PLL · Mu ipari yokokoro ṣiṣẹ - Ṣe imudojuiwọn Awọn iye fun oṣuwọn data PMA - Iforukọsilẹ paramita lati baramu GUI
· Ṣe imudojuiwọn apejuwe fun gbigbe data ni Tabili: F-Tile Serial Lite IV Intel FPGA IP Awọn ẹya ara ẹrọ.
Orukọ tabili lorukọ IP si F-Tile Serial Lite IV Intel FPGA IP Parameter Apejuwe ni apakan Awọn paramita fun mimọ.
Tabili ti a ṣe imudojuiwọn: Awọn paramita IP: - Fikun paramita tuntun kan–RSFEC ṣiṣẹ lori Serial Lite IV Simplex IP miiran ti a gbe si ikanni FGT kanna. - Ṣe imudojuiwọn awọn iye aiyipada fun igbohunsafẹfẹ itọkasi aago Transceiver.
Itusilẹ akọkọ.

ISO 9001: 2015 forukọsilẹ

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	intel F Tile Serial Lite IV Intel FPGA IP [pdf] Itọsọna olumulo F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Itọsọna olumulo F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

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Itọsọna olumulo

F Tile Serial Lite IV Intel FPGA IP

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