VHDLwhiz UART Test Interface Jenereyitha Incwadi yoMsebenzisi

Le mveliso ikuvumela ukuba wenze ujongano lwesiko lokufunda nokubhala amaxabiso erejista yeFPGA usebenzisa i-UART. Imodyuli eyenziwe yeVHDL kunye neskripthi sePython sibonelela ngokukwazi ukusebenzisana neentlobo ezahlukeneyo zobhaliso kuyilo lwakho lweFPGA.

Iimfuno

Itoliki yePython 3
iphakheji yepyserial

Umgaqo-nkqubo

Imveliso isebenzisa iprotocol yokuqulunqa idatha eneempawu zolawulo ezine:

Igama: FUNDA_REQ, Ixabiso: 0x0A - Umyalelo ovela kumamkeli ukuya kwiFPGA ukuqalisa ngokubhala ulandelelwano ukuthumela zonke iirejista emva kwe-UART
Igama: START_BHALA, Ixabiso: 0x0B – Iphawula isiqalo solandelelwano lokubhala nakweliphi na icala

Igama: END_BHALA, Ixabiso: 0x0C – Uphawula isiphelo solandelelwano lokubhala kulo naliphi na icala
Igama: BALEKA, Ixabiso: I-0x0D-Umlinganiswa obalekayo osetyenziselwa ukubaleka amagama olawulo

Imiyalelo yokusetyenziswa kwemveliso

Ukuqhuba izikripthi

Ukusebenzisa imveliso, qinisekisa ukuba unePython 3 efakiweyo kunye nephakheji yePyserial. Qhuba izikripthi ngetoliki yePython 3.

Ukuvelisa i-Custom Interfaces

Sebenzisa i-gen_uart_regs.py script ukuvelisa ujongano lwesiko lokufunda nokubhala amaxabiso erejista yeFPGA. Ungakhankanya ukubunjwa kwegalelo kunye neerejista zemveliso kunye neentlobo xa uvelisa imveliso files.

Ukusebenzisana neerejista

Unokufunda ukusuka okanye ubhale kulo naliphi na inani leerejista kuyilo lwakho lweFPGA usebenzisa imodyuli eyenziweyo yeVHDL kunye nescript yePython. Iirejista ezifikelelekayo zinokuba neentlobo ezifana ne-std_logic, std_logic_vector, esayiniweyo, okanye engasayinwanga.

Ilayisensi

Ilayisensi ye-MIT ibandakanya ikhowudi yomthombo iimfuno zelungelo lokushicilela kunye nemigaqo yokusetyenziswa. Jonga kwi-LICENSE.txt file kwi Zip file ngeenkcukacha.

Changelog

Olu tshintsho lubhekisa kwiprojekthi files, kwaye olu xwebhu luhlaziywa ngokufanelekileyo

Inguqulelo	Amagqabantshintshi
1.0.0	Ukukhutshwa kokuqala
1.0.1	Kulungiswe ukulahleka "kwakho" ireferensi yegciwane xa ungenisa njenge uart_regs.py njengemodyuli yePython. Ubhalo olutshintshiweyo aluphumelelanga ukuya kushicilelo Kunqanda ushicilelo kwiconsole xa usebenza njengemodyuli ethathwa ngaphandle.
1.0.2	Lungisa impazamo yeVivado [i-Synth 8-248] xa kungekho ndlela yokuphuma regs.
1.0.3	Lungisa isilumkiso seVivado Linter: Irejista yenziwe iqhutywa yi ukusetha kwakhona ngongqamaniso
1.0.4	Lungisa ikona xa ufumana igama elingalunganga elinophawu lokubaleka njengebhayithi yokugqibela. Igama elilandelayo nalo lingalahleka kuba asizange siyicime i-recv_data_prev_is_escape xa sibuyela kwi-IDLE. Iskripthi se-gen_uart_regs.py ngoku sivumela kuphela amagama awodwa ereg.

Inkcazo

Olu xwebhu luchaza oku kulandelayo files kunye neefolda:
gen_uart_regs.py

yenziwe/uart_regs.vhd
generated/uart_regs.py
generated/instantiation_template.vho
rtl/uart_regs_backend.vhd
rtl/uart_rx.vhd
rtl/uart_tx.vhd
idemo/umthi_womkhenkce/
idemo/xilinx_arty_a7_35/
demo/xilinx_arty_s7_50/
Iskripthi se-gen_uart_regs.py kunye ne-VHDL exhasayo files kule projekthi ikuvumela ukuba wenze ujongano lwesiko lokufunda nokubhala amaxabiso erejista yeFPGA yeentlobo ezahlukeneyo kunye nobubanzi usebenzisa i-UART.
Ungasebenzisa imodyuli yeVHDL eyenziweyo kunye neskripthi sePython ukufunda okanye ukubhala kulo naliphi na inani lerejista kuyilo lwakho. Iirejista ezifikelelekayo ze-UART zinokuba neentlobo std_logic, std_logic_vector, esayiniweyo, okanye engasayinwanga.
Unokwenza isigqibo malunga nokwakhiwa okuchanekileyo kwegalelo kunye neerejista zemveliso kunye neentlobo xa uvelisa imveliso files usebenzisa i-gen_uart_regs.py script.
Izikripthi zePython zenziwe ngokuyinxenye ngoncedo lwesixhobo sobukrelekrele bokwenziwa kwe-ChatGPT, ngelixa ikhowudi ye-VHDL yenziwe ngesandla.

Iimfuno

Iincwadi zeempendulo kule projekthi maziqhutywe ngetoliki yePython 3 kwaye makufakwe iPyserial package.
Ungayifaka i-pyserial ngePip usebenzisa lo myalelo: ipip ufake ipyserial

Umgaqo-nkqubo

I-VHDL files kunye neskripthi sePython sisebenzisa iprotocol yokuqulunqa idatha enolawulo olune

Igama	Ixabiso	Comment
FUNDA_REQ	0x0A	Umyalelo osuka kumamkeli oya kwi FPGA ukuze uqalise ukubhala Ukulandelelanisa ukuthumela zonke iirejista emva kwe-UART
START_BHALA	0x0B	Uphawula isiqalo solandelelwano lokubhala kuyo nayiphi na ulwalathiso
END_BHALA	Ngama-0x0C	Uphawula isiphelo solandelelwano lokubhala kulo naliphi na icala
BALEKA	0x0D	Umbhalo we-Escape osetyenziselwa ukubaleka nawaphina amagama olawulo, ukuquka ESCAPE umbhalo ngokwawo, xa avela njengedatha phakathi kwe START_WRITE kunye END_WRITE izimakishi.

Nayiphi na i-READ_REQ byte engabalekanga ethunyelwe kwi-FPGA ngumyalelo wokuthumela zonke iirejista zayo ezifikelelekayo ze-UART (amagalelo kunye neziphumo) emva kumamkeli ngaphezulu kwe-UART. Lo myalelo udla ngokukhutshwa kuphela siscript uart_regs.py.
Ekufumaneni lo myalelo, i-FPGA iya kuphendula ngokuthumela umxholo wazo zonke iirejista emva kumamkeli. Okokuqala, imiqondiso yegalelo, emva koko imiqondiso yokuphuma. Ukuba ubude bazo abudibanisi ukuya kuphinda-phindo lwe-bits ezisi-8, amasuntswana asezantsi ebhayithi yokugqibela azakuba nooziro.
Ulandelelwano lokubhala luhlala luqala nge- START_WRITE byte kwaye iphele nge- END_WRITE byte. Naziphi na ii-bytes phakathi kwezo zithathwa njenge-data bytes. Ukuba nayiphi na i-byte yedatha inexabiso elifanayo njengophawu lolawulo, i-byte yedatha kufuneka ibaleke. Oku kuthetha ukuthumela umbhalo owongezelelweyo we-ESCAPE phambi kwe-byte yedatha ukubonisa ukuba ngokwenene yidatha.
Ukuba i-START_WRITE engabalekanga ifika naphina kuluhlu lwee-bytes, ithathwa njengesiqalo solandelelwano lokubhala. Imodyuli ye-uart_regs_backend isebenzisa olu lwazi ukuvumelanisa kwakhona kwimeko apho unxibelelwano luphuma ku-sync.

gen_uart_regs.py

Esi siscript kufuneka uqale ngaso ukwenza ujongano. Ngezantsi ngumfanekiso wekhusi wemenyu yoncedo onokuyifumana ngokuqhuba: python gen_uart_regs.py -h
Ukuvelisa ujongano lwesiko, kufuneka uqhube okushicilelweyo ngerejista nganye oyifunayo ye-UART elawulekayo edweliswe njengeempikiswano. Iindidi ezikhoyo zezi std_logic, std_logic_vector, engasayinwanga, kwaye yasayinwa.
Indlela engagqibekanga (umkhomba-ndlela) ingaphakathi kwaye uhlobo olungagqibekanga luyi std_logic_vector ngaphandle kokuba irejista inobude: 1. Emva koko, iya kungagqibekanga ku std_logic.

Ke, ukuba ufuna ukwenza isiginali yegalelo std_logic, ungasebenzisa naziphi na ezi mpikiswano:
yam_sl=1
my_sl=1:ngaphakathi

my_sl=1:in:std_logic
Zonke ezi zantlukwano zingasentla ziya kubangela ukuba iskripthi sivelise olu phawu lufikelelekayo lwe-UART:
Masiqhube iskripthi ngeengxoxo ukuvelisa ujongano kunye neerejista ezininzi zezalathiso ezahlukeneyo, ubude, kunye neendidi.

Yenziwe files

Ukubaleka okuyimpumelelo kweskripthi se-gen_uart_regs.py siyakuvelisa isiqulathi seefayili esibizwa ngokuba senziwe ngezithathu. files zidweliswe ngezantsi. Ukuba sele zikhona, ziya kubhalwa ngaphezulu.
yenziwe/uart_regs.vhd

generated/uart_regs.py
generated/instantiation_template.vho
uart_regs.vhd

Le yimodyuli yojongano lwesiko elenziwe siscript. Kufuneka uyiqinise kuyilo lwakho, apho inokufikelela kwiirejista ofuna ukuzilawula usebenzisa i-UART.
Yonke into engaphezulu kwecandelo elithi "- UART iirejista ezifikelelekayo" iya kufana nayo yonke imodyuli ye-uart_regs, ngelixa ukubunjwa kweempawu ze-port ngaphantsi kwaloo mgca kuxhomekeke kwiingxoxo ezinikwe iscript generator.
Udweliso olungezantsi lubonisa umbutho we uart_regs imodyuli ephuma kwimveliso yomyalelo exampiboniswe kwicandelo le-gen_uart_regs.py

Awudingi ukwenza ngaxeshanye uphawu lwe-uart_rx, njengoko luphathwa kwi-uart_rx. imodyuli.
Xa imodyuli ifumana isicelo sokufunda, iya kubamba amaxabiso azo zonke igalelo kunye neempawu zemveliso ngaphakathi komjikelo wewotshi yangoku. Umfanekiso okhawulezayo uthunyelwa kumamkeli nge-UART.
Xa ukubhalwa kusenzeka, zonke iirejista zemveliso zihlaziywa ngamaxabiso amatsha ngaphakathi komjikelo wewotshi efanayo. Akunakwenzeka ukutshintsha amaxabiso ophawu lwemveliso ngokwahlukeneyo.

Nangona kunjalo, iskripthi se-uart_regs.py sivumela umsebenzisi ukuba ahlaziye kuphela iziphumo ezikhethiweyo ngokufunda kuqala amaxabiso akhoyo azo zonke iirejista. Emva koko ibhala onke amaxabiso, kuquka nalawo ahlaziyiweyo.
uart_regs.py
I- generated/uart_regs.py file uveliswa kunye nemodyuli ye-uart_regs yeVHDL kwaye iqulethe ulwazi lwerejista yesiko kwiheda ye file. Ngesi script, unokufunda ukusuka okanye ubhale kwiirejista zakho zesiko ngokulula.

Imenyu yoncedo

Chwetheza i-python uart_regs.py -h ukuprinta imenyu yoncedo:

Ukumisela izibuko le-UART

Umbhalo uneenketho zokuseta izibuko le UART usebenzisa i -c switch. Oku kusebenza kwiiWindows kunye neLinux. Yimisele kwelinye lamazibuko akhoyo adweliswe kwimenyu yoncedo. Ukuseta izibuko elingagqibekanga, ungahlela kwakhona i-UART_PORT eguquguqukayo kwiskripthi se-uart_regs.py.

Uluhlu lweerejista

Ulwazi malunga nerejista yokwenza imephu ibekwe kwiheda yeskripthi se-uart_regs.py ngeskripthi se-gen_uart_regs.py. Ungadwelisa iirejista ezikhoyo kunye ne--l switch, njengoko kubonwe ngezantsi. Lo ngumyalelo wasekhaya kwaye awuzukusebenzelana neFPGA ekujoliswe kuyo

Ukubhala kwiirejista

Ungabhalela kuyo nayiphi na irejista yendlela yokuphuma ngokusebenzisa i -w switch. Nika igama lerejista elilandelwa ngu "=" kunye nexabiso elinikiweyo njengokubini, i-hexadecimal, okanye ixabiso lokugqibela, njengoko kubonisiwe ngezantsi.
Qaphela ukuba ukuphunyezwa kweVHDL kufuna ukuba iskripthi sibhale zonke iirejista zemveliso ngaxeshanye. Ngoko ke, ukuba awukhankanyi uluhlu olupheleleyo lweerejista zemveliso, okushicilelweyo kuqala kuzakufunda kwi FPGA ekujoliswe kuyo kwaye emva koko usebenzise loo maxabiso kwezi zilahlekileyo. Isiphumo siya kuba kukuba kuphela iirejista ezichaziweyo zitshintsha
Xa ubhala, zonke iirejista ezichaziweyo ziya kutshintsha ngexesha lomjikelo wewotshi enye, hayi nje ukuba zifunyenwe nge-UART.

Iirejista zokufunda

Sebenzisa i -r switch ukufunda onke amanani erejista, njengoko kubonisiwe ngezantsi. Amaxabiso aphawulwe ngomthubi ngala sitshintshe kwi-ex yangaphambili yokubhalaample
Ufundo ngalunye lubonisa umfanekiso okhawulezayo walo lonke igalelo kunye neerejista zemveliso. Bonke ba-sampikhokelwa ngexesha lomjikelo wewotshi efanayo

Ukulungisa ingxaki

Sebenzisa i--d switch kunye naluphi na olunye utshintsho ukuba ufuna ukulungisa iprotocol yonxibelelwano. Emva koko, iskripthi siya kuprinta zonke iibytes ezithunyelweyo nezifunyenweyo kunye tag bona ukuba ngabalinganiswa bolawulo, njengoko kubonisiwe ngezantsi.

Ukusebenzisa ujongano kwezinye izikripthi zePython

Iskripthi se-uart_regs.py siqulethe iklasi ye-UartRegs onokuyisebenzisa ngokulula njengojongano lonxibelelwano kwezinye izikripthi zePython zesiko. Ngenisa nje iklasi, yenza into yayo, kwaye uqale ukusebenzisa iindlela, njengoko kuboniswe ngezantsi.

Jonga kwi-docstrings kwikhowudi yePython yendlela kunye neenkcazo kunye neentlobo zexabiso lokubuyisela.

instantiation_template.vho

Ithempleyithi ye-instantiation yenziwe kunye nemodyuli ye-uart_regs ukulungiselela wena. Ukugcina ixesha lokubhala ikhowudi, unokukopa imodyuli yemodyuli kunye nezibhengezo zomqondiso kuyilo lwakho.

I-RTL engatshintshiyo files

Kufuneka ubandakanye oku kulandelayo files kwiprojekthi yakho yeVHDL ukuze zihlanganiswe kwithala leencwadi elifanayo njengemodyuli ye-uart_regs:
rtl/uart_regs_backend.vhd

rtl/uart_rx.vhd
rtl/uart_tx.vhd
Imodyuli ye-uart_regs_backend isebenzisa oomatshini be-finite-state abavala kwaye bakhuphe idatha yerejista. Isebenzisa iimodyuli ze-uart_rx kunye ne-uart_tx ukuphatha unxibelelwano lwe-UART kunye nomamkeli.

Iiprojekthi zedemo

Kukho iiprojekthi ezintathu zedemo ezibandakanyiweyo kwiZip file. Bakuvumela ukuba ulawule iiperipherals kwiibhodi ezahlukeneyo kunye neerejista ezinkulu ezimbalwa, zangaphakathi.
Iifolda zedemo zibandakanya uart_regs.vhd eyenziwe kwangaphambili kunye ne-uart_regs.py fileyenziwe ngokukodwa ezo ziyilo.

I-Lattice iCEstick

Idemo/icecube2_icestick ifolda iqulethe idemo yokufikelela kwirejista yophumezo yebhodi yeLattice iCEstick FPGA.
Ukuqhuba inkqubo yophumezo, vula idemo/lattice_icestick/icecube2_proj/uart_regs_sbt.project file kwiLattice iCEcube2 uyilo lwesoftware.
Emva kokulayisha iprojekthi kwi-iCEcube2 GUI, cofa iZixhobo→Balekisa Konke ukwenza ibitmap yodweliso lwenkqubo. file.

Ungasebenzisa iLattice Diamond Programmer isixhobo esizimeleyo ukuqwalasela iFPGA nge bitmap eyenziweyo. file. Xa uMdwelisi weDayimane evula, cofa Vula iprojekthi ekhoyo yomdwelisi kwibhokisi yencoko yababini eyamkelekileyo.
Khetha iprojekthi file ifumaneka kwi-Zip: demo/lattice_icestick/diamond_programmer_project.xcf kwaye ucofe u-Kulungile.
Emva kokulayisha iprojekthi, cofa amachaphaza amathathu kwi File Uluhlu lwegama, njengoko kubonisiwe ngasentla. Bhrawuza ukukhetha i-bitmap file oyenzileyo kwi-icecube2

demo/lattice_icestick/icecube2_proj/uart_regs_Implmnt/sbt/outputs/bitmap/top_icestick_bitmap.bin
Okokugqibela, ngebhodi ye-iCEstick eplagiwe kwizibuko le-USB kwikhompyuter yakho, khetha uYilo→ Inkqubo yokucwangcisa iflash yeSPI kwaye uqwalasele iFPGA.
Ungaqhubeka ngoku ukufunda nokubhala iirejista ngokusebenzisa idemo/lattice_icestick/uart_regs.py umbhalo njengoko kuchaziwe kwicandelo uart_regs.py.

I-Xilinx Digilent Arty A7-35T

Ungafumana ukuphunyezwa kwedemo yeArtix-7 35T Arty FPGA evaluation kit kwi demo/arty_a7_35 folda.
Vula iVivado kwaye uhambe uye kwi-extracted files usebenzisa i Tcl console efunyenwe ezantsi kujongano lwe GUI. Chwetheza lo myalelo ukufaka isiqulathi seefayili zeprojekthi yedemo:

cd /demo/arty_a7_35/vivado_proj/
Yenza iskripthi se-creement_vivado_proj.tcl Tcl ukuvuselela iprojekthi yeVivado:
umthombo ./create_vivado_proj.tcl

Cofa ukuvelisa i-Bitstream kwibar esecaleni ukuze usebenze kuwo onke amanyathelo okuphunyezwa kwaye uvelise i-bitstream yeprogram file.
Okokugqibela, cofa i-Vula i-Hardware Manager kwaye inkqubo ye-FPGA nge-GUI.
Ngoku ungaqhubeka ufunda kwaye ubhale iirejista ngokusebenzisa idemo/arty_a7_35/uart_regs.py script njengoko kuchaziwe kwicandelo uart_regs.py.

Xilinx Digilent Arty S7-50

Ungafumana ukuphunyezwa kwedemo ye-Arty S7: Spartan-7 FPGA ibhodi yophuhliso kwi-demo/arty_s7_50 ifolda.
Vula iVivado kwaye uhambe uye kwi-extracted files usebenzisa i Tcl console efunyenwe ezantsi kujongano lwe GUI. Chwetheza lo myalelo ukufaka isiqulathi seefayili zeprojekthi yedemo:

cd /demo/arty_s7_50/vivado_proj/
Yenza iskripthi se-creement_vivado_proj.tcl Tcl ukuvuselela iprojekthi yeVivado:
umthombo ./create_vivado_proj.tcl

Cofa ukuvelisa i-Bitstream kwibar esecaleni ukuze usebenze kuwo onke amanyathelo okuphunyezwa kwaye uvelise i-bitstream yeprogram file.
Okokugqibela, cofa i-Vula i-Hardware Manager kwaye inkqubo ye-FPGA nge-GUI.
Ngoku ungaqhubeka ufunda kwaye ubhale iirejista ngokusebenzisa idemo/arty_s7_50/uart_regs.py script njengoko kuchaziwe kwicandelo uart_regs.py.

Ukuphunyezwa

Akukho mfuno zikhethekileyo zokuphunyezwa.

Izithintelo

Akukho miqobo yexesha efunekayo kolu yilo kuba ujongano lwe-UART lucotha kwaye luphathwa njengojongano olungena-asynchronous.

Igalelo le-uart_rx kwimodyuli ye-uart_regs ilungelelaniswe ngaphakathi kwimodyuli ye-uart_rx. Ke, akufuneki ukuba idityaniswe kwimodyuli ekwinqanaba eliphezulu.

Imiba eyaziwayo

Kusenokufuneka umise kwakhona imodyuli phambi kokuba isetyenziswe, kuxhomekeke ekubeni iFPGA yakho yezakhiwo iyawaxhasa amaxabiso erejista angagqibekanga.

Iinkcukacha ezithe vetshe

Ilungelo lokushicilela VHDLwhiz.com

Ii-FAQs

Q: Yintoni injongo yokwenziwa kojongano lwe-UART?

A: I-UART test interface generator ivumela ukudalwa kojongano lwesiko ukusebenzisana nemilinganiselo yerejista yeFPGA usebenzisa unxibelelwano lwe-UART.

Umbuzo: Ndiyifaka njani iphakheji yePyserial?

A: Ungayifaka iPyserial ngePip usebenzisa umyalelo: pip ufake ipyserial

Amaxwebhu / Izibonelelo

VHDLwhiz UART Test Interface Generator [pdf] Incwadi yokusebenzisa
UART Test Interface Generator, Test Interface Generator, Interface Generator, Generator

Iimbekiselo

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VHDLwhiz UART Test Interface Generator

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