VHDLwhiz UART Gwajin Interface Generator Manual

Wannan samfurin yana ba ku damar ƙirƙirar musaya na al'ada don karantawa da rubuta ƙimar rijistar FPGA ta amfani da UART. Samfuran VHDL da rubutun Python suna ba da ikon yin hulɗa tare da nau'ikan rajista iri-iri a cikin ƙirar FPGA ku.

Abubuwan bukatu

Python 3 mai fassara
kunshin pyserial

Yarjejeniya

Samfurin yana amfani da ƙa'idar tsara bayanai tare da haruffa masu sarrafawa huɗu:

Suna: KARANTA_REQ, Darajar: 0x0A - Umurni daga mai watsa shiri zuwa FPGA don fara jerin rubuta don aika duk rajista akan UART
Suna: START_RUBUTA, Darajar: 0x0B - Alamar farkon jerin rubuce-rubuce ta kowane bangare

Suna: END_RUBUTA, Darajar: 0x0C - Alamar ƙarshen jerin rubuce-rubuce ta kowane bangare
Suna: TSIRA, Darajar: 0x0D - Halin tserewa da aka yi amfani da shi don guje wa kalmomin sarrafawa

Umarnin Amfani da samfur

Gudanar da Rubutun

Don amfani da samfurin, tabbatar cewa an shigar da Python 3 da kunshin Pyserial. Gudanar da rubutun ta hanyar fassarar Python 3.

Ƙirƙirar Mu'amala ta Musamman

Yi amfani da rubutun gen_uart_regs.py don samar da mu'amala ta al'ada don karantawa da rubuta ƙimar rijistar FPGA. Kuna iya ƙididdige abun da ke ciki na rajistar shigarwa da fitarwa da nau'ikan lokacin samar da fitarwa files.

Yin hulɗa tare da masu rijista

Kuna iya karantawa ko rubuta zuwa kowane adadin rajista a cikin ƙirar ku ta FPGA ta amfani da ƙirar VHDL da rubutun Python. Rijistar da ake samu na iya samun nau'ikan kamar std_logic, std_logic_vector, sanya hannu, ko ba a sanya hannu ba.

Lasisi

Lasisin MIT ya ƙunshi buƙatun haƙƙin mallaka na lambar tushe da sharuɗɗan amfani. Koma zuwa LICENSE.txt file cikin zip file don cikakkun bayanai.

Canji

Waɗannan canje-canje suna nufin aikin files, kuma an sabunta wannan takarda daidai da haka

Sigar	Jawabi
1.0.0	Sakin farko
1.0.1	Kafaffen batan "kai" bug lokacin da ake shigo da shi azaman uart_regs.py azaman tsarin Python. Canza rubutun da ya gaza bugawa zuwa keɓe ga kauce wa bugu zuwa na'ura wasan bidiyo yayin aiki azaman ƙirar da aka shigo da ita.
1.0.2	Gyara don Kuskuren Vivado [Synth 8-248] lokacin da babu yanayin yanayin waje.
1.0.3	Gyara Vivado Linter Gargadi: Rijista ya kunna ta sake saitin aiki tare
1.0.4	Gyara yanayin kusurwa lokacin karɓar kalmar da ba daidai ba tare da halin tserewa azaman byte na ƙarshe. Za a rasa kalmar ta gaba saboda ba mu share recv_data_prev_is_escape lokacin komawa IDLE ba. Rubutun gen_uart_regs.py yanzu yana ba da sunaye na musamman kawai.

Bayani

Wannan takarda ta bayyana abubuwan da ke biyowa files da manyan fayiloli:
gen_uart_regs.py

generated/uart_regs.vhd
generated/uart_regs.py
generated/instantiation_template.vho
rtl/uart_regs_backend.vhd
rtl/uart_rx.vhd
rtl/uart_tx.vhd
demo/lattice_icestick/
demo/xilinx_arty_a7_35/
demo/xilinx_arty_s7_50/
Rubutun gen_uart_regs.py da goyon bayan VHDL files a cikin wannan aikin yana ba ku damar samar da musaya na al'ada don karantawa da rubuta ƙimar rijistar FPGA na nau'ikan nau'ikan da faɗin iri daban-daban ta amfani da UART.
Kuna iya amfani da tsarin VHDL da aka ƙirƙira da rubutun Python don karantawa daga ko rubuta zuwa kowane adadin rajista a cikin ƙirar ku. Masu rijistar UART na iya samun nau'ikan std_logic, std_logic_vector, sanya hannu, ko rashin sa hannu.
Kuna iya yanke shawara akan madaidaicin abubuwan shigarwa da rajistar shigarwa da nau'ikan lokacin samar da fitarwa files ta amfani da rubutun gen_uart_regs.py.
Rubutun Python an ƙirƙiri wani yanki ne tare da taimakon kayan aikin leken asiri na ChatGPT, yayin da lambar VHDL aka yi da hannu.

Abubuwan bukatu

Rubutun da ke cikin wannan aikin dole ne a gudanar da su ta hanyar fassarar Python 3 kuma dole ne a shigar da kunshin Pyserial.
Kuna iya shigar da pyserial ta hanyar Pip ta amfani da wannan umarni: pip install pyserial

Yarjejeniya

Farashin VHDL files da rubutun Python suna amfani da ka'idar tsara bayanai tare da sarrafawa guda huɗu

Suna	Daraja	Sharhi
KARANTA_REQ	0x0A	Umurni daga mai watsa shiri zuwa FPGA don fara rubutu jerin don aika duk rajistar baya akan UART
START_RUBUTA	0x0B	Alamar farkon jerin rubutun a cikin ko wanne hanya
END_RUBUTA	0x0c ku	Alamar ƙarshen jerin rubutun a kowane bangare
TSIRA	0 x0d	Halayen tserewa da aka yi amfani da su don guje wa kowane kalmomin sarrafawa, gami da harafin ESCAPE kanta, lokacin da suka bayyana azaman bayanai tsakanin alamomin START_WRITE da END_WRITE.

Duk wani byte na READ_REQ da ba a iya tserewa ba da aka aika zuwa FPGA umarni ne don aika duk rajistan shiga UART (shigarwa da fitarwa) zuwa mai masaukin baki akan UART. Wannan umarni yawanci ana bayar da shi ne kawai ta rubutun uart_regs.py.
Bayan karɓar wannan umarni, FPGA za ta amsa ta hanyar aika abubuwan da ke cikin duk rajista zuwa mai masaukin baki. Na farko, sigina na shigarwa, sannan siginar fitarwa. Idan tsayin su bai ƙara zuwa mahara na 8 ragowa ba, ƙananan raƙuman baiti na ƙarshe za su zama sifili.
Jeri rubuta koyaushe yana farawa da START_WRITE byte kuma yana ƙare da END_WRITE byte. Duk wani bytes tsakanin waɗancan ana ɗaukar su bayanan bytes ne. Idan kowane bytes na bayanai yana da ƙima ɗaya da halin sarrafawa, byte ɗin bayanan dole ne a tsere. Wannan yana nufin aika ƙarin harafin ESCAPE kafin bayanan byte don nuna cewa ainihin bayanai ne.
Idan START_WRITE wanda ba'a tsira ba ya isa ko'ina a cikin rafi na bytes, ana ɗaukarsa farkon jerin rubuce-rubuce. Tsarin uart_regs_backend yana amfani da wannan bayanin don sake daidaitawa idan sadarwar ta daina aiki tare.

gen_uart_regs.py

Wannan shine rubutun dole ne ku fara da shi don samar da hanyar sadarwa. A ƙasa akwai hoton allo na menu na taimako wanda zaku iya samu ta hanyar gudu: python gen_uart_regs.py -h
Don samar da keɓancewar al'ada, dole ne ku gudanar da rubutun tare da kowane rajistar ku na UART mai sarrafa abin da kuke so da aka jera azaman muhawara. Nau'o'in da ake da su sune std_logic, std_logic_vector, marasa sa hannu, da sanya hannu.
Yanayin tsoho (direction) yana ciki kuma nau'in tsoho shine std_logic_vector sai dai idan rajistan yana da tsayi: 1. Sa'an nan, zai tsoma baki zuwa std_logic.

Don haka, idan kuna son ƙirƙirar siginar shigarwar std_logic, zaku iya amfani da ɗayan waɗannan gardama:
my_sl=1
my_sl=1:in

my_sl=1: in:std_logic
Duk bambance-bambancen da ke sama za su haifar da rubutun da ke haifar da wannan siginar da za a iya samu ta UART:
Bari mu gudanar da rubutun tare da mahawara don samar da hanyar sadarwa tare da rajista da yawa na kwatance, tsayi, da iri daban-daban

An ƙirƙira files

Gudun nasara na rubutun gen_uart_regs.py zai samar da babban fayil mai suna wanda aka samar tare da uku files da aka jera a kasa. Idan sun riga sun kasance, za a sake rubuta su.
generated/uart_regs.vhd

generated/uart_regs.py
generated/instantiation_template.vho
uart_regs.vhd

Wannan shine tsarin mu'amala na al'ada wanda rubutun ya samar. Kuna buƙatar aiwatar da shi a cikin ƙirar ku, inda zai iya samun damar yin amfani da rajistar da kuke son sarrafawa ta amfani da UART.
Duk abin da ke sama da sashin "- UART masu samun damar yin rajista" zai kasance iri ɗaya ga kowane nau'in uart_regs, yayin da abun da ke cikin siginar tashar jiragen ruwa da ke ƙasan wannan layin ya dogara da muhawarar da aka bayar ga rubutun janareta.
Lissafin da ke ƙasa yana nuna mahaɗin don tsarin uart_regs wanda ya samo asali daga umarnin samar da exampwanda aka nuna a cikin sashin gen_uart_regs.py

Ba kwa buƙatar daidaita siginar uart_rx, kamar yadda ake sarrafa wannan a cikin uart_rx. module.
Lokacin da tsarin ya sami buƙatar karantawa, zai ɗauki ƙimar duk shigarwar da siginar fitarwa a cikin zagayowar agogo na yanzu. Ana aika hoton nan take zuwa mai masaukin baki akan UART.
Lokacin da rubutu ya faru, ana sabunta duk rijistar fitarwa tare da sabbin dabi'u a cikin zagayen agogo ɗaya. Ba zai yiwu a canza ƙimar siginar fitarwa daban-daban ba.

Koyaya, rubutun uart_regs.py yana bawa mai amfani damar sabunta abubuwan da aka zaɓa kawai ta hanyar karantawa da darajoji na yanzu na duk rijistar. Daga nan sai ta sake rubuta duk darajoji, gami da waɗanda aka sabunta.
uart_regs.py
An ƙirƙira/uart_regs.py file An ƙirƙira shi tare da uart_regs VHDL module kuma ya ƙunshi bayanan rajista na al'ada a cikin taken file. Tare da wannan rubutun, zaku iya karantawa ko rubuta zuwa rajistar ku na al'ada cikin sauƙi.

Menu na taimako

Buga python uart_regs.py -h don buga menu na taimako:

Saita tashar tashar UART

Rubutun yana da zaɓuɓɓuka don saita tashar tashar UART ta amfani da -c switch. Wannan yana aiki akan Windows da Linux. Saita shi zuwa ɗaya daga cikin samammun tashoshin jiragen ruwa da aka jera a cikin menu na taimako. Don saita tsohuwar tashar tashar jiragen ruwa, Hakanan zaka iya shirya canjin UART_PORT a cikin rubutun uart_regs.py.

Lissafin lissafin

Ana sanya bayanai game da taswirar rajista a cikin taken rubutun uart_regs.py ta rubutun gen_uart_regs.py. Kuna iya jera rijistar da ke akwai tare da canza -l, kamar yadda aka gani a ƙasa. Wannan umarni ne na gida kuma ba zai yi hulɗa tare da FPGA da aka yi niyya ba

Rubuce-rubuce zuwa masu rajista

Kuna iya rubutawa zuwa kowane rajistar yanayin waje ta amfani da -w switch. Bayar da sunan rajista wanda ke biye da "=" da ƙimar da aka bayar azaman binary, hexadecimal, ko ƙima na goma, kamar yadda aka nuna a ƙasa.
Lura cewa aiwatar da VHDL yana buƙatar rubutun don rubuta duk rajistar fitarwa lokaci guda. Don haka, idan ba ku ƙididdige cikakken saitin rajistar fitarwa ba, rubutun zai fara yin karatu daga FPGA da aka yi niyya sannan kuma amfani da waɗannan ƙimar ga waɗanda suka ɓace. Sakamakon zai zama ƙayyadaddun rajista kawai suna canzawa
Lokacin da kuka yi rubutu, duk ƙayyadaddun rajista za su canza yayin zagayowar agogo ɗaya, ba da zarar an karɓi su akan UART ba.

Karatun rajista

Yi amfani da canjin -r don karanta duk ƙimar rajista, kamar yadda aka nuna a ƙasa. Ƙimar da aka yiwa alama a rawaya sune waɗanda muka canza a cikin rubutun da ya gabata example
Kowane karantawa yana nuna hoto nan take na duk rajistar shigarwa da fitarwa. Dukkansu sampjagoranci yayin zagayowar agogo guda

Gyara kurakurai

Yi amfani da maɓalli na -d tare da kowane ɗayan maɓalli idan kuna buƙatar gyara ka'idar sadarwa. Sannan, rubutun zai buga duk abubuwan da aka aika da karɓa da kuma tag su idan sun kasance haruffa masu sarrafawa, kamar yadda aka nuna a kasa.

Amfani da dubawa a cikin wasu rubutun Python

Rubutun uart_regs.py ya ƙunshi nau'in UartRegs wanda zaka iya amfani dashi cikin sauƙi azaman hanyar sadarwa a cikin wasu rubutun Python na al'ada. Kawai shigo da ajin, ƙirƙirar wani abu, sannan fara amfani da hanyoyin, kamar yadda aka nuna a ƙasa.

Koma zuwa docstrings a cikin lambar Python don hanya da kwatance da kuma dawo da nau'ikan ƙima.

instantiation_template.vho

An ƙirƙiri samfuri ta atomatik tare da tsarin uart_regs don dacewa. Don adana lokacin yin coding, zaku iya kwafin saƙon saƙon nan take da sanarwar sigina cikin ƙirar ku.

RTL files

Kuna buƙatar haɗa waɗannan abubuwan files a cikin aikin VHDL ɗin ku don a haɗa su cikin ɗakin karatu ɗaya kamar tsarin uart_regs:
rtl/uart_regs_backend.vhd

rtl/uart_rx.vhd
rtl/uart_tx.vhd
Tsarin uart_regs_backend yana aiwatar da injunan jihohi masu iyaka waɗanda suke agogo da fitar da bayanan rajista. Yana amfani da kayan aikin uart_rx da uart_tx don sarrafa sadarwar UART tare da mai watsa shiri.

Ayyukan demo

Akwai ayyukan demo guda uku da aka haɗa a cikin Zip file. Suna ba ku damar sarrafa abubuwan da ke kewaye a kan alluna daban-daban da kuma ƴan mafi girma, rajista na ciki.
Fayilolin demo sun haɗa da riga-kafi uart_regs.vhd da uart_regs.py files sanya musamman ga waɗanda kayayyaki.

Lattice iCEstick

Babban fayil ɗin demo/icecube2_icestick yana ƙunshe da aiwatar da damar yin rijista don hukumar Lattice iCEstick FPGA.
Don gudanar da tsarin aiwatarwa, buɗe demo/lattice_icestick/icecube2_proj/uart_regs_sbt.project file a cikin Lattice iCEcube2 ƙira software.
Bayan loda aikin a cikin iCEcube2 GUI, danna Kayan aiki → Run Duk don samar da bitmap ɗin shirye-shirye file.

Kuna iya amfani da kayan aikin Lattice Diamond Programmer Standalone don saita FPGA tare da ingantaccen bitmap. file. Lokacin da Diamond Programmer ya buɗe, danna Buɗe shirin da ke akwai a cikin akwatin maganganu maraba.
Zaɓi aikin file samu a cikin Zip: demo/lattice_icestick/diamond_programmer_project.xcf kuma danna Ok.
Bayan aikin yayi lodi, danna dige guda uku a cikin File Kundin suna, kamar yadda aka nuna a sama. Nemo don zaɓar bitmap file wanda kuka ƙirƙira a cikin iCEcube2

demo/lattice_icestick/icecube2_proj/uart_regs_Implmnt/sbt/outputs/bitmap/top_icestick_bitmap.bin
A ƙarshe, tare da allon iCEstick a cikin tashar USB akan kwamfutarka, zaɓi Design→Program don tsara SPI flash kuma saita FPGA.
Yanzu zaku iya ci gaba da karantawa da rubuta rajista ta amfani da rubutun demo/lattice_icestick/uart_regs.py kamar yadda aka bayyana a sashin uart_regs.py.

Xilinx Digilent Arty A7-35T

Kuna iya nemo aiwatar da demo na Artix-7 35T Arty FPGA kit ɗin kimantawa a cikin babban fayil ɗin demo/arty_a7_35.
Bude Vivado kuma kewaya zuwa abin da aka fitar files ta amfani da na'urar wasan bidiyo na Tcl da aka samo a kasan haɗin GUI. Buga wannan umarni don shigar da babban fayil ɗin aikin demo:

cd /demo/arty_a7_35/vivado_proj/
Yi aikin ƙirƙirar_vivado_proj.tcl Tcl rubutun don sake haɓaka aikin Vivado:
tushen ./create_vivado_proj.tcl

Danna Ƙirƙirar Bitstream a cikin labarun gefe don gudanar da duk matakan aiwatarwa da samar da bitstream na shirye-shirye file.
A ƙarshe, danna Buɗe Manajan Hardware kuma shirya FPGA ta hanyar GUI.
Yanzu zaku iya ci gaba da karantawa da rubuta rajista ta amfani da rubutun demo/arty_a7_35/uart_regs.py kamar yadda aka bayyana a sashin uart_regs.py.

Xilinx Digilent Arty S7-50

Kuna iya nemo aiwatar da demo na Arty S7: Spartan-7 FPGA ci gaban hukumar a cikin babban fayil ɗin demo/arty_s7_50.
Bude Vivado kuma kewaya zuwa abin da aka fitar files ta amfani da na'urar wasan bidiyo na Tcl da aka samo a kasan haɗin GUI. Buga wannan umarni don shigar da babban fayil ɗin aikin demo:

cd /demo/arty_s7_50/vivado_proj/
Yi aikin ƙirƙirar_vivado_proj.tcl Tcl rubutun don sake haɓaka aikin Vivado:
tushen ./create_vivado_proj.tcl

Danna Ƙirƙirar Bitstream a cikin labarun gefe don gudanar da duk matakan aiwatarwa da samar da bitstream na shirye-shirye file.
A ƙarshe, danna Buɗe Manajan Hardware kuma shirya FPGA ta hanyar GUI.
Yanzu zaku iya ci gaba da karantawa da rubuta rajista ta amfani da rubutun demo/arty_s7_50/uart_regs.py kamar yadda aka bayyana a cikin sashin uart_regs.py.

Aiwatarwa

Babu takamaiman bukatun aiwatarwa.

Matsaloli

Babu takamaiman ƙayyadaddun ƙayyadaddun lokaci da ake buƙata don wannan ƙira saboda ƙirar UART tana jinkirin kuma ana kula da ita azaman ƙirar asynchronous.

An daidaita shigar da uart_rx zuwa tsarin uart_regs a cikin tsarin uart_rx. Don haka, baya buƙatar aiki tare a cikin babban matakin matakin.

Abubuwan da aka sani

Kuna iya buƙatar sake saita tsarin kafin a iya amfani da shi, dangane da ko gine-ginen FPGA ɗinku yana goyan bayan ƙimar rijistar tsoho.

Karin bayani

Haƙƙin mallaka VHDLwhiz.com

FAQs

Q: Mene ne manufar UART gwajin dubawa janareta?

A: Babban janareta na gwajin gwaji na UART yana ba da damar ƙirƙirar musaya na al'ada don yin hulɗa tare da ƙimar rijistar FPGA ta amfani da sadarwar UART.

Tambaya: Ta yaya zan shigar da kunshin Pyserial?

A: Kuna iya shigar da Pyserial ta hanyar Pip ta amfani da umarnin: pip install pyserial

Takardu / Albarkatu

VHDLwhiz UART Test Interface Generator [pdf] Manual mai amfani
UART Test Interface Generator, Gwaji Interface Generator, Interface Generator, Generator

Magana

Manual mai amfani

VHDLwhiz UART Test Interface Generator

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