VHDLwhiz UART Test Interface Generator User Manual

Izi zimakupatsani mwayi wopanga mawonekedwe owerengera ndi kulemba ma regista a FPGA pogwiritsa ntchito UART. Module yopangidwa ndi VHDL ndi Python script imapereka mwayi wolumikizana ndi mitundu yosiyanasiyana yolembetsa pamapangidwe anu a FPGA.

Zofunikira

Wotanthauzira Python 3
pyserial phukusi

Ndondomeko

Chogulitsacho chimagwiritsa ntchito protocol yopangira data yokhala ndi zilembo zinayi zowongolera:

Dzina: WERENGANI_REQ, Mtengo: 0x0A - Lamulani kuchokera kwa omwe akukhala nawo kupita ku FPGA kuti ayambe kulemba mndandanda kuti atumize zolembetsa zonse ku UART
Dzina: START_LEMBANI, Mtengo: 0x0B - Imawonetsa chiyambi cha kulemba motsatira mbali zonse

Dzina: END_LEMBA, Mtengo: 0x0C - Imawonetsa kumapeto kwa kalembedwe kalembedwe mbali zonse
Dzina: THAWANI, Mtengo: 0x0D - Makhalidwe othawa omwe amagwiritsidwa ntchito pothawa mawu owongolera

Malangizo Ogwiritsira Ntchito Zogulitsa

Kuyendetsa Scripts

Kuti mugwiritse ntchito malonda, onetsetsani kuti mwayika Python 3 ndi phukusi la Pyserial. Yendetsani zolembedwa kudzera pa womasulira wa Python 3.

Kupanga Custom Interfaces

Gwiritsani ntchito gen_uart_regs.py script kuti mupange malo ochezera amomwe mungawerenge ndi kulemba ma regista a FPGA. Mutha kutchulanso zolembera zolowera ndi zotulutsa ndi mitundu popanga zotulutsa files.

Kulumikizana ndi Registers

Mutha kuwerenga kuchokera kapena kulembera ku zolembetsa zingapo pamapangidwe anu a FPGA pogwiritsa ntchito gawo la VHDL lopangidwa ndi Python script. Ma regista opezeka amatha kukhala ndi mitundu monga std_logic, std_logic_vector, osayinidwa, kapena osasainidwa.

Chilolezo

Layisensi ya MIT imakhudza zofunikira za kukopera kwa gwero ndi momwe mungagwiritsire ntchito. Onani ku LICENSE.txt file mu zip file zatsatanetsatane.

Changelog

Zosinthazi zikulozera ku polojekiti files, ndipo chikalatachi chikusinthidwa moyenera

Baibulo	Ndemanga
1.0.0	Kutulutsidwa koyamba
1.0.1	Kukonzekera kusowa kwa "self" bug pamene mukulowetsa monga uart_regs.py monga gawo la Python. Zolemba zosinthidwa zalephera kusindikizidwa kukhala kusiyapo pewani kusindikiza ku kontrakitala mukamagwira ntchito ngati gawo lotumizidwa kunja.
1.0.2	Konzani zolakwika za Vivado [Synth 8-248] pomwe palibe regs zakunja.
1.0.3	Konzani chenjezo la Vivado Linter: Kulembetsa kwathandizira kuyendetsedwa ndi sinthaninso synchronous
1.0.4	Konzani ngodya pamene mukulandira mawu olakwika ndi zilembo zothawa ngati byte yomaliza. Mawu otsatirawa atayikanso chifukwa sitinachotse recv_data_prev_is_escape pobwerera ku IDLE. Zolemba za gen_uart_regs.py tsopano zimalola mayina apadera okha.

Kufotokozera

Chikalatachi chikufotokoza zotsatirazi files ndi zikwatu:
gen_uart_regs.py

generated/uart_regs.vhd
generated/uart_regs.py
generated/instantiation_template.vho
rtl/uart_regs_backend.vhd
rtl/uart_rx.vhd
rtl/uart_tx.vhd
chiwonetsero/lattice_icestick/
chiwonetsero/xilinx_arty_a7_35/
chiwonetsero/xilinx_arty_s7_50/
Zolemba za gen_uart_regs.py ndikuthandizira VHDL files mu pulojekitiyi amakulolani kuti mupange malo ochezera a powerenga ndi kulemba FPGA zolembera zamitundu yosiyanasiyana ndi m'lifupi pogwiritsa ntchito UART.
Mutha kugwiritsa ntchito gawo lopangidwa la VHDL ndi Python script kuti muwerenge kapena kulembera nambala iliyonse yamarejista pamapangidwe anu. Ma regista opezeka a UART amatha kukhala ndi mitundu std_logic, std_logic_vector, yosainidwa, kapena yosasainidwa.
Mutha kusankha pazolemba zenizeni zolembera ndi zotulutsa ndi mitundu mukamapanga zotulutsa filepogwiritsa ntchito gen_uart_regs.py script.
Zolemba za Python zidapangidwa pang'ono mothandizidwa ndi chida chanzeru chaukadaulo cha ChatGPT, pomwe code ya VHDL idapangidwa ndi manja.

Zofunikira

Zolemba za polojekitiyi ziyenera kuyendetsedwa kudzera mwa womasulira wa Python 3 ndipo phukusi la Pyserial liyenera kukhazikitsidwa.
Mutha kukhazikitsa pyserial kudzera pa Pip pogwiritsa ntchito lamulo ili: pip install pyserial

Ndondomeko

Chithunzi cha VHDL files ndi Python script amagwiritsa ntchito protocol yopangira data yokhala ndi zowongolera zinayi

Dzina	Mtengo	Ndemanga
WERENGANI_REQ	0x0A	Lamulani kuchokera kwa wolandirayo kupita ku FPGA kuti muyambe kulemba tumizani zolembetsa zonse pa UART
START_LEMBANI	0x0B	Imawonetsa chiyambi cha kalembedwe mu iliyonse malangizo
END_LEMBA	Zamgululi	Imayika kumapeto kwa kalembedwe kotsatira mbali zonse
KUTHAWUKA	0x0d pa	Escape zilembo zomwe zimagwiritsidwa ntchito pothawa mawu aliwonse owongolera, kuphatikiza zilembo za ESCAPE, zikawoneka ngati data pakati pa zolembera za START_WRITE ndi END_WRITE.

BYTE iliyonse yosapeŵeka ya READ_REQ yotumizidwa ku FPGA ndi malangizo oti atumize zolembera zake zonse zopezeka ndi UART (zolowetsa ndi zotuluka) kwa wolandila kudzera pa UART. Lamuloli nthawi zambiri limaperekedwa ndi uart_regs.py script.
Mukalandira lamulo ili, FPGA iyankha potumiza zomwe zili m'marejista onse kwa wolandirayo. Choyamba, zizindikiro zolowera, ndiye zotulukapo. Ngati kutalika kwawo sikungaphatikizepo kuchulukitsa kwa ma bits 8, tinthu tating'ono ta mabati omaliza tidzakhala ziro.
Kulemba kumayamba ndi START_WRITE byte ndipo kumatha ndi END_WRITE byte. Ma byte aliwonse pakati pawo amatengedwa ngati ma data byte. Ngati ma data byte ali ndi mtengo wofanana ndi wowongolera, data byte iyenera kuthawa. Izi zikutanthauza kutumiza munthu wowonjezera wa ESCAPE pamaso pa data byte kuti awonetse kuti ndi data.
Ngati START_WRITE yomwe sinapulumuke ikafika paliponse pamtundu wa ma byte, imatengedwa ngati chiyambi cha kalembera. Gawo la uart_regs_backend limagwiritsa ntchito chidziwitsochi kuti chilumikizenso ngati kulumikizana kwasiya kulumikizana.

gen_uart_regs.py

Ili ndiye script yomwe muyenera kuyamba nayo kuti mupange mawonekedwe. Pansipa pali chithunzi chazithunzi zothandizira zomwe mungapeze pothamanga: python gen_uart_regs.py -h
Kuti mupange mawonekedwe achikhalidwe, muyenera kuyendetsa script ndi kaundula wanu uliwonse wa UART womwe mukufuna wotchulidwa ngati mikangano. Mitundu yomwe ilipo ndi std_logic, std_logic_vector, osasainidwa, ndi kusaina.
Njira yokhazikika (njira) ili mkati ndipo mtundu wokhazikika ndi std_logic_vector pokhapokha kaundula ndi kutalika: 1. Kenako, idzasintha kukhala std_logic.

Chifukwa chake, ngati mukufuna kupanga std_logic yolowetsa chizindikiro, mutha kugwiritsa ntchito iliyonse mwa mfundo izi:
wanga_sl=1
wanga_sl=1:mu

my_sl=1:mu:std_logic
Mitundu yonse yomwe ili pamwambapa ipangitsa kuti script ipange chizindikiro chofikira cha UART:
Tiyeni tiyendetse zolembazo ndi mfundo kuti tipeze mawonekedwe okhala ndi zolembetsa zingapo zamayendedwe, utali, ndi mitundu

Zapangidwa files

Kuthamanga bwino kwa gen_uart_regs.py script kutulutsa chikwatu chomwe chimatchedwa kuti chopangidwa ndi atatuwa. filezalembedwa pansipa. Ngati zilipo kale, zidzasinthidwa.
generated/uart_regs.vhd

generated/uart_regs.py
generated/instantiation_template.vho
uart_regs.vhd

Iyi ndiye gawo lachidziwitso chopangidwa ndi script. Muyenera kuyiyika pamapangidwe anu, komwe imatha kupeza zolembera zomwe mukufuna kuziwongolera pogwiritsa ntchito UART.
Chilichonse chomwe chili pamwamba pa gawo la "- UART lofikira" lidzakhala lofanana ndi gawo lililonse la uart_regs, pomwe mawonekedwe azizindikiro zamadoko pansi pa mzerewu zimadalira mikangano yoperekedwa ku script ya jenereta.
Mndandanda womwe uli pansipa ukuwonetsa gulu la uart_regs module lochokera ku kupanga command example kuwonetsedwa mu gawo la gen_uart_regs.py

Simufunikanso kulunzanitsa uart_rx siginecha, monga izo zimagwiridwa mu uart_rx. moduli.
Module ikalandira pempho lowerengedwa, imajambula zidziwitso zonse zolowera ndi zotuluka mkati mwa wotchi yomwe ilipo. Chithunzicho chimatumizidwa kwa wolandirayo kudzera pa UART.
Zolemba zikachitika, zolembera zonse zotuluka zimasinthidwa ndi zikhalidwe zatsopano mkati mwa wotchi yomweyo. Sizingatheke kusintha ma siginecha otuluka payekhapayekha.

Komabe, uart_regs.py script imalola wogwiritsa ntchito kusintha zomwe asankha powerenga kaye zomwe zili m'marejista onse. Kenako imalembanso zikhalidwe zonse, kuphatikiza zomwe zasinthidwa.
uart_regs.py
The generated/uart_regs.py file imapangidwa pamodzi ndi gawo la uart_regs VHDL ndipo ili ndi zidziwitso zolembetsa zomwe zili pamutu wa file. Ndi script iyi, mutha kuwerenga kapena kulembera ku zolembera zanu mosavuta.

Menyu yothandizira

Lembani python uart_regs.py -h kusindikiza mndandanda wothandizira:

Kukhazikitsa doko la UART

Cholembacho chili ndi zosankha zoyika doko la UART pogwiritsa ntchito -c switch. Izi zimagwira ntchito pa Windows ndi Linux. Ikhazikitseni ku amodzi mwa madoko omwe alipo omwe alembedwa mumenyu yothandizira. Kuti mukhazikitse doko lokhazikika, mutha kusinthanso mawonekedwe a UART_PORT mu uart_regs.py script.

Ma register olembetsa

Zambiri za mamapu olembetsa zayikidwa pamutu wa uart_regs.py script ndi gen_uart_regs.py script. Mutha kulembetsa zolembetsa zomwe zilipo ndi -l switch, monga tawonera pansipa. Ili ndi lamulo la komweko ndipo silingagwirizane ndi FPGA yomwe mukufuna

Kulembera ku zolembera

Mutha kulembera ku zolembera zilizonse zakunja pogwiritsa ntchito -w switch. Perekani dzina lolembetsa lotsatiridwa ndi "=" ndi mtengo woperekedwa ngati binary, hexadecimal, kapena mtengo wa decimal, monga momwe zilili pansipa.
Dziwani kuti kukhazikitsidwa kwa VHDL kumafuna kuti script ilembe zolembera zonse nthawi imodzi. Chifukwa chake, ngati simunatchule mndandanda wathunthu wazolembetsa, script imayamba kuwerenga kuchokera pa FPGA yomwe mukufuna ndikugwiritseni ntchito zomwe zikusowa. Zotsatira zake zikhala kuti zolembetsa zotchulidwa zokha zimasintha
Mukalemba, zolembetsa zonse zomwe zafotokozedwa zimasintha nthawi yomweyo, osati akangolandiridwa pa UART.

Kuwerenga kaundula

Gwiritsani ntchito -r switch kuti muwerenge ziwerengero zonse zolembetsa, monga zikuwonetsedwa pansipa. Makhalidwe olembedwa achikasu ndi omwe tidawasintha m'mbuyomu yolemba kaleample
Kuwerenga kulikonse kumawonetsa chithunzithunzi chanthawi yomweyo ya zolembera zonse zolowetsa ndi zotuluka. Iwo onse ndi sampkutsogozedwa panthawi yomweyi

Kuthetsa vuto

Gwiritsani ntchito -d switch ndi masiwichi ena aliwonse ngati mukufuna kukonza njira yolumikizirana. Kenako, script idzasindikiza mabayiti onse otumizidwa ndi kulandilidwa ndi tag ngati ali olamulira, monga momwe zilili pansipa.

Kugwiritsa ntchito mawonekedwe muzolemba zina za Python

Zolemba za uart_regs.py zili ndi gulu la UartRegs lomwe mungagwiritse ntchito mosavuta ngati njira yolumikizirana muzolemba zina za Python. Ingolowetsani kalasi, pangani chinthu chake, ndikuyamba kugwiritsa ntchito njira, monga momwe zilili pansipa.

Onani ma docstrings mu code ya Python kuti mupeze njira ndi mafotokozedwe ndi mitundu yobwezera.

instantiation_template.vho

Template instantiation imapangidwa limodzi ndi uart_regs module kuti muthandizire. Kuti musunge nthawi yokhotakhota, mutha kutengera mawonekedwe a module ndi zidziwitso zamasigini pamapangidwe anu.

Kukhazikika kwa RTL files

Muyenera kuphatikiza zotsatirazi files mu projekiti yanu ya VHDL kuti asonkhanitsidwe mulaibulale yomweyo monga gawo la uart_regs:
rtl/uart_regs_backend.vhd

rtl/uart_rx.vhd
rtl/uart_tx.vhd
Uart_regs_backend module imagwiritsa ntchito makina amtundu wa finite-state omwe amalowetsa ndi kutulutsa deta. Imagwiritsa ntchito ma module a uart_rx ndi uart_tx kuti azitha kulumikizana ndi UART ndi wolandirayo.

Ntchito zowonetsera

Pali ma projekiti atatu ophatikizidwa mu Zip file. Amakulolani kuti muwongolere zotumphukira pama board osiyanasiyana komanso ma regista akuluakulu angapo amkati.
Mafoda owonetsera akuphatikiza uart_regs.vhd wopangidwa kale ndi uart_regs.py files anapangidwira mwachindunji mapangidwe amenewo.

Lattice iCEstick

Foda yachiwonetsero/icecube2_icestick ili ndi kaundula wofikira pakukhazikitsa kwa board ya Lattice iCEstick FPGA.
Kuti mugwiritse ntchito, tsegulani demo/lattice_icestick/icecube2_proj/uart_regs_sbt.project file mu Lattice iCEcube2 design software.
Mukatsitsa pulojekitiyi mu iCEcube2 GUI, dinani Zida → Thamanga Zonse kuti mupange pulogalamu ya bitmap. file.

Mutha kugwiritsa ntchito chida cha Lattice Diamond Programmer Standalone kukonza FPGA ndi bitmap yopangidwa. file. Pamene Diamond Programmer atsegula, dinani Tsegulani pulojekiti yomwe ilipo kale mu bokosi lolandirira.
Sankhani polojekiti file zopezeka mu Zip: demo/lattice_icestick/diamond_programmer_project.xcf ndikudina Chabwino.
Pambuyo pomaliza ntchitoyo, dinani madontho atatu mu bokosilo File Mzere wa dzina, monga momwe tawonetsera pamwambapa. Sakatulani kuti musankhe bitmap file zomwe mudapanga mu iCEcube2

demo/lattice_icestick/icecube2_proj/uart_regs_Implmnt/sbt/outputs/bitmap/top_icestick_bitmap.bin
Pomaliza, ndi bolodi ya iCEstick yolumikizidwa padoko la USB pakompyuta yanu, sankhani Design→Pulogalamu yokonza kung'anima kwa SPI ndikusintha FPGA.
Tsopano mutha kupitiliza kuwerenga ndi kulemba zolembetsa pogwiritsa ntchito demo/lattice_icestick/uart_regs.py script monga tafotokozera mu gawo la uart_regs.py.

Xilinx Digilent Arty A7-35T

Mutha kupeza kukhazikitsidwa kwachiwonetsero kwa zida zowunikira za Artix-7 35T Arty FPGA mufoda ya demo/arty_a7_35.
Tsegulani Vivado ndikuyenda kupita ku zochotsedwa files pogwiritsa ntchito Tcl console yomwe imapezeka pansi pa mawonekedwe a GUI. Lembani lamulo ili kuti mulowe chikwatu cha polojekiti:

cd /demo/arty_a7_35/vivado_proj/
Pangani script ya create_vivado_proj.tcl Tcl kuti mukonzenso pulojekiti ya Vivado:
gwero ./create_vivado_proj.tcl

Dinani Pangani Bitstream mumzere wam'mbali kuti muyendetse masitepe onse ndikuyambitsa pulogalamuyo file.
Pomaliza, dinani Open Hardware Manager ndikukonzekera FPGA kudzera pa GUI.
Tsopano mutha kupitiliza kuwerenga ndi kulemba zolembetsa pogwiritsa ntchito demo/arty_a7_35/uart_regs.py script monga tafotokozera mu gawo la uart_regs.py.

Xilinx Digilent Arty S7-50

Mutha kupeza kukhazikitsidwa kwachiwonetsero kwa Arty S7: Spartan-7 FPGA board board mu demo/arty_s7_50 foda.
Tsegulani Vivado ndikuyenda kupita ku zochotsedwa files pogwiritsa ntchito Tcl console yomwe imapezeka pansi pa mawonekedwe a GUI. Lembani lamulo ili kuti mulowe chikwatu cha polojekiti:

cd /demo/arty_s7_50/vivado_proj/
Pangani script ya create_vivado_proj.tcl Tcl kuti mukonzenso pulojekiti ya Vivado:
gwero ./create_vivado_proj.tcl

Dinani Pangani Bitstream mumzere wam'mbali kuti muyendetse masitepe onse ndikuyambitsa pulogalamuyo file.
Pomaliza, dinani Open Hardware Manager ndikukonzekera FPGA kudzera pa GUI.
Tsopano mutha kupitiliza kuwerenga ndi kulemba zolembetsa pogwiritsa ntchito demo/arty_s7_50/uart_regs.py script monga tafotokozera mu gawo la uart_regs.py.

Kukhazikitsa

Palibe zofunikira zenizeni zokhazikitsidwa.

Zopinga

Palibe zoletsa zanthawi yeniyeni zomwe zimafunikira pamapangidwe awa chifukwa mawonekedwe a UART ndiwapang'onopang'ono ndipo amawonedwa ngati mawonekedwe asynchronous.

Kulowetsa kwa uart_rx ku gawo la uart_regs kumalumikizidwa mkati mwa gawo la uart_rx. Chifukwa chake, sizifunika kulumikizidwa mugawo lapamwamba.

Nkhani zodziwika

Mungafunike kukonzanso gawoli lisanagwiritsidwe ntchito, kutengera ngati kapangidwe kanu ka FPGA kamathandizira zikhalidwe zolembetsa.

Zambiri

Ufulu VHDLwhiz.com

FAQs

Q: Kodi cholinga cha jenereta ya mawonekedwe a UART ndi chiyani?

A: UART test interface jenereta imalola kuti pakhale mawonekedwe olumikizirana makonda kuti azilumikizana ndi FPGA zolembera zolembera pogwiritsa ntchito kulumikizana kwa UART.

Q: Kodi ndimayika bwanji phukusi la Pyserial?

A: Mutha kukhazikitsa Pyserial kudzera pa Pip pogwiritsa ntchito lamulo: pip install pyserial

Zolemba / Zothandizira

VHDLwhiz UART Test Interface Generator [pdf] Buku Logwiritsa Ntchito
UART Test Interface Generator, Test Interface Generator, Interface Generator, Generator

Maumboni

Buku Logwiritsa Ntchito

VHDLwhiz UART Test Interface Generator

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