VHDLwhiz UART Test Interface Jenareta Yekushandisa Manual

Ichi chigadzirwa chinokutendera kuti ugadzire yakasarudzika nzvimbo yekuverenga nekunyora FPGA rejista makoshero uchishandisa UART. Iyo yakagadzirwa VHDL module uye Python script inopa kugona kupindirana nemhando dzakasiyana dzemarejista mune yako FPGA dhizaini.

Zvinodiwa

Python 3 muturikiri
pyserial package

Protocol

Chigadzirwa chacho chinoshandisa data framing protocol ine mana ekudzora mavara:

Zita: VERENGA_REQ, Kukosha: 0x0A - Raira kubva kumuenzi kuenda kuFPGA kuti utange kunyora kutevedzana kutumira marejista ese kumashure pamusoro peUART.
Zita: START_NYORA, Kukosha: 0x0B - Inoratidza kutanga kwekutevedzana kwekunyora mune chero nzira

Zita: END_NYORA, Kukosha: 0x0C - Inoratidza kupera kwekutevedzana kwekunyora mune chero nzira
Zita: TIZIYA, Kukosha: 0x0D -Kutiza hunhu hunoshandiswa kutiza mazwi ekudzora

Mirayiridzo Yekushandiswa Kwechigadzirwa

Kumhanyisa Scripts

Kuti ushandise chigadzirwa, ita shuwa kuti une Python 3 yakaiswa uye Pyserial package. Mhanya zvinyorwa kuburikidza nePython 3 muturikiri.

Kugadzira Custom Interfaces

Shandisa gen_uart_regs.py script kugadzira tsika dzekutarisa kuverenga nekunyora FPGA rejista makoshero. Iwe unogona kutsanangura kuumbwa kwezvinyorwa zvekupinza uye zvinobuda uye mhando kana uchigadzira zvinobuda files.

Kudyidzana neRegister

Iwe unogona kuverenga kubva kana kunyora kune chero nhamba yemarejista mune yako FPGA dhizaini uchishandisa yakagadzirwa VHDL module uye Python script. Marejista anosvikika anogona kuve nemhando dzakadai std_logic, std_logic_vector, yakasainwa, kana isina kusaina.

License

Iyo MIT rezenisi inovhara iyo kodhi kodhi yekodzero zvinodiwa uye mazwi ekushandisa. Tarisa kuLICENSE.txt file muZip file kuti uwane ruzivo.

Changelog

Shanduko idzi dzinoreva purojekiti files, uye gwaro iri rinogadziridzwa saizvozvo

Version	Mashoko
1.0.0	Kusunungurwa kwekutanga
1.0.1	Yakagadziriswa yakashaikwa "yega" referensi bug paunenge uchiunza seuart_regs.py sePython module. Kusandurwa kunyora kwakatadza kudhindwa kuita kunze kwe dzivisa kudhinda kune koni paunenge uchimhanya semodule inotorwa kunze kwenyika.
1.0.2	Gadzirisa Vivado [Synth 8-248] kukanganisa kana pasina kunze kwemodhi regs.
1.0.3	Gadzirisa Vivado Linter yambiro: Rejista yakagonesa inofambiswa ne synchronous reset
1.0.4	Gadzirisa kesi yekona kana uchigamuchira izwi risina kurongeka rine hunhu hwekutiza sebhaiti yekupedzisira. Izwi rinotevera raizorasikawo nekuti hatina kubvisa recv_data_prev_is_escape pataidzokera kuIDLE. Iyo gen_uart_regs.py script ikozvino inobvumira akasarudzika mazita ereg.

Tsanangudzo

Gwaro iri rinotsanangura zvinotevera files uye mapepa:
gen_uart_regs.py

generated/uart_regs.vhd
generated/uart_regs.py
generated/instantiation_template.vho
rtl/uart_regs_backend.vhd
rtl/uart_rx.vhd
rtl/uart_tx.vhd
demo/lattice_icestick/
demo/xilinx_arty_a7_35/
demo/xilinx_arty_s7_50/
Iyo gen_uart_regs.py script uye inotsigira VHDL files mupurojekiti ino inobvumidza iwe kuti ugadzire yakasarudzika nzvimbo yekuverenga nekunyora FPGA rejista maitiro emhando dzakasiyana uye upamhi uchishandisa UART.
Unogona kushandisa iyo yakagadzirwa VHDL module uye Python script kuverenga kubva kana kunyora kune chero nhamba yemarejista mudhizaini yako. Marejista anosvikika eUART anogona kuve nemhando std_logic, std_logic_vector, yakasainwa, kana kusaina.
Iwe unogona kusarudza pamusoro peiyo chaiyo kuumbwa kwekuisa uye kubuda marejista uye marudzi paunenge uchigadzira zvinobuda filendiri kushandisa gen_uart_regs.py script.
Manyoro ePython akagadzirwa zvishoma nerubatsiro rweChatGPT yekugadzira njere chishandiso, nepo VHDL kodhi ichigadzirwa nemaoko.

Zvinodiwa

Zvinyorwa mupurojekiti iyi zvinofanirwa kuitwa kuburikidza nemuturikiri wePython 3 uye Pyserial package inofanira kuiswa.
Unogona kuisa pyserial kuburikidza nePip uchishandisa uyu murairo: pip isa pyserial

Protocol

Iye VHDL files uye Python script shandisa data-framing protocol ine mana control

Zita	Value	Comment
VERENGA_REQ	0x0A	Raira kubva kumugamuchiri kuenda kuFPGA kuti utange kunyora kutevedzana kwekutumira marejista ese kumashure pamusoro peUART
START_NYORA	0x0B	Inotangisa mutsara wekunyora mune chero direction
END_NYORA	0x0C	Inomaka panoperera mutsara wekunyora mune chero nzira
TIZUKA	0x0D	Escape character inoshandiswa kutiza chero mazwi ekudzora, kusanganisira iwo ESCAPE mavara pachawo, paanoonekwa sedata pakati pe START_WRITE neEND_WRITE mamaka.

Chero isina kupukunyuka READ_REQ byte inotumirwa kuFPGA murairo wekutumira marejista ayo eUART-anowanikwa (mapipu nezvabuda) kudzokera kumuenzi pamusoro peUART. Uyu murairo unowanzo kupihwa chete neuart_regs.py script.
Pakugamuchira uyu murairo, iyo FPGA inopindura nekutumira zviri mukati meese marejista kumashure kumuenzi. Kutanga, masaini ekuisa, ipapo masaini anobuda. Kana kureba kwadzo dzikasawedzera kuwanda kwe8 bits, mabheti epasi ekupedzisira byte anozove akatungirwa zero.
Kutevedzana kwekunyora kunotangira neSTART_WRITE byte uye kunopera ne END_WRITE byte. Chero mabheti pakati peaya anoonekwa se data bytes. Kana chero data byte ine kukosha kwakafanana seye control character, data byte inofanira kupukunyuka. Izvi zvinoreva kutumira imwe ESCAPE hunhu pamberi pe data byte kuratidza kuti ichokwadi data.
Kana isina kupukunyuka START_WRITE ikasvika chero munzvimbo yemabhayiti, inotorwa sekutanga kwekunyora kutevedzana. Iyo uart_regs_backend module inoshandisa iyi ruzivo kuwiriranisa kana kutaurirana kwabuda mukuwirirana.

gen_uart_regs.py

Ichi ndicho chinyorwa chaunofanira kutanga nacho kuti ugadzire iyo interface. Pazasi pane skrini yemenu yekubatsira yaunogona kuwana nekumhanya: python gen_uart_regs.py -h
Kuti ugadzire chimiro chetsika, unofanirwa kumhanyisa script nechero yako yaunoda UART inodzoreka marejista akanyorwa senharo. Mhando dziripo std_logic, std_logic_vector, isina kusaina, uye yakasainwa.
The default mode (direction) iri mukati uye iyo default type ndeye std_logic_vector kunze kwekunge rejista iri yehurefu: 1. Zvadaro, ichaita default ku std_logic.

Saka, kana iwe uchida kugadzira std_logic yekuisa chiratidzo, unogona kushandisa chero yeiyi nharo:
yangu_sl=1
my_sl=1:mu

my_sl=1:mu:std_logic
Zvese zviri pamusoro zvakasiyana zvinokonzeresa kuti script igadzire iyi UART-inogoneka chiratidzo:
Ngatimhanyei script nenharo kuti ibudise interface ine akati wandei marejista enzira dzakasiyana, kureba, nemhando.

Yakagadzirwa files

Kumhanya kwakabudirira kwegen_uart_regs.py script kuchaburitsa dhairekitori rakadanwa rakagadzirwa nevatatu. files dzakanyorwa pazasi. Kana dzatovepo, dzinozonyorwa.
generated/uart_regs.vhd

generated/uart_regs.py
generated/instantiation_template.vho
uart_regs.vhd

Iyi ndiyo tsika yekubatanidza module inogadzirwa ne script. Iwe unofanirwa kuisimbisa mune yako dhizaini, kwainokwanisa kuwana marejista aunoda kudzora uchishandisa UART.
Zvese zviri pamusoro pe "- UART inowanikwa marejista" chikamu chichafanana kune yega yega uart_regs module, nepo kuumbwa kwemasaini echiteshi pazasi iwo mutsara zvinoenderana nenharo dzakapihwa kune jenareta script.
Rondedzero iri pazasi inoratidza mubatanidzwa weiyo uart_regs module inokonzeresa kubva kukugadzira command exampinoratidzwa mugen_uart_regs.py secti

Iwe haufanire kuwiriranisa iyo uart_rx chiratidzo, sezvakabatwa muuart_rx. module.
Kana iyo module ikagamuchira chikumbiro chekuverenga, inobata kukosha kwese kupinza uye kubuda masaini mukati meazvino wachi kutenderera. Iyo pakarepo snapshot inotumirwa kumugadziri pamusoro peUART.
Kana kunyora kukaitika, zvese zvinobuda marejista zvinogadziridzwa nehunhu hutsva mukati menguva imwechete yewachi. Hazvibviri kushandura maratidziro echiratidzo chekubuda mumwe nemumwe.

Nekudaro, iyo uart_regs.py script inobvumira mushandisi kugadzirisa chete zvakasarudzwa zvakabuda nekutanga kuverenga kumashure maitiro azvino emarejista ese. Inobva yanyora kumashure ese kukosha, kusanganisira iwo akagadziridzwa.
uart_regs.py
Iyo yakagadzirwa/uart_regs.py file inogadzirwa pamwe chete neiyo uart_regs VHDL module uye ine iyo tsika rejista ruzivo mumusoro weiyo file. Nechinyorwa ichi, unogona kuverenga kubva kana kunyora kune yako tsika marejista zviri nyore.

Rubatsiro menyu

Nyora python uart_regs.py -h kudhinda menyu yekubatsira:

Kuisa iyo UART port

Iyo script ine sarudzo dzekuseta UART chiteshi uchishandisa -c switch. Izvi zvinoshanda paWindows neLinux. Isa kune imwe yeanowanikwa madoko akanyorwa mune yekubatsira menyu. Kuseta chiteshi chepombi, unogona zvakare kugadzirisa iyo UART_PORT musiyano muuart_regs.py script.

Kunyora mazita

Ruzivo nezve regista mepu inoiswa mumusoro weiyo uart_regs.py script negen_uart_regs.py script. Iwe unogona kunyora marejista aripo ne -l switch, sezvinoonekwa pazasi. Uyu murairo wepanzvimbo uye hauzodyidzana nechinangwa cheFPGA

Kunyorera kumarejista

Iwe unogona kunyora kune chero ekunze marejista uchishandisa iyo -w switch. Ipa zita rerejista rinoteverwa ne "=" uye kukosha kwakapihwa sebhanari, hexadecimal, kana kukosha kwedesimali, sezvaratidzwa pazasi.
Ziva kuti kuita kweVHDL kunoda kuti script inyore marejista ese anobuda panguva imwe chete. Naizvozvo, kana ukasatsanangura seti yakazara yemarejista ezvinobuda, script inotanga kuverenga kubva pane yakananga FPGA uye wozoshandisa iwo maitiro kune ayo asipo. Mhedzisiro ichave yekuti chete marejista akatsanangurwa anochinja
Paunonyora, ese marejista akatsanangurwa anochinja panguva imwechete yewachi, kwete kana angogamuchirwa pamusoro peUART.

Kuverenga mabhuku

Shandisa iyo -r switch kuti uverenge ese marejitari maitiro, sezvakaratidzwa pazasi. Hunhu hwakanyorwa neruvara rweyero ndihwo hwatakachinja mune yakapfuura nyora example
Kuverenga kwega kwega kunoratidza mufananidzo wepakarepo wezvese zvekupinza uye zvinobuda. Vose vari sampinotungamirirwa panguva imwe chete yewachi

Debugging

Shandisa iyo -d switch neimwe yedzimwe switch kana iwe uchida kugadzirisa iyo yekutaurirana protocol. Zvadaro, iyo script ichadhinda zvese zvakatumirwa uye zvakagamuchirwa bytes uye tag kana ari mavara ekudzora, sezvaratidzwa pazasi.

Kushandisa iyo interface mune mamwe maPython zvinyorwa

Iyo uart_regs.py script ine UartRegs kirasi yaunogona kushandisa zviri nyore seyekutaurirana interface mune mamwe etsika Python zvinyorwa. Ingo pinza kirasi, gadzira chinhu chayo, uye tanga kushandisa nzira, sezvaratidzwa pazasi.

Tarisa kune docstrings muPython kodhi yenzira uye tsananguro uye kudzoka kukosha mhando.

instantiation_template.vho

Iyo instantiation template inogadzirwa pamwe neiyo uart_regs module kuitira nyore kwako. Kuti uchengetedze nguva yekukodha, unogona kukopa iyo module instantiation uye zviziviso zvechiratidzo mudhizaini yako.

Static RTL files

Unofanira kusanganisira zvinotevera files mune yako VHDL purojekiti kuitira kuti iunganidzwe muraibhurari imwechete seiyo uart_regs module:
rtl/uart_regs_backend.vhd

rtl/uart_rx.vhd
rtl/uart_tx.vhd
Iyo uart_regs_backend module inoshandisa finite-state michina inovharira mukati uye kunze kwerejista data. Inoshandisa iyo uart_rx uye uart_tx module kubata iyo UART kutaurirana nemugamuchiri.

Demo mapurojekiti

Kune matatu mapurojekiti edemo anosanganisirwa muZip file. Vanokubvumira kuti udzore maperipherals pamapuranga akasiyana-siyana pamwe chete nemamwe makuru, marejista emukati.
Maforodha edemo anosanganisira pre-yakagadzirwa uart_regs.vhd uye uart_regs.py fileyakagadzirwa zvakananga kune izvo zvigadzirwa.

Lattice iCEstick

Iyo demo/icecube2_icestick folda ine rejista yekuwana demo kuitisa yeLattice iCEstick FPGA bhodhi.
Kuti umhanye kuburikidza nekuita maitiro, vhura demo/lattice_icestick/icecube2_proj/uart_regs_sbt.project file muLattice iCEcube2 dhizaini software.
Mushure mekurodha purojekiti mu iCEcube2 GUI, tinya Zvishandiso → Mhanya Zvese kuti ugadzire iyo programming bitmap. file.

Unogona kushandisa Lattice Diamond Programmer Standalone chishandiso kugadzirisa iyo FPGA neyakagadzirwa bitmap. file. Kana Diamond Programmer inovhura, tinya Vhura chirongwa chiripo chepurogiramu mubhokisi rekugamuchira rekugamuchira.
Sarudza chirongwa file inowanikwa muZip: demo/lattice_icestick/diamond_programmer_project.xcf wobva wadzvanya OK.
Mushure mekutakura purojekiti, tinya madotsi matatu mu File Zita column, sezvaratidzwa pamusoro. Bhurawuza kuti usarudze bitmap file iyo yawakagadzira muICEcube2

demo/lattice_icestick/icecube2_proj/uart_regs_Implmnt/sbt/outputs/bitmap/top_icestick_bitmap.bin
Chekupedzisira, ne iCEstick board yakanamirwa mu USB port pakombuta yako, sarudza Dhizaina→ Chirongwa kuronga iyo SPI flash uye kugadzirisa iyo FPGA.
Iwe unogona ikozvino kuenderera mberi nekuverenga nekunyora marejista uchishandisa demo/lattice_icestick/uart_regs.py script sekutsanangurwa kwazvinoitwa muchikamu cheuart_regs.py.

Xilinx Digilent Arty A7-35T

Unogona kuwana kuisirwa kwedemo kweArtix-7 35T Arty FPGA yekuongorora kit mune demo/arty_a7_35 folda.
Vhura Vivado uye enda kune yakabviswa files uchishandisa iyo Tcl console inowanikwa pazasi peiyo GUI interface. Nyora murairo uyu kuti uise demo project folder:

cd /demo/arty_a7_35/vivado_proj/
Isa iyo create_vivado_proj.tcl Tcl script kuti udzorezve chirongwa cheVivado:
kunobva ./create_vivado_proj.tcl

Dzvanya Gadzira Bitstream mubhara reparutivi kuti umhanye nematanho ese ekuita uye gadzira iyo programming bitstream file.
Pakupedzisira, tinya Vhura Hardware Manager uye ronga iyo FPGA kuburikidza neGUI.
Iwe unogona ikozvino kuenderera mberi nekuverenga nekunyora marejista uchishandisa demo/arty_a7_35/uart_regs.py script sekutsanangurwa kwazvinoitwa muchikamu cheuart_regs.py.

Xilinx Digilent Arty S7-50

Unogona kuwana kuisirwa kwedemo kweiyo Arty S7: Spartan-7 FPGA yekuvandudza bhodhi mune iyo demo/arty_s7_50 folda.
Vhura Vivado uye enda kune yakabviswa files uchishandisa iyo Tcl console inowanikwa pazasi peiyo GUI interface. Nyora murairo uyu kuti uise demo project folder:

cd /demo/arty_s7_50/vivado_proj/
Isa iyo create_vivado_proj.tcl Tcl script kuti udzorezve chirongwa cheVivado:
kunobva ./create_vivado_proj.tcl

Dzvanya Gadzira Bitstream mubhara reparutivi kuti umhanye nematanho ese ekuita uye gadzira iyo programming bitstream file.
Pakupedzisira, tinya Vhura Hardware Manager uye ronga iyo FPGA kuburikidza neGUI.
Iwe unogona ikozvino kuenderera mberi nekuverenga nekunyora marejista uchishandisa demo/arty_s7_50/uart_regs.py script sekutsanangurwa kwazvinoitwa muchikamu cheuart_regs.py.

Implementation

Iko hakuna chaiyo yekushandisa zvinodiwa.

Zvipingamupinyi

Hapana zvipingaidzo zvenguva zvinodikanwa padhizaini iyi nekuti iyo UART interface inononoka uye inobatwa seasynchronous interface.

Iyo uart_rx yekuisa kune uart_regs module inowiriraniswa mukati meuart_rx module. Nekudaro, haidi kuwiriraniswa mune yepamusoro-level module.

Nyaya dzinozivikanwa

Ungangoda kusetazve module isati yashandiswa, zvichienderana nekuti yako FPGA dhizaini inotsigira default rejista tsika.

More info

FAQs

Mubvunzo: Chii chinangwa cheUART test interface jenareta?

A: Iyo UART test interface jenareta inobvumira kugadzirwa kwetsika inopindirana kuti idyidzane neFPGA rejista kukosha uchishandisa UART kutaurirana.

Mubvunzo: Ndinoisa sei Pyserial package?

A: Unogona kuisa Pyserial kuburikidza nePip uchishandisa murairo: pip install pyserial

Zvinyorwa / Zvishandiso

VHDLwhiz UART Test Interface Generator [pdf] User Manual
UART Test Interface jenareta, Test Interface jenareta, Interface jenareta, jenareta

References

User Manual

VHDLwhiz UART Test Interface Generator

Product Information