intel Triple-Speed Ethernet Agilex FPGA IP Dhizaini Example
Quick Start Guide
Iyo Triple-Speed Ethernet Intel® FPGA IP yeIntel Agilex ™ inopa kugona kwekugadzira dhizaini ex.amples yezvirongwa zvakasarudzwa, izvo zvinokutendera kuti:
- Unganidza dhizaini kuti uwane fungidziro yekushandiswa kwenzvimbo yeIP uye nguva.
- Tevedzera dhizaini kuti uone kushanda kweIP kuburikidza nekuenzanisa.
- Edza dhizaini pane Hardware uchishandisa Intel Agilex I-Series Transceiver-SoC Development Kit.
- Kana iwe ukagadzira dhizaini example, iyo parameter editor inogadzira iyo fileinodiwa kutevedzera, kuunganidza, uye kuyedza dhizaini muhardware.
Cherechedza: Rutsigiro rwe Hardware parizvino haiwanikwe muIntel Quartus® Prime Pro Edition Software vhezheni 22.3.
Development Stages yeDesign Example
Cherechedza: MuIntel Quartus Prime Pro Edition Software vhezheni 22.3, chigamba chinodiwa kudzivirira kutadza kutevedzera pane dhizaini ex.ample. Kuti uwane rumwe ruzivo, tarisa kune KDB chinongedzo: Sei simulation ichitadza kune iyo Triple-Speed Ethernet Intel FPGA IP Multiport Dhizaini Ex.ample?.
Related Information
Nei simulation ichitadza kune iyo Triple-Speed Ethernet Intel® FPGA IP Multiport Dhizaini Example?.
Directory Structure
Iyo Triple-Speed Ethernet Intel FPGA IP dhizaini example file madhairekitori ane zvinotevera kugadzirwa files ye10/100/1000 Multiport Ethernet MAC Dhizaini Example ine 1000BASE-X/SGMII PCS uye Embedded PMA
- Iyo hardware kumisikidza uye bvunzo files (iyo hardware dhizaini example) vari mukatiample_dir>/hardware_test_design.
- The simulation files (testbench yekufananidza chete) iri mukatiample_dir>/example_testbench.
- Iyo yekuunganidza-chete dhizaini example iri muample_dir>/ compilation_test_design.
- Iyo yekuunganidza bvunzo uye Hardware bvunzo madhizaini anoshandisa files muample_dir>/ex_tse/common.
Dhairekitori Magadzirirwo eDesign Example
Tafura 1. Triple-Speed Ethernet Intel FPGA IP Testbench File Tsanangudzo
| Dhairekitori/File | Tsanangudzo |
| Testbench uye Simulation Files | |
| <design_example_dir>/example_testbench/ basic_avl_tb_top_mac_pcs.sv | Top-level testbench file. Testbench inosimbisa iyo DUT uye inomhanyisa Verilog HDL mabasa kugadzira uye kugamuchira mapaketi. |
| Testbench Scripts | |
| <design_example_dir>/example_testbench/ run_vsim_mac_pcs.sh | Iyo ModelSim script yekumhanyisa testbench. |
| akaenderera… | |
| Dhairekitori/File | Tsanangudzo |
| <design_example_dir>/example_testbench/ run_vcs_mac_pcs.sh | Iyo Synopsy* VCS script yekumhanyisa testbench. |
| <design_example_dir>/example_testbench/ run_vcsmx_mac_pcs.sh | Iyo Synopsys VCS MX script (yakasanganiswa Verilog HDL uye System Verilog ine VHDL) kumhanyisa testbench. |
| <design_example_dir>/example_testbench/ run_xcelium_mac_pcs.sh | Iyo Xcelium* script yekumhanyisa testbench. |
Tafura 2. Triple-Speed Ethernet Intel FPGA IP Hardware Design Example File Tsanangudzo
| Dhairekitori/File | Tsanangudzo |
| <design_example_dir>/hardware_test_design/ altera_eth_tse_hw.qpf | Intel Quartus Prime chirongwa file. |
| <design_example_dir>/hardware_test_design/ altera_eth_tse_hw.qsf | Intel Quartus Prime purojekiti marongero file. |
| <design_example_dir>/hardware_test_design/ altera_eth_tse_hw.sdc | Synopsys Design Constraints files. Unogona kukopa uye kugadzirisa izvi files kune yako wega Intel Stratix® 10 dhizaini. |
| <design_example_dir>/hardware_test_design/ altera_eth_tse_hw.v | Yepamusoro-chikamu Verilog HDL dhizaini example file. |
| <design_example_dir>/hardware_test_design/ common/ | Hardware design example support files. |
Kugadzira iyo Dhizaini Example
Maitiro Ekugadzira Dhizaini Example
Exampuye Dhizaini Tab muTriple-Speed Ethernet Intel FPGA IP Parameter Mharidzo
Tevedza nhanho idzi kugadzira iyo hardware dhizaini example uye testbench:
- MuIntel Quartus Prime Pro Edition software, tinya File ➤ New Project Wizard kugadzira itsva Quartus Prime project, kana File ➤ Vhura Project kuvhura iripo Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo.
- Sarudza Intel Agilex mudziyo mhuri uye sarudza mudziyo une LVDS.
- Dzvanya Finish kuti uvhare wizard.
- MuIP Catalog, tsvaga uye sarudza Interface Protocol ➤ Ethernet ➤ 1G Multirate
- Ethernet ➤ Triple-Speed Ethernet Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
- Taura zita repamusoro-soro kune yako tsika IP musiyano. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
- Dzvanya OK. Iyo parameter editors inooneka.
- Kugadzira dhizaini example, sarudza dhizaini example preset kubva Presets raibhurari uye tinya Nyorera. Paunosarudza dhizaini, iyo sisitimu inozadza otomatiki IP paramita yedhizaini. Iyo parameter mupepeti inoisa otomatiki maparamendi anodiwa kugadzira iyo dhizaini example. Usachinje preset paramita muIP tebhu.
- For Example Dhizaini Files, sarudza Simulation sarudzo yekugadzira testbench, kana Synthesis sarudzo yekugadzira iyo hardware dhizaini example.
- Ongorora: Iwe unofanirwa kusarudza inokwana imwe yesarudzo kuti ugadzire iyo dhizaini example.
- Pamusoro peExample Dhizaini tebhu, pasi Yakagadzirwa HDL Format, sarudza Verilog HDL kana VHDL.
- Pasi peTarget Development Kit, sarudza iyo Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) kana sarudza Hapana
- Dzvanya Example Design: “example_design” bhatani. Sarudza Example Dhizaini Dhairekitori hwindo rinoonekwa.
- Kana iwe uchida kugadzirisa iyo dhizaini exampiyo dhairekitori nzira kana zita kubva kune zvakasara zvakaratidzwa (eth_tse_0_example_design), tsvaga kunzira nyowani uye nyora iyo nyowani dhizaini exampzita rezita (ample_dir>).
- Dzvanya OK.
Design Example Parameters
Parameters muExampuye Design Tab
| Parameter | Tsanangudzo |
| Sarudza Dhizaini | Aripo example magadzirirwo eiyo IP parameter marongero. |
| Example Dhizaini Files | The files kugadzira chikamu chebudiriro chakasiyana.
• Kutevedzera—kunoita zvinodiwa files yekutevedzera example design. • Synthesis-inogadzira synthesis files. Shandisa izvi files kuunganidza dhizaini muIntel Quartus Prime Pro Edition software yekuyedza Hardware uye kuita static nguva yekuongorora. |
| Gadzira File Format | Iyo fomati yeRTL files yekufananidza-Verilog kana VHDL. |
| Sarudza Bhodhi | Yakatsigirwa hardware yekugadzira dhizaini. Paunosarudza Intel FPGA yekuvandudza bhodhi, iyo Target Device ndiyo inoenderana nemudziyo uri paDevelopment Kit.
Kana iyi menyu isipo, hapana bhodhi rinotsigirwa resarudzo dzaunosarudza. Agilex I-Series Transceiver-SoC Development Kit: Iyi sarudzo inokubvumira kuti uedze dhizaini example pane yakasarudzwa Intel FPGA IP yekuvandudza kit. Iyi sarudzo inosarudza otomatiki iyo Target Device kuenzanisa mudziyo paIntel FPGA IP yekuvandudza kit. Kana yako bhodhi revision ine akasiyana mudziyo giredhi, unogona kuchinja chinangwa mudziyo. Hapana: Iyi sarudzo haisanganisi zvinhu zvehardware zveiyo dhizaini example. |
Kutevedzera iyo Triple-Speed Ethernet Intel FPGA IP Dhizaini Example Testbench
Maitiro ekutevedzera Example Testbench
Tevera matanho aya kutevedzera testbench:
- Shandura kune testbench simulation dhairekitoriample_dir>/ example_testbench.
- Mhanya iyo simulation script yeiyo inotsigirwa simulator yesarudzo yako. Iyo script inounganidza uye inomhanyisa testbench mune simulator. Tarisa kune tafura Matanho ekutevedzera Testbench.
Matanho ekutevedzera Testbench
| Simulator | Mirayiridzo |
| ModelSim* | Mumutsara wekuraira, nyora vsim -do run_vsim_mac_pcs.do. Kana ukasarudza kutevedzera pasina kuunza ModelSim GUI, nyora vsim -c -do run_vsim_mac_pcs.do. |
| Synopsys VCS*/ VCS MX | Mumutsara wekuraira, nyora sh run_vcs_mac_pcs.sh kana sh run_vcsmx_mac_pcs.sh. |
| Xcelium | Mumutsara wekuraira, nyora sh run_xcelium_mac_pcs.sh. |
- Ongorora zvabuda. Iyo testbench yakabudirira inotumira mapaketi gumi, inogamuchira yakafanana nhamba yemapakiti, uye inoratidza inotevera meseji.
Kunyora uye Kugadzirisa Dhizaini Example mu Hardware
Kuunganidza iyo hardware dhizaini example uye gadzirisa pane yako Intel Agilex mudziyo, tevera matanho aya:
- Ita shuwa kuti hardware dhizaini example generation yapera.
- MuIntel Quartus Prime Pro Edition software, vhura iyo Intel Quartus Prime purojekitiample_dir>/hardware_test_design/ altera_eth_tse_hw.qpf.
- Pane iyo Processing menyu, tinya Start Compilation.
- Mushure mekubudirira kuunganidza, a.sof file inowanikwa muample_dir>/hardwarde_test_design directory
10/100/1000 Multiport Ethernet MAC Dhizaini Example ine 1000BASE-X/SGMII PCS uye Embedded PMA
Iyi dhizaini example inoratidza mhinduro yeEthernet yeIntel Agilex zvishandiso uchishandisa iyo Triple-Speed Ethernet IP. Iwe unogona kugadzira dhizaini kubva kuExample Dhizaini tebhu yeTriple-Speed Ethernet IP parameter mupepeti. Kugadzira iyo dhizaini exampuye, iwe unofanirwa kutanga waisa iyo parameter kukosha kweiyo IP mutsauko waunoda kugadzira mune yako yekupedzisira chigadzirwa. Kugadzira iyo dhizaini example inogadzira kopi yeIP. Iyo testbench uye hardware dhizaini exampuye shandisa kopi yeIP semudziyo uri mukuedzwa (DUT). Kana iwe ukasaisa iyo parameter kukosha kweDUT kuti ienderane neiyo parameter kukosha mune yako yekupedzisira chigadzirwa, dhizaini ex.ampiyo iwe yaunogadzira haishandisi iyo IP mutsauko waunoda.
Features
- Inogadzira iyo yakagadzirwa example yeTtatu-Speed Ethernet Multiport Ethernet MAC isina Yemukati FIFO uye PCS ine LVDS I/O uchishandisa akawanda-channel yakagovaniswa FIFO.
- Inogadzira traffic munzira yekufambisa uye inosimbisa yakagamuchirwa data kuburikidza neiyo transceiver LVDS I / O yekunze loopback.
- Tx uye RX serial yekunze loopback modhi kuburikidza neLVDS I/O.
- Inotsigira chete loopback yekunze.
- Inotsigira zviteshi zvina chete.
Hardware uye Software Zvinodiwa
- Intel inoshandisa iyi inotevera Hardware uye software kuyedza iyo dhizaini exampuye mune Linux system:
- Intel Quartus Prime Pro Edition software
- ModelSim, VCS, VCS MX, uye Xcelium simulators
Tsanangudzo Yekushanda
Dhizaini Zvikamu
| Chikamu | Tsanangudzo |
| Katatu-Speed Ethernet Intel FPGA IP | Iyo Triple-Speed Ethernet Intel FPGA IP (altera_eth_tse) inomisikidzwa neinotevera gadziriro:
• Magadzirirwo Akakosha: — Core Variation: 10/100/1000Mb Ethernet MAC ine 1000BASE-X/SGMII PCS — Shandisa yemukati FIFO: Haina kusarudzwa — Nhamba yezviteshi: 4 — Transceiver mhando: LVDS I/O • MAC Options: — Gonesa MAC 10/100 hafu duplex rutsigiro: Akasarudzwa — Gonesa loopback yemunharaunda paMII/GMII: Akasarudzwa — Gonesa yekuwedzera MAC unicast kero: Haina kusarudzwa — Batanidza nhamba dzekuverenga: Akasarudzwa — Gonesa 64-bit statistics byte counters: Haina kusarudzwa — Batanidza multicast hashtable: Haina kusarudzwa — Rongedza misoro yepakiti kune 32-bit muganhu: Haina kusarudzwa — Gonesa full-duplex flow control: Akasarudzwa — Ita kuti VLAN ionekwe: Haina kusarudzwa — Ita kuti mashiripiti aonekwe: Akasarudzwa — Sanganisira MDIO module (MDC/MDIO): Akasarudzwa — Host wachi divisor: 50 • Nguvaamp Sarudzo: — Vhura nguvaamping: Haina kusarudzwa • PCS/Transceiver Options: — Gonesa SGMII zambuko: Akasarudzwa |
| Client Logic | Inogadzira uye inotarisisa mapaketi anotumirwa kana kugamuchirwa kuburikidza neIP. |
| Ethernet Traffic Controller | Inodzorwa kuburikidza neAvalon® memory-mapped interface. |
| JTAG kuAvalon memory-mapped interface Kero Decoder | Shandura JTAG Zviratidzo zveAvalon memory-mapped interface. |
Clock uye Reset Signals
| Signal | Direction | Upamhi | Tsanangudzo |
| ref_clk | Input | 1 | Madhiraivha anonyoresa yekuwana referensi wachi uye MAC FIFO chimiro chekutarisa wachi. Isa wachi ku100 MHz. |
| iopll_refclk | Input | 1 | 125 MHz referensi wachi yeiyo 1.25 Gbps seriyoni LVDS I/O interface. |
Simulation
Iyo simulation test kesi inoita nhanho dzinotevera:
- Anotanga dhizaini example nekumhanya kwekushanda kwe1G.
- Inogadzirisa Triple-Speed Ethernet MAC uye PCS marejista.
- Inomirira kusvika chirevo chechiyero chinoshanda chiratidzo.
- Inotumira asiri-PTP mapaketi kuchiteshi 0.
- MAC RX port 0 inotumira mapaketi akagamuchirwa kuMAC TX port 1.
Testbench
Block Dhizaini yeDesign Example Multiport 10/100/1000Mb Ethernet MAC ine 1000BASE-X/SGMII PCS ine LVDS I/O Simulation Testbench
Simulation Muedzo Mhedzisiro yeVCS Simulator
Document Revision History for the Triple-Speed Ethernet Intel FPGA IP Intel Agilex Dhizaini Example User Guide
| Document Version | Intel Quartus Prime Version | IP Version | Kuchinja |
| 2022.12.09 | 22.3 | 21.1.0 | Kusunungurwa kwekutanga. |
Zvinyorwa / Zvishandiso
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intel Triple-Speed Ethernet Agilex FPGA IP Dhizaini Example [pdf] Bhuku reMushandisi Katatu-Speed Ethernet Agilex FPGA IP Dhizaini Example, Triple-Speed, Ethernet Agilex FPGA IP Dhizaini Example, IP Dhizaini Example |
