intel OPAE FPGA Linux Fa'ata'ita'iga Aveta'avale masini

OPAE Intel FPGA Linux Fa'ata'ita'iga Aveta'avale masini

O le OPAE Intel FPGA aveta'avale e tu'uina atu feso'ota'iga mo fa'aoga avanoa e fa'aoga ai, fa'amatala, tatala, ma fa'aoga FPGA fa'avavevave i luga o fa'avae fa'apipi'iina i Intel FPGA fofo ma mafai ai ona fa'atino galuega fa'afoe e pei o le FPGA toe fa'atulagaina, pulega o le eletise, ma le virtualization.

Fa'ata'ita'iga o Meafaigaluega

Mai le tulaga o le OS o view, o le meafaigaluega FPGA e foliga mai o se masini PCIe masani. O le manatuaga o le masini FPGA o lo'o fa'atulagaina e fa'aaoga ai se fa'asologa o fa'amaumauga (Device Feature List). O mea e lagolagoina e le masini FPGA o loʻo faʻaalia e ala i nei faʻamaumauga, e pei ona faʻaalia i lalo i le ata o loʻo i lalo:

FPGA PCIe masini

E lagolagoina e le aveta'avale PCIe SR-IOV e fatu ai Galuega Fa'atino (VFs) lea e mafai ona fa'aoga e fa'atonu ai fa'avavevave ta'ito'atasi i masini masini.

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'atau a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie fa'aalia i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel e maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua.

O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

FPGA PCIe masini

FPGA Pulega afi (FME)
O le FPGA Management Engine e fa'atino ai le mana ma le fa'avevela, fa'amatalaga sese, toe fa'afouina, lipoti o fa'atinoga, ma isi galuega tetele. O FPGA ta'itasi e tasi le FME, lea e maua i taimi uma e ala i le Fa'atinoga Fa'aletino (PF). E mafai ona maua avanoa fa'apitoa i le FME e fa'aoga ai le avanoa e fa'aoga ai le avanoa e fa'aoga ai le avanoa e fa'aaoga ai le close() e avea ma tagata fa'apitoa (a'a).

Taulaga
O le Taulaga o lo'o fa'atusalia le feso'ota'iga i le va o le ie FPGA static (le "FPGA Interface Manager (FIM)") ma se vaega e mafai ona toe fa'aogaina o lo'o iai le Accelerator Function (AF). O le Taulaga e pulea le fesoʻotaʻiga mai le polokalama i le faʻavavevave ma faʻaalia foliga e pei o le toe setiina ma le debug. O se masini PCIe e mafai ona tele Ports, ma e mafai ona fa'aalia Ports ta'itasi e ala i le VF e ala i le tu'uina atu e fa'aaoga ai le FPGA_FME_PORT_ASSIGN ioctl i le masini FME.

Fuafuaga Accelerator (AF) Vaega

• O lo'o fa'apipi'i se Vaega Fa'avavevave (AF) i se Taulaga ma fa'aalia ai se itulagi e 256K MMIO e fa'aoga mo tusi resitala fa'atonu fa'avavevave.
• E mafai ona maua avanoa fa'apitoa i se AFU o lo'o fa'apipi'i i se Taulaga e ala i le fa'aogaina o le matala() i luga o le masini Port, ma fa'asa'oloto e fa'aoga latalata().
• E mafai fo'i e fa'aoga-avanoa talosaga mmap() fa'avavevave MMIO itulagi.

Toe fetuutuunai vaega
E pei ona taʻua i luga, e mafai ona toe faʻaleleia le faʻavavevave e ala i le toe faʻatulagaina o se vaega o le Accelerator Function (AF) file. Ole Fa'agaioiga Fa'avavevave (AF) e tatau ona fa'atupuina mo le FIM tonu ma le fa'aitulagi fa'atatau (Port) ole FPGA; a le o lea, o le a le manuia le faʻaogaina o le faʻatonuga ma e ono mafua ai le le mautonu o le faiga. E mafai ona siaki lenei feso'ota'iga e ala i le fa'atusatusaina o le ID fa'afeso'ota'i o lo'o ta'ua i le ulutala AF fa'asaga i le ID ID fa'aalia e le FME e ala i sysfs. Ole siaki lea e masani ona faia ile avanoa ole tagata fa'aoga a'o le'i vala'au ile toefa'atonu IOCTL.

Fa'aaliga:
I le taimi nei, soʻo se polokalama faakomepiuta e mafai ona maua le FPGA, e aofia ai i latou o loʻo taʻavale i totonu o se talimalo faʻapitoa, e tatau ona tapunia aʻo leʻi taumafai e toe faʻaleleia se vaega. O laasaga o le a:

1. La'u ese le aveta'avale mai le malo
2. Aveese le VF mai le malo
3. Taofi le SR-IOV
4. Fa'atino vaega toe fetuutuunai
5. Fa'amalo le SR-IOV
6. Fa'apipi'i le VF i le malo
7. uta le avetaavale i totonu o le malo

FPGA Virtualization
Ina ia mafai ona maua se faʻavavevave mai tusi talosaga o loʻo taʻavale i totonu o se VM, e manaʻomia ona tuʻuina atu le taulaga a le AFU i se VF e faʻaaoga ai laasaga nei:

1. O le PF e ona uma ports AFU ona o le faaletonu. So'o se uafu e mana'omia ona toe fa'afo'i i le VF e tatau ona tu'u muamua mai le PF e ala ile FPGA_FME_PORT_RELEASE ioctl ile masini FME.
2. O le taimi lava e tatala ai N ports mai le PF, o le poloaiga o loʻo i lalo e mafai ona faʻaogaina e mafai ai e SRIOV ma VFs. O VF ta'itasi e na'o le tasi le uafu ma le AFU. echo N > PCI_DEVICE_PATH/sriov_numvfs
3. Pasia le VF i VM.
4. O le AFU i lalo o le VF e mafai ona maua mai talosaga i le VM (fa'aoga le aveta'avale tutusa i totonu o le VF).

Fa'aaliga:
E le mafai ona tu'uina atu se FME i se VF, o lea e na'o le PF e maua ai le PR ma isi galuega tau pulega.

Faalapotopotoga Avetaavale

PCIe Module Device Driver

Faalapotopotoga Avetaavale

O masini FPGA e foliga mai o masini PCIe masani; o lea, o le avetaavale masini FPGA PCIe (intel-FPGA-PCI.ko) e masani lava ona uta muamua pe a iloa se FPGA PCIe PF poʻo VF. O lenei aveta'avale e fa'atino se sao fa'apitoa i le fa'ata'ita'iga o le aveta'avale. e:

• Fausia se masini koneteina FPGA e avea ma matua o masini faʻapitoa.
• Savalivali i le Lisi o Mea Fa'apitoa, lea e fa'atinoina i le PCIe masini BAR memory, e su'e ai masini fa'apitoa ma a latou vaega laiti ma fausia ni masini fa'avae mo i latou i lalo o le masini koneteina.
• Lagolago SR-IOV.
• Fa'ailoaina le fa'aogaina o masini fa'apitoa, lea e fa'ate'aina galuega mo vaega laiti ma fa'aalia galuega masani e fa'aalia ai ta'avale masini.

PCIe Module Device Aveta'avale Galuega

• O lo'o iai le su'esu'ega PCIe, fa'avasegaga o masini, ma le su'esu'eina o mea.
• Fausia sysfs directories mo le masini matua, FPGA Management Engine (FME), ma le Taulaga.
• Fausia tulaga aveta'avale tulaga, mafua ai ona utaina e le fatu Linux a latou ta'avale module ta'itasi.

FME Platform Module Device Driver

• Pulea ma le vevela, lipoti o mea sese, lipoti o faatinoga, ma isi galuega tetele. E mafai ona e mauaina nei galuega e ala i fesoʻotaʻiga sysfs faʻaalia e le avetaavale FME.
• Toe fetuutuunai vaega. E resitalaina e le aveta'avale FME se Pule o le FPGA i le taimi o le fa'avaeina o le PR; o le taimi lava e maua ai se FPGA_FME_PORT_PR ioctl mai ia te oe, e faʻaaogaina le galuega faʻaoga masani mai le FPGA Manager e faʻamaeʻa ai le toe faʻaleleia o le bitstream i le Taulaga ua tuʻuina atu.
• Puleaina o uafu mo virtualization. O le aveta'avale FME e fa'ailoa mai ai ioctls e lua, FPGA_FME_PORT_RELEASE, lea e fa'asa'olotoina le Taulaga tu'u mai PF; ma le FPGA_FME_PORT_ASSIGN, lea e tuʻuina atu le Taulaga i tua i le PF. O le taimi lava e tuʻuina atu ai le Taulaga mai le PF, e mafai ona tuʻuina atu i le VF e ala i fesoʻotaʻiga SR-IOV na tuʻuina atu e le avetaavale PCIe. Mo nisi faʻamatalaga, vaʻai ile "FPGA Virtualization".

FME Platform Module Device Avetaavale Galuega

• Fausia le node ole masini FME.
• Fausia le FME sysfs files ma fa'atino le FME sysfs file fesoasoani.
• Fa'atino le FME vaega ta'avale ta'avale laiti.
• FME tulaga tumaoti sub-aveta'avale:
  • Ulutala FME
  • Pulea vevela
  • Pulea Malosiaga
  • Sese ole lalolagi
  • Toe fetuutuunai vaega
  • Galuega Fa'alelalolagi

Port Platform Module Device Driver
E tutusa ma le aveta'avale FME, o le aveta'avale FPGA Port (ma le AFU) (intel-fpga-afu. Ko) e su'esu'eina pe a faia le masini fa'atūlagaa Port. O le galuega autu a lenei module o le tuʻuina atu lea o se atinaʻe mo faʻaoga-avanoa talosaga e maua ai le faʻavavevave taʻitasi, e aofia ai le faʻatonuina o le faʻatonuga i luga o le Taulaga, AFU MMIO e auina atu i fafo, DMA buffer mapping service, UMsg (1) faʻamatalaga, ma galuega faʻamama mamao ( vaai i luga).

UMsg e na'o le lagolagoina e ala i le Acceleration Stack mo le Intel Xeon® Processor ma le FPGA Fa'atasi.

Port Platform Module Device Driver Galuega

• Fausia le node o le masini o le Port character.
• Fausia le Port sysfs files ma faʻaaogaina le Port sysfs file fesoasoani.
• Fa'atinoina le Port private feature sub-drivers.
• Port private feature sub-drivers:
  • Ulutala Taulaga
  • AFU
  • Sese Taulaga
  • UMsg(2)
  • Fa'ailoga Tap

Talosaga FPGA Device Enumeration
O lenei vaega o loʻo faʻaalia ai le faʻaogaina e tusi talosaga le masini FPGA mai le sysfs hierarchy i lalo o /sys/class/fpga. I le exampi lalo, lua Intel FPGA masini faʻapipiʻi i totonu o le talimalo. O masini FPGA ta'itasi e tasi le FME ma le lua Taulaga (AFU). Mo masini FPGA taʻitasi, o se lisi o masini e faia i lalo o / sys / vasega / fpga:

/sys/class/fpga/intel-fpga-dev.0
/sys/class/fpga/intel-fpga-dev.1

O node ta'itasi e tasi le FME ma le lua Taulaga (AFUs) e fai ma masini tamaiti:
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-fme.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.2
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.3

I se tulaga lautele, o fesoʻotaʻiga FME/Port sysfs e taʻua e faapea:
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-fme.j/
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-port.k/

ma ou faanumera sosoo uma masini koneteina, j faanumera faanumera FME ma k faanumera sosoo uma Taulaga.

O nodes masini e fa'aoga mo ioctl() ma mmap() e mafai ona fa'asino ile:
/dev/intel-fpga-fme.j
/dev/intel-fpga-port.k

PCIe Avetaavale Enumeration
O lenei vaega o loʻo tuʻuina atu ai se faʻaopoopogaview o le faʻasologa o tulafono mo le faʻavasegaina o masini na faia e intel-fpga-pci.ko. O faʻamaumauga autu ma galuega tauave o loʻo faʻamaonia. O lenei vaega e sili ona mulimulitaia pe a viewi le fa'ailoga puna (pcie.c).

Fa'asologa o Fa'amaumauga o Fa'amaumauga

enum fpga_id_type {
PARENT_ID,
FME_ID,
PORT_ID,
FPGA_ID_MAX
};
static struct idr fpga_ids[FPGA_ID_MAX];
struct fpga_chardev_info {
const char *igoa;
dev_t devt;
};
struct fpga_chardev_info fpga_chrdevs[] = {
{ .igoa = FPGA_FEATURE_DEV_FME },
{ .igoa = FPGA_FEATURE_DEV_PORT },
};
vasega fa'atonuga *fpga_class;
static struct pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_DCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_DCP),},
{0,}
};
static struct pci_driver cci_pci_driver = {
.igoa = DRV_NAME,
.id_table = cci_pcie_id_tbl,
.su'esu'e = cci_pci_su'esu'e,
.aveese = cci_pci_remove,
.sriov_configure = cci_pci_sriov_configure
};
struct cci_drvdata {
int device_id;
struct masini *fme_dev;
struct mutex loka;
struct list_head port_dev_list;
int released_port_num;
struct list_head itulagi;
};
struct build_feature_devs_info {
struct pci_dev *pdev;
vale __iomem *ioaddr;
vale __iomem *ioend;
int current_bar;
fa'aleaogaina __iomem *pfme_hdr;
struct masini *parent_dev;
struct platform_device *feature_dev;
};

Fa'asologa o Fa'amaumauga

• ccidrv_init()
  • Fa'amatamata fpga_ids fa'aoga idr_init().
  • Fa'amatamata fpga_chrdevs[i].devt fa'aaoga alloc_chrdev_region().
  • Fa'amatamata fpga_class e fa'aaoga ai le class_create().
  • pci_register_driver(&cci_pci_driver);
• cci_pci_su'esu'e()
  • Faʻaaga le masini PCI, talosaga avanoa i ona itulagi, seti le PCI master mode, ma configure DMA.
• cci_pci_create_feature_devs() build_info_alloc_and_init()
  • Fa'asoa se struct build_feature_devs_info, amataina.
    .parent_dev ua seti i se matua sysfs directory (intel-fpga-dev.id) o loʻo iai le FME ma Port sysfs directories.
• parse_feature_list()
  • Savali i le BAR0 Device Feature List e su'e ai le FME, le Taulaga, ma o latou foliga patino.
• parse_feature() parse_feature_afus() parse_feature_fme()
  • Pe a feagai ma se FME:
• build_info_create_dev()
  • Fa'asoa se masini fa'avae mo le FME, teuina ile build_feature_devs_info.feature_dev.
  • feature_dev.id ua amata i le taunuuga o idr_alloc(fpga_ids[FME_ID],
  • feature_dev.parent ua seti ile build_feature_devs_info.parent_dev.
  • Fa'asoa se fa'asologa o punaoa fa'avae ile feature_dev.resource.
• Fa'asoa se struct feature_platform_data, amatalia, ma teu se fa'ailoga ile feature_dev.dev.platform_data
  • create_feature_instance() build_info_add_sub_feature()
  • Amata le feature_dev.resource[FME_FEATURE_ID_HEADER].
  • feature_platform_data_add()
  • Fa'amatamata feature_platform_data.features[FME_FEATURE_ID_HEADER], mea uma sei vagana .fops.
• parse_feature() parse_feature_afus() parse_feature_port()
  • Pe a maua se Taulaga:
• build_info_create_dev()
  • Fa'asoa se masini fa'avae mo le Taulaga, fa'aputu i build_feature_devs_info.feature_dev.
  • feature_dev.id ua amata i le taunuuga o idr_alloc(fpga_ids[PORT_ID],
  • feature_dev.parent ua seti ile build_feature_devs_info.parent_dev.
  • Fa'asoa se fa'asologa o punaoa fa'avae ile feature_dev.resource.
  • Fa'asoa se struct feature_platform_data, amatalia, ma teu se fa'ailoga ile feature_dev.dev.platform_data
• build_info_commit_dev()
  • Faaopoopo le struct feature_platform_data.node mo le Taulaga i le lisi o Taulaga i le struct cci_drvdata.port_dev_list
• create_feature_instance() build_info_add_sub_feature()
  • Amata le feature_dev.resource[PORT_FEATURE_ID_HEADER].
• feature_platform_data_add()
  • Fa'amatamata feature_platform_data.features[PORT_FEATURE_ID_HEADER], mea uma vagana .fops.
• parse_feature() parse_feature_afus() parse_feature_port_uafu()
  • Pe a maua se AFU:
• create_feature_instance() build_info_add_sub_feature()
  • Amata le feature_dev.resource[PORT_FEATURE_ID_UAFU].
• feature_platform_data_add()
  • Fa'amatamata feature_platform_data.features[PORT_FEATURE_ID_UAFU], mea uma sei vagana .fops.
• parse_feature() parse_feature_private() parse_feature_fme_private()
  • Pe a maua se vaega tumaoti a le FME:
• create_feature_instance() build_info_add_sub_feature()
  • Ulutala feature_dev.resource[id].
• feature_platform_data_add()
  • Initialize feature_platform_data.features[id], mea uma ae vagana ai .fops.
• parse_feature() parse_feature_private() parse_feature_port_private()
• Pe a o'o mai se vaega fa'apitoa Taulaga: * create_feature_instance() build_info_add_sub_feature() * Initialize feature_dev.resource[id]. * feature_platform_data_add() Initialize feature_platform_data.features[id], mea uma ae .fops.
• parse_ports_from_fme()
  • Afai o loʻo faʻapipiʻiina le avetaʻavale i luga o le Physical Function (PF), ona:
• Fa'asolo le parse_feature_list() tafe i luga o taulaga ta'itasi o lo'o fa'amatalaina ile ulutala FME.
• Fa'aoga le BAR o lo'o ta'ua i totonu o le Taulaga ta'itasi i le ulutala.

FME Platform Device Initialization
O lenei vaega o loʻo tuʻuina atu ai se faʻaopoopogaview o le faʻasologa o tulafono mo le amataina o masini FME na faia e le intel-fpga-fme.ko. O fa'amaumauga autu ma galuega tauave e fa'apupulaina. O lenei vaega e sili ona mulimulitaia pe a viewi totonu o le fa'ailoga puna (fme-main.c).

FME Platform Mea Fa'atonu Fa'amaumauga

struct feature_ops {
int (* init)(struct platform_device *pdev, struct feature * feature);
int (*uinit)(struct platform_device *pdev, struct feature * feature);
umi (* ioctl)(struct platform_device *pdev, struct feature * feature,
unsigned int cmd, unsigned long arg);
int (* su'ega)(struct platform_device *pdev, struct feature *featura);
};
struct feature {
const char *igoa;
int punaoa_index;
vale __iomem *ioaddr;
struct feature_ops *ops;
};
struct feature_platform_data {
struct list_head node;
struct mutex loka;
dev_status umi e le'i sainia;
fausaga cdev cdev;
struct platform_device *dev;
unsigned int disable_count;
fa'agaogao *fa'atasi;
int numera;
int (*config_port)(struct platform_device *, u32, bool);
struct platform_device *(*fpga_for_each_port)(struct platform_device *,
void *, int (*match)(struct platform_device *, void *)); struct
uiga fa'apitoa[0];
};
struct perf_object {
int id;
const struct attribute_group **attr_groups;
struct masini *fme_dev;
struct list_head node;
struct list_head tamaiti;
struct kobject kobj;
};
struct fpga_fme {
u8 port_id;
u64 pr_err;
struct masini *dev_err;
struct perf_object *perf_dev;
struct feature_platform_data *pdata;
};

FME Platform Device Initialization tafega

FME Initialization Fa'asolo

• fme_su'esu'e() fme_dev_init()
  • Amata se struct fpga_fme ma teu i le feature_platform_data.private fanua.
• fme_probe() fpga_dev_feature_init() feature_instance_init()
  • Fa'asaoina se struct feature_ops i le feature_platform_data.features mo vaega ta'itasi o lo'o fa'anofoina.
  • Valaau le galuega faataitai, pe afai ei ai, mai le struct.
  • Valaau le galuega init mai le struct.
• fme_su'esu'e() fpga_register_dev_ops()
  • Fausia le node masini FME, resitalaina se fausaga file_gaioiga.

Fa'amataina o Mea Fa'apipi'i Taulaga
O lenei vaega o loʻo tuʻuina atu ai se faʻaopoopogaview o le fa'asologa o tulafono mo le amataina o masini uafu na faia e le intel-fpga-afu.ko. O faʻamaumauga autu ma galuega tauave o loʻo faʻamaonia. O lenei vaega e sili ona mulimulitaia pe a viewi le fa'ailoga fa'apogai (afu.c).

Fa'atonuga o Fa'amaumauga o Meafaitino Tau Taulaga

struct feature_ops {
int (* init)(struct platform_device *pdev, struct feature * feature);
int (*uinit)(struct platform_device *pdev, struct feature * feature);
umi (* ioctl)(struct platform_device *pdev, struct feature * feature,
unsigned int cmd, unsigned long arg);
int (* su'ega)(struct platform_device *pdev, struct feature *featura);
};
struct feature {
const char *igoa;
int punaoa_index;
vale __iomem *ioaddr;
struct feature_ops *ops;
};
struct feature_platform_data {
struct list_head node;
struct mutex loka;
dev_status umi e le'i sainia;
fausaga cdev cdev;
struct platform_device *dev;
unsigned int disable_count;
fa'agaogao *fa'atasi;
int numera;
int (*config_port)(struct platform_device *, u32, bool);
struct platform_device *(*fpga_for_each_port)(struct platform_device *,
void *, int (*match)(struct platform_device *, void *));
struct feature features[0];
};
struct fpga_afu_region {
u32 faasino upu;
fu'a u32;
u64 tele;
u64 offset;
u64 tino;
struct list_head node;
};
struct fpga_afu_dma_region {
u64 user_addr;
u64 umi;
u64 iova;
struct itulau **itulau;
struct rb_node node;
bool in_use;
};
struct fpga_afu {
u64 itulagi_cur_offset;
int num_regions;
u8 num_umsgs;
struct list_head itulagi;
struct rb_root dma_regions;
struct feature_platform_data *pdata;
};

Fa'aulufalega o Mea Fa'apipi'i Taulaga

Fa'amataina le Taulaga

• afu_probe() afu_dev_init()
  • Amata se struct fpga_afu ma teu i le feature_platform_data.private fanua.
• afu_probe() fpga_dev_feature_init() feature_instance_init()
  • Fa'asaoina se struct feature_ops i le feature_platform_data.features mo vaega ta'itasi o lo'o fa'anofoina.
  • Valaau le galuega faataitai, pe afai ei ai, mai le struct.
  • Valaau le galuega init mai le struct.
• afu_su'esu'e() fpga_register_dev_ops()
  • Fausia le node o le Port character device, resitalaina se fausaga file_gaioiga.

FME IOCTLs
IOCTLs e vala'au ile avanoa file fa'amatala mo /dev/intel-fpga-fme.j FPGA_GET_API_VERSION—fa'afo'i le fa'asologa o lo'o iai nei o se numera, amata mai le 0.

FPGA_CHECK_EXTENSION—e lē o lagolagoina nei.

FPGA_FME_PORT_RELEASE—arg o se faasinoala i se:

struct fpga_fme_port_release {
__u32 argsz; // ile: sizeof(struct fpga_fme_port_release)
__u32 fu'a; // i: e tatau ona 0
__u32 port_id; // i: ID port (mai le 0) e faʻasaʻo.
};

FPGA_FME_PORT_ASSIGN—arg o se faasinoala i se:

struct fpga_fme_port_assign {
__u32 argsz; // ile: sizeof(struct fpga_fme_port_assign)
__u32 fu'a; // i: e tatau ona 0
__u32 port_id; // i: ID port (mai le 0) e tofia. (e tatau lava
na tatalaina muamua e FPGA_FME_PORT_RELEASE)
};

FPGA_FME_PORT_PR—arg o se faasinoala i se:

struct fpga_fme_port_pr {
__u32 argsz; // ile: sizeof(struct fpga_fme_port_pr)
__u32 fu'a; // i: e tatau ona 0
__u32 port_id; // i totonu: ID ID (mai le 0)
__u32 lapo'a_pui; // i le: lapopoa o le bitstream buffer i paita. E tatau ona 4-byte
fetaui.
__u64 tuatusi_tumau; // i: faʻasologa o tuatusi o le bitstream buffer
__u64 tulaga; // fafo: tulaga sese (bitmask)
};

Port IOCTLs
IOCTLs e vala'au ile avanoa file fa'amatala mo /dev/intel-fpga-port.k FPGA_GET_API_VERSION—fa'afo'i le lomiga o lo'o i ai nei o se numera, amata mai le 0. FPGA_CHECK_EXTENSION-e le o lagolagoina i le taimi nei.

FPGA_PORT_GET_INFO—arg o se faasinoala i se:

struct fpga_port_info {
__u32 argsz; // i totonu: sizeof(struct fpga_port_info)
__u32 fu'a; // i fafo: toe foʻi 0
__u32 numera_itulagi; // fafo: numera o itulagi MMIO, 2 (1 mo AFU ma 1 mo
STP)
__u32 num_umsgs; // fafo: numera o UMsg e lagolagoina e meafaigaluega
};

FPGA_PORT_GET_REGION_INFO—arg o se faasinoala i se:

struct fpga_port_region_info {
__u32 argsz; // ile: sizeof(struct fpga_port_region_info)
__u32 fu'a; // i fafo: (bitmask) { FPGA_REGION_READ, FPGA_REGION_WRITE,
FPGA_REGION_MMAP }
__u32 faasino upu; // ile: FPGA_PORT_INDEX_UAFU poʻo le FPGA_PORT_INDEX_STP
__u32 fa'aofuofu; // i: e tatau ona 0
__u64 lapopoa; // fafo: tele o le itulagi MMIO i bytes
__u64 offset; // fafo: offset o le MMIO itulagi mai le amataga o le masini fd
};

FPGA_PORT_DMA_MAP—arg o se faasinoala i se:
struct fpga_port_dma_map {
__u32 argsz; // i: sizeof(fa'atonuga fpga_port_dma_map)
__u32 fu'a; // i totonu: e tatau ona 0 __u64 user_addr; // i: fa'agaioiga fa'apitoa
tuatusi. E tatau ona fa'aoga itulau.
__u64 umi; // i: umi o fa'afanua i bytes. E tatau ona tele itulau
tele.
__u64 iova; // fafo: IO tuatusi virtual };

FPGA_PORT_DMA_UNMAP—arg o se faasinoala i se:
struct fpga_port_dma_unmap {
__u32 argsz; // i totonu: sizeof(struct fpga_port_dma_unmap)
__u32 fu'a; // i: e tatau ona 0
__u64 iova; // i: IO tuatusi virtual na toe faʻafoʻi mai e se muamua
FPGA_PORT_DMA_MAP };

• FPGA_PORT_RESET—arg e tatau ona NULL.
• FPGA_PORT_UMSG_ENABLE—e tatau ona NULL le finauga.
• FPGA_PORT_UMSG_DISABLE—o finauga e tatau ona NULL.

FPGA_PORT_UMSG_SET_MODE—arg o se faasinoala i se:

struct fpga_port_umsg_cfg {
__u32 argsz; // ile: sizeof(struct fpga_port_umsg_cfg)
__u32 fu'a; // i: e tatau ona 0
__u32 fa'ailoga_mape; // i totonu: UMsg fa'ailoga fa'ata'ita'iga fa'afanua bitmap. Fa'ailoa po'o fea UMsg's
mafai.
};

FPGA_PORT_UMSG_SET_BASE_ADDR—

• UMsg e tatau ona faʻagata aʻo leʻi tuʻuina atu lenei ioctl.
• O le fanua o le iova e tatau ona fai mo se pa puipui e lava le telē mo UMsg uma (num_umsgs * PAGE_SIZE).
  • O le pa'u ua fa'ailogaina "o lo'o fa'aaogaina" e le pulega o le aveta'avale.
  • Afai o le iova o le NULL, soʻo se itulagi muamua e le faʻailogaina o le "faʻaaogaina".
• arg o se faasinoala i se:
  struct fpga_port_umsg_base_addr {
  • u32 argsz; // ile: sizeof(struct fpga_port_umsg_base_addr)
  • u32 fu'a; // i: e tatau ona 0
  • u64 iova; // i: tuatusi faakomepiuta IO mai FPGA_PORT_DMA_MAP. };

Fa'aaliga:

• Ina ia faʻamalo mea sese o le taulaga, e tatau ona e tusia le bitmask saʻo o mea sese o loʻo i ai nei, mo example, mea sese pusi > manino
• UMsg e na'o le lagolagoina e ala i le Acceleration Stack mo le Intel Xeon Processor ma le Integrated FPGA.

sysfs Files

FME Header sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/

sysfs file	mmio fanua	ituaiga	avanoa
ports_num	fme_header.capability.num_ports	decimal int	Faitau-na'o
cache_size	fme_header.capability.cache_size	decimal int	Faitau-na'o
lomiga	fme_header.capability.fabric_verid	decimal int	Faitau-na'o
socket_id	fme_header.capability.socket_id	decimal int	Faitau-na'o
bitstream_id	fme_header.bitstream_id	hex uint64_t	Faitau-na'o
bitstream_metadata	fme_header.bitstream_md	hex uint64_t	Faitau-na'o

FME Pulega vevela sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/thermal_mgmt/

sysfs file	mmio fanua	ituaiga	avanoa
paepae1	thermal.threshold.tmp_thshold1	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
paepae2	thermal.threshold.tmp_thshold2	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
threshold_trip	thermal.threshold.therm_trip_thshold	decimal int	Faitau-na'o
threshold1_reached	thermal.threshold.thshold1_status	decimal int	Faitau-na'o
threshold2_reached	thermal.threshold.thshold2_status	decimal int	Faitau-na'o
threshold1_policy	vevela. threshold.thshold_policy	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
vevela	thermal.rdsensor_fm1.fpga_temp	decimal int	Faitau-na'o

FME Malosiaga Pulega sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/power_mgmt/

sysfs file	mmio fanua	ituaiga	avanoa
'aina	power.status.pwr_consumed	hex uint64_t	Faitau-na'o
paepae1	power.threshold.threshold1	hex uint64_t	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
paepae2	power.threshold.threshold2	hex uint64_t	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
threshold1_status	power.threshold.threshold1_status	tesisima e le'i sainia	Faitau-na'o
threshold2_status	power.threshold.threshold2_status	tesisima e le'i sainia	Faitau-na'o
rtl	power.status.fpga_latency_report	tesisima e le'i sainia	Faitau-na'o

FME Global Error sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/errors/

sysfs file	mmio fanua	ituaiga	avanoa
pcie0_errors	gerror.pcie0_err	hex uint64_t	Faitau-tusi
pcie1_errors	gerror.pcie1_err	hex uint64_t	Faitau-tusi
inject_error	gerror.ras_error_inj	hex uint64_t	Faitau-tusi

intel-fpga-dev.i/intel-fpga-fme.j/errors/fme-errors/

sysfs file	mmio fanua	ituaiga	avanoa
mea sese	gerror.fme_err	hex uint64_t	Faitau-na'o
first_error	gerror.fme_first_err.err_reg_status	hex uint64_t	Faitau-na'o
next_error	gerror.fme_next_err.err_reg_status	hex uint64_t	Faitau-na'o
manino	Fa'amama mea sese, first_error, next_error	eseese uint64_t	Tusi-na'o

Fa'aaliga:
Ina ia faʻamalo le FME mea sese, e tatau ona e tusia le bitmask saʻo o mea sese o loʻo iai nei, mo se faʻataʻitaʻigaample pusi sese > manino.

FME Vaega Toefa'atonu sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/pr/

sysfs file	mmio fanua	ituaiga	avanoa
interface_id	pr.fme_pr_intfc_id0_h, pr.fme_pre_intfc_id0_l	hex 16-paita	Faitau-na'o

FME Global Performance sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/dperf/clock

sysfs file	mmio fanua	ituaiga	avanoa
uati	gperf.clk.afu_interf_clock	hex uint64_t	Faitau-na'o

intel-fpga-dev.i/intel-fpga-fme.j/dperf/cache/ (E le aoga mo Acceleration Stack mo Intel Xeon CPU ma FPGAs)

sysfs file	mmio fanua	ituaiga	avanoa
fa'a'aisa	gperf.ch_ctl.freeze	decimal int	Faitau-tusi
faitau_hit	gperf.CACHE_RD_HIT	hex uint64_t	Faitau-na'o
faitau_misi	gperf.CACHE_RD_MISS	hex uint64_t	Faitau-na'o
write_hit	gperf.CACHE_WR_HIT	hex uint64_t	Faitau-na'o
tusi_misi	gperf.CACHE_WR_MISS	hex uint64_t	Faitau-na'o
hold_request	gperf.CACHE_HOLD_REQ	hex uint64_t	Faitau-na'o
tx_req_stall	gperf.CACHE_TX_REQ_STALL	hex uint64_t	Faitau-na'o

sysfs file	mmio fanua	ituaiga	avanoa
rx_req_stall	gperf.CACHE_RX_REQ_STALL	hex uint64_t	Faitau-na'o
data_write_port_contention	gperf.CACHE_DATA_WR_PORT_CONTEN	hex uint64_t	Faitau-na'o
tag_write_port_contention	gperf.CACHE_TAG_WR_PORT_CONTEN	hex uint64_t	Faitau-na'o

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/ (E le aoga mo Acceleration Stack mo Intel Xeon CPU ma FPGAs)

sysfs file	mmio fanua	ituaiga	avanoa
fa'a'aisa	gpperf.vtd_ctl.freeze	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/afuk/ (E le aoga mo Acceleration Stack mo Intel Xeon CPU ma FPGAs)

sysfs file	mmio fanua	ituaiga	avanoa
faitau_transaction	gperf.VTD_AFU0_MEM_RD_TRANS	hex uint64_t	Faitau-na'o
write_transaction	gperf.VTD_AFU0_MEM_WR_TRANS	hex uint64_t	Faitau-na'o
tlb_read_hit	gperf.VTD_AFU0_TLB_RD_HIT	hex uint64_t	Faitau-na'o
tlb_write_hit	gperf.VTD_AFU0_TLB_WR_HIT	hex uint64_t	Faitau-na'o

intel-fpga-dev.i/intel-fpga-fme.j/dperf/fabric/

sysfs file	mmio fanua	ituaiga	avanoa
mafai	gpperf.fab_ctl.(faagaioia)	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
fa'a'aisa	gpperf.fab_ctl.freeze	decimal int	Tagata fa'aoga: Faitau-na'o A'a: Faitau-tusi
pcie0_read	gperf.FAB_PCIE0_RD	hex uint64_t	Faitau-na'o
pcie0_tusi	gperf.FAB_PCIE0_WR	hex uint64_t	Faitau-na'o
pcie1_read	gperf.FAB_PCIE1_RD	hex uint64_t	Faitau-na'o
pcie1_tusi	gperf.FAB_PCIE1_WR	hex uint64_t	Faitau-na'o
upi_faitau	gperf.FAB_UPI_RD	hex uint64_t	Faitau-na'o
upi_tusi	gperf.FAB_UPI_WR	hex uint64_t	Faitau-na'o

intel-fpga-ev.i/intel-fpga/fme.j/dperf/fabric/portk/

sysfs file	mmio fanua	ituaiga	avanoa
pcie0_read	gperf.FAB_PCIE0_RD	hex uint64_t	Faitau-na'o
pcie0_tusi	gperf.FAB_PCIE0_WR	hex uint64_t	Faitau-na'o
pcie1_read	gperf.FAB_PCIE1_RD	hex uint64_t	Faitau-na'o
pcie1_tusi	gperf.FAB_PCIE1_WR	hex uint64_t	Faitau-na'o
upi_faitau	gperf.FAB_UPI_RD	hex uint64_t	Faitau-na'o
upi_tusi	gperf.FAB_UPI_WR	hex uint64_t	Faitau-na'o

Port Header sysfs files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	mmio fanua	ituaiga	avanoa
id	port_header.capability.port_number	decimal int	Faitau-na'o
ltr	port_header.control.latency_tolerance	decimal int	Faitau-na'o

Taulaga AFU Ulutala sysfs files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	mmio fanua	ituaiga	avanoa
afu_id	afu_header.guid	hex 16-paita	Faitau-na'o

Port Error sysfs files
intel-fpga-dev.i/intel-fpga-port.k/errors/

sysfs file	mmio fanua	ituaiga	avanoa
mea sese	perror.port_error	hex uint64_t	Faitau-na'o
first_error	perror.port_first_error	hex uint64_t	Faitau-na'o
first_malformed_req	perror.malreq	hex 16-paita	Faitau-na'o
manino	sese.(sese uma)	eseese uint64_t	Tusi-na'o

Fa'aaliga:
Ina ia faʻamalo le Port mea sese, e tatau ona e tusia le bitmask saʻo o mea sese o loʻo i ai nei, mo se faʻataʻitaʻigaample pusi sese > manino.

Toe Iloilo Tala'aga

Fa'amatalaga Fa'amaumauga	Suiga
2017.10.02	Uluai Fa'asalalauga.

OPAE Intel FPGA Linux Device Driver Architecture Guide

Pepa / Punaoa

intel OPAE FPGA Linux Fa'ata'ita'iga Aveta'avale masini [pdf] Taiala mo Tagata Fa'aoga OPAE FPGA Linux Fa'ata'avale Aveta'avale Fa'ata'ita'iga, OPAE FPGA, Fa'ata'ita'iga Fa'atonu Aveta'avale Fa'atonu Linux, Fa'ata'ita'iga Fa'ata'avale, Fa'ata'ita'iga

Fa'asinomaga

• Tusi Taiala