intel OPAE FPGA Linux Driver Architecture

OPAE Intel FPGA Linux Architecture Driver Na'urar

Direban OPAE Intel FPGA yana ba da musaya don aikace-aikacen sarari mai amfani don daidaitawa, ƙididdigewa, buɗewa, da samun dama ga masu haɓaka FPGA akan dandamali sanye take da mafita na Intel FPGA kuma yana ba da damar ayyukan sarrafa matakin tsarin kamar sake fasalin FPGA, sarrafa iko, da haɓakawa.

Hardware Architecture

Daga wurin OS na view, Kayan aikin FPGA yana bayyana azaman na'urar PCIe na yau da kullun. An tsara ƙwaƙwalwar na'urar FPGA ta amfani da ƙayyadaddun tsarin bayanai (Jerin Fasalolin Na'ura). Abubuwan da ke da goyan bayan na'urar FPGA ana fallasa su ta waɗannan tsarin bayanai, kamar yadda aka kwatanta a ƙasa a cikin adadi mai zuwa:

FPGA PCIe Na'urar

Direba yana goyan bayan PCIe SR-IOV don ƙirƙirar Ayyuka na Farko (VFs) waɗanda za a iya amfani da su don sanya masu haɓaka ɗaiɗaikun mutane zuwa injunan kama-da-wane.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aikin FPGA da samfuran semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.

Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.

Na'urar FPGA PCIe mai ƙima

Injin Gudanar da FPGA (FME)
Injin Gudanarwa na FPGA yana yin iko da kula da zafi, rahoton kuskure, sake tsarawa, rahoton aiki, da sauran ayyukan ababen more rayuwa. Kowane FPGA yana da FME guda ɗaya, wanda koyaushe ana samun dama ta hanyar Ayyukan Jiki (PF). Aikace-aikacen-sarari mai amfani na iya samun keɓancewar dama ga FME ta amfani da buɗe (), da sake shi ta amfani da kusa () azaman mai amfani mai gata (tushen).

Port
Tashar tashar jiragen ruwa tana wakiltar mu'amala tsakanin masana'anta na FPGA ("FPGA Interface Manager (FIM)") da wani yanki na sake daidaitawa wanda ke ɗauke da Ayyukan Accelerator (AF). Tashar tashar jiragen ruwa tana sarrafa sadarwa daga software zuwa na'ura mai sauri kuma tana fallasa fasali kamar sake saiti da cirewa. Na'urar PCIe na iya samun Tashoshi da yawa, kuma kowace Port za a iya fallasa su ta hanyar VF ta hanyar sanya ta ta amfani da FPGA_FME_PORT_ASSIGN ioctl akan na'urar FME.

Sashen Accelerator Aiki (AF).

• Sashin Ayyukan Haɗawa (AF) yana haɗe zuwa tashar jiragen ruwa kuma yana fallasa yanki na MMIO 256K don amfani da takamaiman rajistar sarrafawa.
• Aikace-aikacen sararin samaniya na iya samun keɓantaccen damar zuwa AFU da ke haɗe zuwa tashar jiragen ruwa ta amfani da buɗe () akan na'urar Port, da sake shi ta amfani da kusa ().
• Aikace-aikacen-sararin mai amfani kuma na iya daidaita yankuna MMIO masu haɓakawa ().

Sake fasalin ɓangarori
Kamar yadda aka ambata a sama, ana iya sake daidaita masu haɓakawa ta hanyar sake fasalin wani ɓangaren aikin Accelerator (AF) file. Dole ne a samar da Aikin Haɓakawa (AF) don ainihin FIM da yankin da aka yi niyya (Port) na FPGA; in ba haka ba, aikin sake saitawa zai gaza kuma zai yiwu ya haifar da rashin kwanciyar hankali na tsarin. Ana iya bincika wannan dacewa ta hanyar kwatanta ID na dubawa da aka lura a cikin taken AF akan ID ɗin dubawar da FME ta fallasa ta hanyar sysfs. Ana yin wannan cak ɗin ta sararin mai amfani kafin kiran sake fasalin IOCTL.

Lura:
A halin yanzu, duk wani shirin software da ke samun damar FPGA, gami da waɗanda ke gudana a cikin runduna mai ƙima, dole ne a rufe su kafin yunƙurin sake fasalin wani yanki. Matakan zasu kasance:

1. Sauke direban daga baƙo
2. Cire VF daga baƙo
3. Kashe SR-IOV
4. Yi sake fasalin wani ɓangare
5. Kunna SR-IOV
6. Toshe VF zuwa baƙo
7. Load da direba a cikin baƙo

FPGA Virtualization
Don ba da damar samun damar mai haɓakawa daga aikace-aikacen da ke gudana a cikin VM, ana buƙatar sanya tashar jiragen ruwa ta AFU zuwa VF ta amfani da matakai masu zuwa:

1. PF ta mallaki dukkan tashoshin jiragen ruwa na AFU ta tsohuwa. Duk tashar jiragen ruwa da ke buƙatar sake sanyawa zuwa VF dole ne a fara fitar da ita daga PF ta FPGA_FME_PORT_RELEASE ioctl akan na'urar FME.
2. Da zarar an saki tashoshin N daga PF, ana iya amfani da umarnin da ke ƙasa don kunna SRIOV da VFs. Kowane VF yana da tashar jiragen ruwa guda ɗaya tare da AFU. echo N> PCI_DEVICE_PATH/sriov_numvfs
3. Shiga cikin VFs zuwa VMs.
4. Ana samun damar AFU ƙarƙashin VF daga aikace-aikace a cikin VM (ta amfani da direba iri ɗaya a cikin VF).

Lura:
Ba za a iya sanya FME zuwa VF ba, don haka PR da sauran ayyukan gudanarwa suna samuwa ta hanyar PF kawai.

Kungiyar Direbobi

Direba Module na PCIe

Kungiyar Direbobi

Na'urorin FPGA suna bayyana azaman na'urorin PCIe na yau da kullun; don haka, direban na'urar FPGA PCIe (intel-FPGA-PCI.ko) koyaushe ana loda shi da farko da zarar an gano FPGA PCIe PF ko VF. Wannan direban yana taka rawar gani a cikin gine-ginen direba. Yana:

• Yana ƙirƙira na'urar kwantena ta FPGA azaman iyayen na'urorin fasalin.
• Yana tafiya ta cikin Lissafin Siffofin Na'ura, wanda aka aiwatar a cikin ƙwaƙwalwar ajiyar na'urar PCIe BAR, don gano na'urori masu mahimmanci da ƙananan fasalulluka da ƙirƙirar na'urorin dandamali a gare su a ƙarƙashin na'urar kwantena.
• Yana goyan bayan SR-IOV.
• Yana gabatar da fasalin kayan aikin na'ura, wanda ke ɓoye ayyuka don ƙananan siffofi kuma yana fallasa ayyukan gama gari don fasalin direbobin na'ura.

Ayyukan Direba Module na PCIe

• Ya ƙunshi gano PCIe, ƙididdigar na'ura, da gano fasalin.
• Ƙirƙirar kundayen adireshi na sysfs don na'urar iyaye, Injin Gudanar da FPGA (FME), da Port.
• Yana ƙirƙira misalan direban dandamali, yana haifar da kernel Linux don ɗaukar nau'ikan direbobin dandamali daban-daban.

FME Platform Module Na'urar Direba

• Gudanar da wutar lantarki da thermal, rahoton kuskure, rahoton aiki, da sauran ayyukan samar da ababen more rayuwa. Kuna iya samun damar waɗannan ayyukan ta hanyar mu'amalar sysfs da direban FME ya fallasa.
• Sake fasalin ɓangarori. Direban FME yana yin rijistar Manajan FPGA yayin ƙaddamar da ƙaramin fasali na PR; da zarar ya karɓi FPGA_FME_PORT_PR ioctl daga gare ku, yana kiran aikin gama gari daga Manajan FPGA don kammala sake fasalin ɓangaren bitstream zuwa tashar da aka bayar.
• Gudanar da tashar jiragen ruwa don haɓakawa. Direban FME ya gabatar da ioctls guda biyu, FPGA_FME_PORT_RELEASE, wanda ke sakin tashar da aka bayar daga PF; da FPGA_FME_PORT_ASSIGN, wanda ke ba da tashar jiragen ruwa zuwa PF. Da zarar an saki Port daga PF, za a iya sanya shi zuwa VF ta hanyar SR-IOV musaya wanda direban PCIe ya bayar. Don ƙarin bayani, koma zuwa "FPGA Virtualization".

Ayyukan Direba Module Platform FME

• Yana ƙirƙira kumburin na'urar harafin FME.
• Yana ƙirƙira FME sysfs files kuma yana aiwatar da FME sysfs file masu shiga.
• Yana aiwatar da ƙananan direbobi masu zaman kansu na FME.
• FME masu zaman kansu sub-direba:
  • Babban darajar FME
  • Gudanar da thermal
  • Gudanar da Wuta
  • Kuskuren Duniya
  • Sake fasalin ɓangarori
  • Ayyukan Duniya

Direba Module Port Platform
Kamar direban FME, direban FPGA Port (da AFU) (intel-fpga-afu. ko) ana bincikensa da zarar an ƙirƙiri na'urar dandamali ta Port. Babban aikin wannan tsarin shine samar da hanyar sadarwa don aikace-aikacen sarari mai amfani don samun dama ga masu haɓakawa guda ɗaya, gami da ainihin ikon sake saiti akan tashar jiragen ruwa, fitarwar yanki na AFU MMIO, sabis ɗin taswirar taswirar DMA, sanarwar UMsg(1), da ayyukan debo na nesa (XNUMX) gani a sama).

Ana goyan bayan UMsg ta hanyar Acceleration Stack don Intel Xeon® Processor tare da Integrated FPGA.

Ayyukan Direba Module Platform Port

• Yana ƙirƙira kumburin na'urar halayen Port.
• Yana ƙirƙirar Port sysfs files kuma yana aiwatar da Port sysfs file masu shiga.
• Yana aiwatar da ƙananan direbobi masu zaman kansu na Port.
• Matsalolin tashar tashar jiragen ruwa masu zaman kansu:
  • Port Header
  • AFU
  • Kuskuren Port
  • UMsg(2)
  • Taɓa sigina

Ƙididdigar Na'urar FPGA Application
Wannan sashe yana gabatar da yadda aikace-aikace ke ƙididdige na'urar FPGA daga matsayi na sysfs a ƙarƙashin /sys/class/fpga. A cikin exampA ƙasa, an shigar da na'urori biyu na Intel FPGA a cikin rundunar. Kowace na'urar FPGA tana da FME ɗaya da Tashoshi biyu (AFUs). Ga kowace na'urar FPGA, an ƙirƙiri kundin adireshin na'ura a ƙarƙashin /sys/class/fpga:

/sys/class/fpga/intel-fpga-dev.0
/sys/class/fpga/intel-fpga-dev.1

Kowane kumburi yana da FME ɗaya da Tashoshi biyu (AFUs) azaman na'urorin yara:
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-fme.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.2
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.3

Gabaɗaya, abubuwan haɗin FME/Port sysfs ana kiran su kamar haka:
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-fme.j/
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-port.k/

tare da na ƙidaya duk na'urorin kwantena a jere, j a jere na ƙididdige FME's da kuma lambobi a jere duk Ports.

Ana iya amfani da nodes ɗin na'urar da aka yi amfani da su don ioctl() da mmap() ta:
/dev/intel-fpga-fme.j
/dev/intel-fpga-port.k

Ƙididdigar Direba na PCIe
Wannan rukunin yana ba da haskeview na kwararar lambar don ƙididdigar na'urar da intel-fpga-pci.ko ke yi. Ana haskaka mahimman tsarin bayanai da ayyuka. Wannan sashe yana da kyau a bi lokacin viewtare da lambar tushe mai rakiyar (pcie.c).

Tsarin Bayanan Ƙididdigar

enum fpga_id_type {
PARENT_ID,
FME_ID,
PORT_ID,
FPGA_ID_MAX
};
daidaitaccen tsari idr fpga_ids[FPGA_ID_MAX];
tsarin fpga_chardev_info {
const char * suna;
dev_t devt;
};
tsarin fpga_chardev_info fpga_chrdevs[] = {
{.suna = FPGA_FEATURE_DEV_FME},
{ .suna = FPGA_FEATURE_DEV_PORT },
};
ajin tsayayyen tsari *fpga_class;
Tsayayyen tsari pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_DCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_DCP),},
{0,}
};
Tsayayyen tsari pci_driver cci_pci_driver = {
.name = DRV_NAME,
.id_table = cci_pcie_id_tbl,
.bincike = cci_pci_probe,
.cire = cci_pci_remove,
.sriov_configure = cci_pci_sriov_configure
};
tsarin cci_drvdata {
int device_id;
na'urar tsari *fme_dev;
tsarin mutex kulle;
tsarin list_head port_dev_list;
int saki_port_num;
tsarin list_head yankuna;
};
struct build_feature_devs_info {
tsarin pci_dev * pdev;
banza __iomem *ioaddr;
banza __iomem * ioend;
int current_bar;
banza __iomem *pfme_hdr;
na'urar tsari *parent_dev;
tsarin dandamali_na'urar * fasalin_dev;
};

Gudun Ƙididdigar

• ccidrv_init()
  • Fara fpga_ids ta amfani da idr_init().
  • Fara fpga_chrdevs[i].devt ta amfani da alloc_chrdev_region().
  • Fara fpga_class ta amfani da class_create().
  • pci_register_driver(&cci_pci_driver);
• cci_pci_probe()
  • Kunna na'urar PCI, buƙatar samun dama ga yankunanta, saita yanayin ƙirar PCI, kuma saita DMA.
• cci_pci_create_feature_devs() build_info_alloc_and_init()
  • Sanya tsarin gini_feature_devs_info, fara shi.
    .parent_dev an saita zuwa directory na sysfs iyaye (intel-fpga-dev.id) wanda ya ƙunshi kundayen adireshi na FME da Port sysfs.
• lissafin_feature_list()
  • Tafiya Jerin Fasalolin Na'urar BAR0 don gano FME, tashar jiragen ruwa, da abubuwan sirrinsu.
• parse_feature() fassarar_feature_afus() parse_feature_fme()
  • Lokacin da aka ci karo da FME:
• gina_info_create_dev()
  • Keɓance na'urar dandamali don FME, tana adanawa a cikin build_feature_devs_info.feature_dev.
  • an fara fasalin_dev.id zuwa sakamakon idr_alloc(fpga_ids[FME_ID],
  • feature_dev.parent an saita zuwa build_feature_devs_info.parent_dev.
  • Rarraba tsararrun kayan aiki a cikin feature_dev.resource.
• Keɓance tsarin fasalin_platform_data, fara shi, sannan adana mai nuni a cikin feature_dev.dev.platform_data
  • Create_feature_imtance() build_info_add_sub_feature()
  • Fara fasalin_dev.resource[FME_FEATURE_ID_HEADER].
  • fasali_dandamali_data_kara()
  • Fara fasalin_platform_data.features[FME_FEATURE_ID_HEADER], komai sai .fops.
• parse_feature() parse_feature_afus() parse_feature_port()
  • Lokacin da aka ci karo da tashar jiragen ruwa:
• gina_info_create_dev()
  • Keɓance na'urar dandamali don tashar jiragen ruwa, tana adanawa a cikin build_feature_devs_info.feature_dev.
  • feature_dev.id an fara shi zuwa sakamakon idr_alloc(fpga_ids[PORT_ID]),
  • feature_dev.parent an saita zuwa build_feature_devs_info.parent_dev.
  • Rarraba tsararrun kayan aiki a cikin feature_dev.resource.
  • Keɓance tsarin fasalin_platform_data, fara shi, sannan adana mai nuni a cikin feature_dev.dev.platform_data
• gina_info_commit_dev()
  • Ƙara tsarin fasalin_platform_data.node don tashar jiragen ruwa zuwa jerin tashoshin jiragen ruwa da ke cikin tsarin cci_drvdata.port_dev_list.
• Create_feature_imtance() build_info_add_sub_feature()
  • Fara fasalin_dev.resource[PORT_FEATURE_ID_HEADER].
• fasali_dandamali_data_kara()
  • Fara fasalin_platform_data.features[PORT_FEATURE_ID_HEADER], komai sai .fops.
• parse_feature() fassarar_feature_afus()
  • Lokacin da aka ci karo da AFU:
• Create_feature_imtance() build_info_add_sub_feature()
  • Fara fasalin_dev.resource[PORT_FEATURE_ID_UAFU].
• fasali_dandamali_data_kara()
  • Fara fasalin_platform_data.features[PORT_FEATURE_ID_UAFU], komai sai .fops.
• parse_feature() parse_feature_private() parse_feature_fme_private()
  • Lokacin da aka ci karo da fasalin sirri na FME:
• Create_feature_imtance() build_info_add_sub_feature()
  • Fara fasalin_dev.resource[id].
• fasali_dandamali_data_kara()
  • Fara fasalin_platform_data.features[id], komai sai .fops.
• parse_feature() parse_feature_private() parse_feature_port_private()
• Lokacin da aka ci karo da fasalin keɓaɓɓen tashar tashar jiragen ruwa: * ƙirƙirar_feature_instance() build_info_add_sub_feature() * Fara fasalin_dev.resource[id]. * feature_platform_data_add() Fara fasalin_platform_data.features[id], komai sai .fops.
• parse_ports_from_fme()
  • Idan an ɗora wa direba akan Ayyukan Jiki (PF), to:
• Gudanar da gudanawar parse_feature_list() akan kowace tashar jiragen ruwa da aka kwatanta a cikin taken FME.
• Yi amfani da BAR da aka ambata a kowace tashar tashar jiragen ruwa a cikin taken.

FME Platform Na'urar Farawa
Wannan rukunin yana ba da haskeview na kwararar lambar don fara na'urar FME da intel-fpga-fme.ko ke yi. Babban tsarin bayanai da ayyuka suna ɗaukaka. Wannan sashe yana da kyau a bi lokacin viewtare da lambar tushe mai rakiyar (fme-main.c).

Tsarin Bayanan Na'urar Platform FME

tsarin fasali_ops {
int (* init) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
int (* uinit) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
dogon (* ioctl) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasali,
int cmd mara izini, dogon arg mara sa hannu);
int (* gwaji) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
};
fasalin tsari {
const char * suna;
int albarkatun_index;
banza __iomem *ioaddr;
tsarin fasalin_ops * ops;
};
struct feature_platform_data {
struct list_head node;
tsarin mutex kulle;
dogon dev_status mara sa hannu;
tsarin CDev cdev;
tsarin dandamali_na'urar * dev;
unsigned int disable_count;
banza *mai zaman kansa;
int num;
int (* config_port) (tsarin dandamali_na'urar *, u32, bool);
tsarin dandamali_na'urar * (*fpga_for_kowanne tashar tashar jiragen ruwa) (na'urar tsarin dandamali *,
fanko *, int (*match) (tsarin dandamali_na'urar *, wofi *)); tsari
fasalin fasali[0];
};
struct perf_object {
id;
const struct attribute_group **attr_groups;
na'urar tsari *fme_dev;
struct list_head node;
struct list_head yara;
tsarin kobject kobj;
};
tsarin fpga_fme {
u8 port_id;
u64 pr_err;
na'urar tsari * dev_err;
struct perf_object * perf_dev;
struct feature_platform_data *pdata;
};

FME Platform Ƙaddamarwar Na'urar Yawo

Farawar FME

• fme_probe() fme_dev_init()
  • Fara tsarin fpga_fme kuma adana shi a cikin fasalin_platform_data.private filin.
• fme_probe() fpga_dev_feature_init() fasalin_instance_init()
  • Ajiye tsarin fasalin_ops cikin fasalin_platform_data.features ga kowane fasalin da ya cika jama'a.
  • Kira aikin gwajin, idan akwai, daga tsarin.
  • Kira aikin init daga tsarin.
• fme_probe() fpga_register_dev_ops()
  • Ƙirƙirar kumburin na'urar harafin FME, yin rijistar tsari file_aiki.

Ƙaddamar da Na'urar Platform Port
Wannan rukunin yana ba da haskeview na kwararar lambar don farawa na'urar tashar jiragen ruwa wanda intel-fpga-afu.ko yayi. Ana haskaka mahimman tsarin bayanai da ayyuka. Wannan sashe yana da kyau a bi lokacin viewlambar tushe mai rakiyar (afu.c).

Tsarin Bayanan Na'urar Platform Port

tsarin fasali_ops {
int (* init) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
int (* uinit) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
dogon (* ioctl) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasali,
int cmd mara izini, dogon arg mara sa hannu);
int (* gwaji) (tsarin dandamali_na'urar * pdev, fasalin fasalin * fasalin);
};
fasalin tsari {
const char * suna;
int albarkatun_index;
banza __iomem *ioaddr;
tsarin fasalin_ops * ops;
};
struct feature_platform_data {
struct list_head node;
tsarin mutex kulle;
dogon dev_status mara sa hannu;
tsarin CDev cdev;
tsarin dandamali_na'urar * dev;
unsigned int disable_count;
banza *mai zaman kansa;
int num;
int (* config_port) (tsarin dandamali_na'urar *, u32, bool);
tsarin dandamali_na'urar * (*fpga_for_kowanne tashar tashar jiragen ruwa) (na'urar tsarin dandamali *,
fanko *, int (*match) (tsarin dandamali_na'urar *, wofi *));
fasalin fasalin tsarin[0];
};
tsarin fpga_afu_region {
u32 index;
u32 tutoci;
u64 girma;
u64 biya;
u64 fy;
struct list_head node;
};
tsarin fpga_afu_dma_region {
u64 mai amfani_addr;
u64 tsayi;
uwa 64;
shafin tsari ** shafuka;
tsarin kumburin rb_node;
amfani mai amfani;
};
tsarin fpga_afu {
u64 yankin_cur_offset;
int num_yankuna;
u8 num_umsgs;
tsarin list_head yankuna;
tsarin rb_root dma_regions;
struct feature_platform_data *pdata;
};

Ƙaddamar da Na'urar Port Platform Flow

Gudun Ƙaddamar da tashar jiragen ruwa

• afu_probe() afu_dev_init()
  • Fara tsarin fpga_afu kuma adana shi a cikin fasalin_platform_data.private filin.
• afu_probe() fpga_dev_feature_init() fasalin_instance_init()
  • Ajiye tsarin fasalin_ops cikin fasalin_platform_data.features ga kowane fasalin da ya cika jama'a.
  • Kira aikin gwajin, idan akwai, daga tsarin.
  • Kira aikin init daga tsarin.
• afu_probe() fpga_register_dev_ops()
  • Ƙirƙirar kumburin na'urar halayen Port, yin rijistar tsari file_aiki.

Farashin FME IOCTL
IOCTLs waɗanda ake kira a buɗe file mai siffanta don /dev/intel-fpga-fme.j FPGA_GET_API_VERSION — mayar da sigar yanzu azaman lamba, farawa daga 0.

FPGA_CHECK_EXTENSION — ba a tallafawa a halin yanzu.

FPGA_FME_PORT_RELEASE—arg shine mai nuni ga:

tsarin fpga_fme_port_release {
__u32 argsz; // a cikin: sizeof (tsarin fpga_fme_port_release)
Tutoci __u32; // in: dole ne ya zama 0
__u32 tashar jiragen ruwa; // a: ID na tashar jiragen ruwa (daga 0) don saki.
};

FPGA_FME_PORT_ASSIGN—arg mai nuni ne ga:

tsarin fpga_fme_port_assign {
__u32 argsz; // a cikin: sizeof (tsarin fpga_fme_port_assign)
Tutoci __u32; // in: dole ne ya zama 0
__u32 tashar jiragen ruwa; // a: ID na tashar jiragen ruwa (daga 0) don sanyawa. (dole ne
wanda FPGA_FME_PORT_RELEASE ya fitar a baya)
};

FPGA_FME_PORT_PR—arg mai nuni ne ga:

tsarin fpga_fme_port_pr {
__u32 argsz; // a cikin: sizeof (tsarin fpga_fme_port_pr)
Tutoci __u32; // in: dole ne ya zama 0
__u32 tashar jiragen ruwa; // a: tashar tashar jiragen ruwa (daga 0)
Girman __u32; // in: girman buffer bitstream a cikin bytes. Dole ne ya zama 4-byte
daidaitacce.
__u64 adireshin buffer_; // in: adreshin tsari na buffer bitstream
__u64 matsayi; // fita: matsayin kuskure (bitmask)
};

Port IOCTLs
IOCTLs waɗanda ake kira a buɗe file mai siffanta don /dev/intel-fpga-port.k FPGA_GET_API_VERSION — mayar da sigar yanzu a matsayin lamba, farawa daga 0. FPGA_CHECK_EXTENSION — ba a tallafawa a halin yanzu.

FPGA_PORT_GET_INFO—arg mai nuni ne ga:

tsarin fpga_port_info {
__u32 argsz; // a cikin: sizeof (tsarin fpga_port_info)
Tutoci __u32; // fita: dawo da 0
__u32 adadi_yankuna; // fita: adadin yankunan MMIO, 2 (1 don AFU da 1 don
STP)
__u32 lamba_umsgs; // fita: adadin UMsg's da kayan aikin ke goyan bayan
};

FPGA_PORT_GET_REGION_INFO—arg mai nuni ne ga:

tsarin fpga_port_region_info {
__u32 argsz; // a cikin: sizeof (tsarin fpga_port_region_info)
Tutoci __u32; // fita: (bitmask) {FPGA_REGION_READ, FPGA_REGION_WRITE,
FPGA_REGION_MMAP }
Fihirisar __u32; // a cikin: FPGA_PORT_INDEX_UAFU ko FPGA_PORT_INDEX_STP
__u32 abin rufewa; // in: dole ne ya zama 0
girman __u64; // fita: girman yankin MMIO a cikin bytes
__u64 biya diyya; // fita: kashewar yankin MMIO daga farkon na'urar fd
};

FPGA_PORT_DMA_MAP—arg mai nuni ne ga:
tsarin fpga_port_dma_map {
__u32 argsz; // in: sizeof(tsarin fpga_port_dma_map)
Tutoci __u32; // a: dole ne ya zama 0 __u64 user_addr; // in: aiwatar da kama-da-wane
adireshin Dole ne a daidaita shafi.
Tsawon __u64; // a: tsawon taswira a cikin bytes. Dole ne ya zama shafi mai yawa
girman.
__u64 iova; // fita: IO kama-da-wane adireshin };

FPGA_PORT_DMA_UNMAP—arg shine mai nuni ga:
tsarin fpga_port_dma_unmap {
__u32 argsz; // in: sizeof(tsarin fpga_port_dma_unmap)
Tutoci __u32; // in: dole ne ya zama 0
__u64 iova; // in: IO kama-da-wane adireshin da aka dawo da shi ta baya
FPGA_PORT_DMA_MAP };

• FPGA_PORT_RESET-arg dole ne ya zama NULL.
• FPGA_PORT_UMSG_ENABLE—arg dole ne ya zama NULL.
• FPGA_PORT_UMSG_DISABLE—args dole ne su zama NULL.

FPGA_PORT_UMSG_SET_MODE—arg shine mai nuni ga:

tsarin fpga_port_umsg_cfg {
__u32 argsz; // a cikin: sizeof (tsarin fpga_port_umsg_cfg)
Tutoci __u32; // in: dole ne ya zama 0
__u32 alamar_bitmap; // in: UMsg yanayin nunin bitmap. Yana nuna waɗanne UMsg's ne
kunna.
};

FPGA_PORT_UMSG_SET_BASE_ADDR-

• Dole ne a kashe UMsg kafin fitar da wannan ioctl.
• Filin iova dole ne ya kasance don ma'auni mai girma isa ga duk UMsg's (num_umsgs * PAGE_SIZE).
  • Ana yiwa maƙerin alamar alama a matsayin “aiki” ta hanyar sarrafa buffer ɗin direba.
  • Idan iova NULL ne, duk wani yanki da ya gabata ba shi da alama a matsayin “aiki”.
• arg is a pointer to a:
  tsarin fpga_port_umsg_base_addr {
  • u32 args; // a cikin: sizeof (tsarin fpga_port_umsg_base_addr)
  • u32 tutoci; // in: dole ne ya zama 0
  • uwa 64; // a cikin: adireshin kama-da-wane na IO daga FPGA_PORT_DMA_MAP. };

Lura:

• Don share kurakuran tashar jiragen ruwa, dole ne ka rubuta ainihin bitmask na kurakurai na yanzu, misaliample, kurakurai cat > share
• Ana goyan bayan UMsg kawai ta hanyar Acceleration Stack don Intel Xeon Processor tare da Integrated FPGA.

sysfs Files

FME Header sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/

sysfs file	filin mm	nau'in	shiga
tashar jiragen ruwa_num	fme_header.capability.num_ports	decimal int	Karanta-kawai
cache_size	fme_header.capability.cache_size	decimal int	Karanta-kawai
sigar	fme_header.capability.fabric_verid	decimal int	Karanta-kawai
socket_id	fme_header.capability.socket_id	decimal int	Karanta-kawai
bitstream_id	fme_header.bitstream_id	hex uint64_t	Karanta-kawai
bitstream_metadata	fme_header.bitstream_md	hex uint64_t	Karanta-kawai

FME Thermal Management Sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/thermal_mgmt/

sysfs file	filin mm	nau'in	shiga
kofa 1	thermal.threshold.tmp_thshold1	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
kofa 2	thermal.threshold.tmp_thshold2	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
bakin_tafiya	thermal.threshold.them_tafiya	decimal int	Karanta-kawai
bakin kofa1_ya isa	thermal.kofa.matsayi1_status	decimal int	Karanta-kawai
bakin kofa2_ya isa	thermal.kofa.matsayi2_status	decimal int	Karanta-kawai
ƙofa1_siyasa	thermal. madaidaicin.manufar_manufa	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
zafin jiki	thermal.rdsensor_fm1.fpga_temp	decimal int	Karanta-kawai

FME Power Management Sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/power_mgmt/

sysfs file	filin mm	nau'in	shiga
cinyewa	iko.status.pwr_cinyewa	hex uint64_t	Karanta-kawai
kofa 1	iko.kofa.kofa1	hex uint64_t	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
kofa 2	iko.kofa.kofa2	hex uint64_t	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
matakin 1_status	iko.kofa.mataki1_status	decimal unsigned	Karanta-kawai
matakin 2_status	iko.kofa.mataki2_status	decimal unsigned	Karanta-kawai
rtl	power.status.fpga_latency_report	decimal unsigned	Karanta-kawai

Kuskuren Duniya na FME sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/errors/

sysfs file	filin mm	nau'in	shiga
pcie0_kurakurai	gerror.pcie0_err	hex uint64_t	Mai karantawa
pcie1_kurakurai	gerror.pcie1_err	hex uint64_t	Mai karantawa
allura_kuskure	gerror.ras_error_inj	hex uint64_t	Mai karantawa

intel-fpga-dev.i/intel-fpga-fme.j/errors/fme-errors/

sysfs file	filin mm	nau'in	shiga
kurakurai	gerror.fme_err	hex uint64_t	Karanta-kawai
farko_kuskure	gerror.fme_first_err.err_reg_status	hex uint64_t	Karanta-kawai
next_kuskure	gerror.fme_next_err.err_reg_status	hex uint64_t	Karanta-kawai
bayyananne	Yana share kurakurai, first_error, next_error	daban-daban uint64_t	Rubuta-kawai

Lura:
Don share kurakuran FME, dole ne ka rubuta ainihin bitmask na kurakurai na yanzu, misaliample cat kurakurai> share.

FME Sake fasalin Sake fasalin sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/pr/

sysfs file	filin mm	nau'in	shiga
interface_id	pr.fme_pr_intfc_id0_h, pr.fme_pre_intfc_id0_l	hex 16-byte	Karanta-kawai

FME Global Performance sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/dperf/clock

sysfs file	filin mm	nau'in	shiga
agogo	gperf.clk.afu_interf_clock	hex uint64_t	Karanta-kawai

intel-fpga-dev.i/intel-fpga-fme.j/dperf/cache/ (Ba shi da inganci don Haɗawa ga Intel Xeon CPU tare da FPGAs)

sysfs file	filin mm	nau'in	shiga
daskare	gperf.ch_ctl.freeze	decimal int	Mai karantawa
karanta_buga	gperf.CACHE_RD_HIT	hex uint64_t	Karanta-kawai
karanta_miss	gperf.CACHE_RD_MISS	hex uint64_t	Karanta-kawai
rubuta_buga	gperf.CACHE_WR_HIT	hex uint64_t	Karanta-kawai
rubuta_miss	gperf.CACHE_WR_MISS	hex uint64_t	Karanta-kawai
hold_request	gperf.CACHE_HOLD_REQ	hex uint64_t	Karanta-kawai
tx_req_stall	gperf.CACHE_TX_REQ_STALL	hex uint64_t	Karanta-kawai

sysfs file	filin mm	nau'in	shiga
rx_req_stall	gperf.CACHE_RX_REQ_STALL	hex uint64_t	Karanta-kawai
bayanai_write_port_concontent	gperf.CACHE_DATA_WR_PORT_CONTEN	hex uint64_t	Karanta-kawai
tag_rubutu_tashar_content	gperf.CACHE_TAG_WR_PORT_CONTEN	hex uint64_t	Karanta-kawai

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/ (Ba shi da inganci don Acceleration Stack don Intel Xeon CPU tare da FPGAs)

sysfs file	filin mm	nau'in	shiga
daskare	gperf.vtd_ctl.freeze	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/afuk/ (Ba shi da inganci don Haɗawa Stack don Intel Xeon CPU tare da FPGAs)

sysfs file	filin mm	nau'in	shiga
karanta_ma'amala	gperf.VTD_AFU0_MEM_RD_TRANS	hex uint64_t	Karanta-kawai
rubuta_ma'amala	gperf.VTD_AFU0_MEM_WR_TRANS	hex uint64_t	Karanta-kawai
tlb_karanta_hit	gperf.VTD_AFU0_TLB_RD_HIT	hex uint64_t	Karanta-kawai
tlb_rubuta_hit	gperf.VTD_AFU0_TLB_WR_HIT	hex uint64_t	Karanta-kawai

intel-fpga-dev.i/intel-fpga-fme.j/dperf/fabric/

sysfs file	filin mm	nau'in	shiga
ba da damar	gperf.fab_ctl.(an kunna)	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
daskare	gperf.fab_ctl.freeze	decimal int	Mai amfani: Tushen Karanta-kawai: Karanta-rubutu
pcie0_karanta	gperf.FAB_PCIE0_RD	hex uint64_t	Karanta-kawai
pcie0_rubuta	gperf.FAB_PCIE0_WR	hex uint64_t	Karanta-kawai
pcie1_karanta	gperf.FAB_PCIE1_RD	hex uint64_t	Karanta-kawai
pcie1_rubuta	gperf.FAB_PCIE1_WR	hex uint64_t	Karanta-kawai
upi_karanta	gperf.FAB_UPI_RD	hex uint64_t	Karanta-kawai
rubuta_upi	gperf.FAB_UPI_WR	hex uint64_t	Karanta-kawai

intel-fpga-ev.i/intel-fpga/fme.j/dperf/fabric/portk/

sysfs file	filin mm	nau'in	shiga
pcie0_karanta	gperf.FAB_PCIE0_RD	hex uint64_t	Karanta-kawai
pcie0_rubuta	gperf.FAB_PCIE0_WR	hex uint64_t	Karanta-kawai
pcie1_karanta	gperf.FAB_PCIE1_RD	hex uint64_t	Karanta-kawai
pcie1_rubuta	gperf.FAB_PCIE1_WR	hex uint64_t	Karanta-kawai
upi_karanta	gperf.FAB_UPI_RD	hex uint64_t	Karanta-kawai
rubuta_upi	gperf.FAB_UPI_WR	hex uint64_t	Karanta-kawai

Port Header sysfs files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	filin mm	nau'in	shiga
id	port_header.capability.port_number	decimal int	Karanta-kawai
ltr	port_header.control.latency_tolerance	decimal int	Karanta-kawai

Port AFU Header sysfs files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	filin mm	nau'in	shiga
afu_id	afu_header.guid	hex 16-byte	Karanta-kawai

Kuskuren Port sysfs files
intel-fpga-dev.i/intel-fpga-port.k/errors/

sysfs file	filin mm	nau'in	shiga
kurakurai	perror.port_error	hex uint64_t	Karanta-kawai
farko_kuskure	perror.port_first_error	hex uint64_t	Karanta-kawai
first_malformed_req	ta'addanci.malreq	hex 16-byte	Karanta-kawai
bayyananne	ta'addanci.(duk kurakurai)	daban-daban uint64_t	Rubuta-kawai

Lura:
Don share kurakuran tashar jiragen ruwa, dole ne ka rubuta ainihin bitmask na kurakurai na yanzu, misaliample cat kurakurai> share.

Tarihin Bita

Sigar Takardu	Canje-canje
2017.10.02	Sakin Farko.

OPAE Intel FPGA Linux Jagorar Gine-ginen Direba

Takardu / Albarkatu

intel OPAE FPGA Linux Driver Architecture [pdf] Jagorar mai amfani Gine-ginen Direba na Linux OPAE FPGA, OPAE FPGA, Gine-ginen Direba na Na'urar Linux, Gine-ginen Direba, Gine-gine

Magana

• Manual mai amfani