intel OPAE FPGA Linux Mea Hoʻokele Hoʻokele Hoʻokele

OPAE Intel FPGA Linux Mea Hoʻokele Hoʻokele Hoʻokele

Hāʻawi ka mea hoʻokele OPAE Intel FPGA i nā loulou no nā noi hoʻohana-space e hoʻonohonoho, helu, wehe, a komo i nā accelerators FPGA ma nā paepae i hoʻolako ʻia me nā hāmeʻa Intel FPGA a hiki i nā hana hoʻokele pae ʻōnaehana e like me ka hoʻonohonoho hou ʻana o FPGA, ka mana mana, a me ka virtualization.

Lako Paahana

Mai ka ʻaoʻao o ka OS view, ʻike ʻia ka hāmeʻa FPGA ma ke ʻano he polokalamu PCIe maʻamau. Hoʻonohonoho ʻia ka hoʻomanaʻo ʻana o ka hāmeʻa FPGA me ka hoʻohana ʻana i kahi ʻano ʻikepili i koho mua ʻia (Device Feature List). Hōʻike ʻia nā hiʻohiʻona i kākoʻo ʻia e ka hāmeʻa FPGA ma o kēia mau hana ʻikepili, e like me ka mea i hōʻike ʻia ma lalo nei ma kēia kiʻi:

Mea hana FPGA PCIe

Kākoʻo ka mea hoʻokele iā PCIe SR-IOV e hana i nā Hana Kūikawā (VFs) i hiki ke hoʻohana ʻia no ka hāʻawi ʻana i nā mea hoʻokele hoʻokahi i nā mīkini virtual.

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka ʻike. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku ʻo Intel e loaʻa i ka mana hou o nā kikoʻī hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā ​​​​lawelawe.

Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.

Mea Hana FPGA PCIe

FPGA Management Engine (FME)
Hana ka FPGA Management Engine i ka mana a me ka hoʻokele wela, ka hōʻike hewa, ka hoʻonohonoho hou ʻana, ka hōʻike ʻana i ka hana, a me nā hana ʻoihana ʻē aʻe. Loaʻa i kēlā me kēia FPGA hoʻokahi FME, i loaʻa mau ma o ka Physical Function (PF). Hiki i nā polokalamu hoʻohana-space ke loaʻa ke komo kūʻokoʻa i ka FME me ka hoʻohana ʻana i ka open(), a hoʻokuʻu iā ia me ka hoʻohana ʻana i close() ma ke ʻano he mea hoʻohana pono (root).

Awa
Hōʻike ka Port i ka pilina ma waena o ka lole FPGA static (ka "FPGA Interface Manager (FIM)") a me kahi ʻāpana hiki ke hoʻonohonoho hou ʻia me kahi Accelerator Function (AF). Mālama ka Port i ke kamaʻilio ʻana mai ka polokalamu a hiki i ka mea holo wikiwiki a hōʻike i nā hiʻohiʻona e like me ka hoʻonohonoho hou a me ka debug. Loaʻa paha i kekahi mea PCIe kekahi mau Awa, a hiki ke hōʻike ʻia kēlā me kēia Port ma o ka VF ma o ka hāʻawi ʻana iā ia me ka hoʻohana ʻana i ka FPGA_FME_PORT_ASSIGN ioctl ma ka hāmeʻa FME.

Hui Hoʻoikaika (AF).

• Hoʻopili ʻia kahi ʻāpana Accelerator Function (AF) i kahi Port a hōʻike i kahi ʻāpana 256K MMIO e hoʻohana ʻia no nā papa inoa hoʻokele kikoʻī.
• Hiki i nā polokalamu hoʻohana-space ke loaʻa i kahi AFU i hoʻopili ʻia i kahi Port ma o ka hoʻohana ʻana i ka open() ma ka hāmeʻa Port, a hoʻokuʻu iā ia me ka hoʻohana ʻana i kahi kokoke ().
• Hiki i nā mea hoʻohana-space applications mmap() accelerator MMIO māhele.

Hoʻonohonoho hou hapa
E like me ka mea i ʻōlelo ʻia ma luna nei, hiki ke hoʻonohonoho hou ʻia nā accelerators ma o ka hoʻonohonoho hou ʻana i kahi hapa o kahi Accelerator Function (AF) file. Pono i hana ʻia ka Accelerator Function (AF) no ka FIM pololei a me ka ʻāpana static i kuhikuhi ʻia (Port) o ka FPGA; inā ʻaʻole, e hāʻule ka hana hoʻonohonoho hou ʻana a hiki paha ke kumu i ka paʻa ʻole o ka ʻōnaehana. Hiki ke nānā ʻia kēia kūlike ma ka hoʻohālikelike ʻana i ka ID interface i ʻike ʻia ma ke poʻo AF me ka ID interface i hōʻike ʻia e ka FME ma o sysfs. Hana ʻia kēia māka e ka mea hoʻohana ma mua o ke kāhea ʻana i ka reconfiguration IOCTL.

Nānā:
I kēia manawa, pono e pani ʻia kekahi polokalamu lako polokalamu e komo ana i ka FPGA, me nā mea e holo ana i loko o kahi host virtualized ma mua o ka hoʻāʻo ʻana i kahi hoʻonohonoho hou ʻana. ʻO nā ʻanuʻu:

1. Wehe i ka mea hoʻokele mai ka malihini
2. Wehe i ka VF mai ka malihini
3. Hoʻopau iā SR-IOV
4. Hana i ka hoʻonohonoho hou ʻana
5. Hiki iā SR-IOV
6. Hoʻopili i ka VF i ka malihini
7. Hoʻouka i ka mea hoʻokele i ka malihini

FPGA Virtualization
I mea e hiki ai ke komo i ka accelerator mai nā noi e holo ana i kahi VM, pono e hāʻawi ʻia ke awa o kēlā me kēia AFU i kahi VF me ka hoʻohana ʻana i nā pae aʻe:

1. No ka PF nā awa AFU a pau ma ka paʻamau. Pono e hoʻokuʻu mua ʻia kēlā me kēia awa i ka VF mai ka PF ma o ka FPGA_FME_PORT_RELEASE ioctl ma ka hāmeʻa FME.
2. Ke hoʻokuʻu ʻia nā awa N mai ka PF, hiki ke hoʻohana ʻia ke kauoha ma lalo nei e hiki ai iā SRIOV a me VF. Loaʻa i kēlā me kēia VF hoʻokahi awa me AFU. echo N > PCI_DEVICE_PATH/sriov_numvfs
3. E hele i nā VF i nā VM.
4. Hiki ke loaʻa ka AFU ma lalo o VF mai nā noi ma VM (me ka hoʻohana ʻana i ka mea hoʻokele like i loko o ka VF).

Nānā:
ʻAʻole hiki ke hāʻawi ʻia kahi FME i kahi VF, no laila aia wale nō ka PR a me nā hana hoʻokele ʻē aʻe ma o ka PF.

Hui Keaukaha

ʻO ka mea hoʻokele polokalamu PCIe Module

Hui Keaukaha

ʻIke ʻia nā mea FPGA e like me nā mea hana PCIe maʻamau; no laila, hoʻouka mua ʻia ka mea hoʻokele FPGA PCIe (intel-FPGA-PCI.ko) i ka manawa i ʻike ʻia ai kahi FPGA PCIe PF a i ʻole VF. Hoʻokani kēia mea hoʻokele i kahi hana infrastructural i ka hale hoʻokele hoʻokele. ʻO ia:

• Hoʻokumu i kahi mea pahu FPGA ma ke ʻano he makua o nā hāmeʻa hiʻona.
• Ke hele nei ma o ka Papa Hana Hana Mea Hana, i hoʻokō ʻia ma ka hoʻomanaʻo ʻana o ka mea hana PCIe BAR, e ʻike i nā mea hiʻohiʻona a me kā lākou mau hiʻohiʻona a hana i nā ʻenehana platform no lākou ma lalo o ka mea pahu.
• Kākoʻo iā SR-IOV.
• Hoʻopuka i ka ʻōnaehana hāmeʻa hiʻohiʻona, ka mea e hoʻokaʻawale i nā hana no nā hiʻohiʻona liʻiliʻi a hōʻike i nā hana maʻamau i nā mea hoʻokele hāmeʻa.

ʻO nā hana hoʻokele o nā mea hoʻokele ʻo PCIe Module

• Loaʻa ka ʻike PCIe, ka helu ʻana o nā hāmeʻa, a me ka ʻike hiʻohiʻona.
• Hana i nā papa kuhikuhi sysfs no ka mea makua, FPGA Management Engine (FME), a me Port.
• Hoʻokumu i nā mea hoʻokele kaʻa platform, e hoʻokau i ka kernel Linux i kā lākou mau mea hoʻokele module platform.

ʻO ka mea hoʻokele hāmeʻa FME Platform Module

• ʻO ka mana a me ka hoʻokele wela, ka hōʻike hewa, ka hōʻike ʻana i ka hana, a me nā hana ʻoihana ʻē aʻe. Hiki iā ʻoe ke komo i kēia mau hana ma o nā interface sysfs i hōʻike ʻia e ka mea hoʻokele FME.
• Hoʻonohonoho hou hapa. Hoʻopaʻa inoa ka mea hoʻokele FME i kahi Luna FPGA i ka wā o ka hoʻomaka ʻana o nā hiʻohiʻona PR; i ka manawa e loaʻa ai iā ia kahi FPGA_FME_PORT_PR ioctl mai iā ʻoe, e kāhea ana ia i ka hana maʻamau mai FPGA Manager e hoʻopau i ka hoʻonohonoho hou ʻana o ka bitstream i ka Port i hāʻawi ʻia.
• Hooponopono awa no ka virtualization. Hoʻokomo ka mea hoʻokele FME i ʻelua ioctls, FPGA_FME_PORT_RELEASE, nāna e hoʻokuʻu i ka Port i hāʻawi ʻia mai PF; a me FPGA_FME_PORT_ASSIGN, ka mea e hoʻihoʻi i ka Port i PF. Ke hoʻokuʻu ʻia ka Port mai ka PF, hiki ke hāʻawi ʻia i ka VF ma o nā kikowaena SR-IOV i hāʻawi ʻia e ka mea hoʻokele PCIe. No ka ʻike hou aku, e nānā i ka "FPGA Virtualization".

FME Platform Module Mea Keaukaha Hana

• Hoʻokumu i ka node hāmeʻa FME.
• Hoʻokumu i nā sysfs FME files a hoʻokō i nā sysfs FME file mea komo.
• Hoʻokō i nā sub-aukaha hiʻona pilikino FME.
• Nā sub-aukaha hiʻona pilikino FME:
  • Poʻomanaʻo FME
  • Hooponopono wela
  • Mana Mana
  • Hapa honua
  • Hoʻonohonoho hou hapa
  • Hana honua

Keaukaha mea hoʻopololei Port Platform Module
E like me ka mea hoʻokele FME, ua hoʻāʻo ʻia ka mea hoʻokele FPGA Port (a me AFU) (intel-fpga-afu. ko) i ka wā i hana ʻia ai ka hāmeʻa paepae Port. ʻO ka hana nui o kēia module ʻo ia ka hāʻawi ʻana i kahi interface no nā noi hoʻohana-space e hiki ai i nā mea hoʻokele hoʻokahi, me ka mana hoʻihoʻi maʻamau ma Port, AFU MMIO hoʻokuʻu ʻāina, DMA buffer mapping service, UMsg(1) hoʻolaha, a me nā hana debug mamao ( e ʻike ma luna).

Kākoʻo ʻia ʻo UMsg ma o Acceleration Stack no Intel Xeon® Processor me FPGA Hoʻohui.

Nā hana hoʻokele o nā mea hoʻokele o ka Port Platform Module

• Hoʻokumu i ka node hāmeʻa Port character.
• Hana i ka Port sysfs files a hoʻokō i ka Port sysfs file mea komo.
• Hoʻokō i ka Port private hiʻona sub-aukaha.
• Nā sub-aukaha hiʻona pilikino awa:
  • Poʻomanaʻo awa
  • AFU
  • Kupa Hapa
  • UMsg(2)
  • Paʻi hōʻailona

Noi FPGA Helu Mea Hana
Hōʻike kēia ʻāpana i ka helu ʻana o nā noi i ka polokalamu FPGA mai ka sysfs hierarchy ma lalo o /sys/class/fpga. I ka exampma lalo, ua hoʻokomo ʻia ʻelua mau mea hana Intel FPGA i ka host. Loaʻa i kēlā me kēia mea FPGA hoʻokahi FME a me ʻelua Ports (AFU). No kēlā me kēia mea hana FPGA, hana ʻia kahi papa kuhikuhi ma lalo o /sys/class/fpga:

/sys/class/fpga/intel-fpga-dev.0
/sys/class/fpga/intel-fpga-dev.1

Loaʻa i kēlā me kēia node hoʻokahi FME a me ʻelua Ports (AFU) ma ke ʻano he mau keiki:
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-fme.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.0
/sys/class/fpga/intel-fpga-dev.0/intel-fpga-port.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.2
/sys/class/fpga/intel-fpga-dev.1/intel-fpga-port.3

Ma keʻano laulā, ua kapa ʻia ka FME/Port sysfs interfaces penei:
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-fme.j/
/sys/class/fpga/intel-fpga-dev.i/intel-fpga-port.k/

me ka helu mau ana au i na mea ipu a pau, j helu i na FME a me k e helu ana i na Awa a pau.

Hiki ke kuhikuhi ʻia nā node mea hoʻohana no ioctl() a me mmap() ma o:
/dev/intel-fpga-fme.j
/dev/intel-fpga-port.k

Helu helu Keaukaha PCIe
Hoʻopau kēia ʻāpanaview o ke kahe helu no ka helu ʻana i nā mea hana i hana ʻia e intel-fpga-pci.ko. Hōʻike ʻia nā ʻōnaehana ʻikepili nui a me nā hana. ʻOi aku ka maikaʻi o kēia ʻāpana i ka wā viewme ke code kumu (pcie.c).

Nā Kūlana ʻikepili helu

enum fpga_id_type {
PARENT_ID,
FME_ID,
PORT_ID,
FPGA_ID_MAX
};
struct static idr fpga_ids[FPGA_ID_MAX];
struct fpga_chardev_info {
const char *inoa;
dev_t devt;
};
struct fpga_chardev_info fpga_chrdevs[] = {
{ .inoa = FPGA_FEATURE_DEV_FME },
{ .inoa = FPGA_FEATURE_DEV_PORT },
};
papa hana paʻa *fpga_class;
static struct pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_MCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_SKX_P),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_RCiEP0_DCP),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIe_DEVICE_ID_VF_DCP),},
{0,}
};
struct static pci_driver cci_pci_driver = {
.inoa = DRV_NAME,
.id_table = cci_pcie_id_tbl,
.probe = cci_pci_probe,
.remove = cci_pci_remove,
.sriov_configure = cci_pci_sriov_configure
};
struct cci_drvdata {
int device_id;
mea hoʻolālā *fme_dev;
struct mutex laka;
struct list_head port_dev_list;
int released_port_num;
struct list_head regions;
};
struct build_feature_devs_info {
struct pci_dev *pdev;
void __iomem *ioaddr;
void __iomem *ioend;
int current_bar;
void __iomem *pfme_hdr;
struct device * makua_dev;
struct platform_device *feature_dev;
};

Kahe helu

• ccidrv_init()
  • E hoʻomaka i ka fpga_ids me ka hoʻohana ʻana i idr_init().
  • E hoʻomaka i ka fpga_chrdevs[i].devt me ka hoʻohana ʻana i alloc_chrdev_region().
  • E hoʻomaka i ka fpga_class me ka class_create ().
  • pci_register_driver(&cci_pci_driver);
• cci_pci_probe()
  • E ho'ā i ka mea hana PCI, e noi i ke komo i kona mau ʻāpana, e hoʻonohonoho i ke ʻano master PCI, a hoʻonohonoho i ka DMA.
• cci_pci_create_feature_devs() build_info_alloc_and_init()
  • E hoʻokaʻawale i kahi struct build_feature_devs_info, e hoʻomaka.
    Hoʻonohonoho ʻia ʻo .parent_dev i kahi papa kuhikuhi sysfs makua (intel-fpga-dev.id) i loaʻa nā papa kuhikuhi FME a me Port sysfs.
• parse_feature_list()
  • E hele i ka BAR0 Device Feature List e ʻike i ka FME, ka Port, a me kā lākou mau hiʻohiʻona pilikino.
• parse_feature() parse_feature_afus() parse_feature_fme()
  • Ke loaʻa kahi FME:
• build_info_create_dev()
  • E hoʻokaʻawale i kahi hāmeʻa paepae no ka FME, e mālama ana ma build_feature_devs_info.feature_dev.
  • Hoʻomaka ʻia ka feature_dev.id i ka hopena o idr_alloc(fpga_ids[FME_ID],
  • Ua hoʻonohonoho ʻia ka feature_dev.parent i build_feature_devs_info.parent_dev.
  • E hoʻokaʻawale i kahi ʻano kumu waiwai ma feature_dev.resource.
• E hoʻokaʻawale i kahi struct feature_platform_data, hoʻomaka, a mālama i kahi kuhikuhi ma feature_dev.dev.platform_data
  • create_feature_instance() build_info_add_sub_feature()
  • E hoʻomaka i ka feature_dev.resource[FME_FEATURE_ID_HEADER].
  • feature_platform_data_add()
  • E hoʻomaka i ka feature_platform_data.features[FME_FEATURE_ID_HEADER], nā mea a pau akā .fops.
• parse_feature() parse_feature_afus() parse_feature_port()
  • Ke ʻike ʻia kahi Port:
• build_info_create_dev()
  • E hoʻokaʻawale i kahi hāmeʻa paepae no ka Awa, e mālama ana ma build_feature_devs_info.feature_dev.
  • Hoʻomaka ʻia ka feature_dev.id i ka hopena o idr_alloc(fpga_ids[PORT_ID],
  • Ua hoʻonohonoho ʻia ka feature_dev.parent i build_feature_devs_info.parent_dev.
  • E hoʻokaʻawale i kahi ʻano kumu waiwai ma feature_dev.resource.
  • E hoʻokaʻawale i kahi struct feature_platform_data, hoʻomaka, a mālama i kahi kuhikuhi ma feature_dev.dev.platform_data
• build_info_commit_dev()
  • Hoʻohui i ka struct feature_platform_data.node no ka Awa i ka papa inoa o nā Awa ma struct cci_drvdata.port_dev_list
• create_feature_instance() build_info_add_sub_feature()
  • E hoʻomaka i ka feature_dev.resource[PORT_FEATURE_ID_HEADER].
• feature_platform_data_add()
  • E hoʻomaka i ka feature_platform_data.features[PORT_FEATURE_ID_HEADER], nā mea a pau koe wale nō .fops.
• parse_feature() parse_feature_afus() parse_feature_port_uafu()
  • Ke loaʻa kahi AFU:
• create_feature_instance() build_info_add_sub_feature()
  • E hoʻomaka i ka feature_dev.resource[PORT_FEATURE_ID_UAFU].
• feature_platform_data_add()
  • E hoʻomaka i ka feature_platform_data.features[PORT_FEATURE_ID_UAFU], nā mea a pau koe wale nō .fops.
• parse_feature() parse_feature_private() parse_feature_fme_private()
  • Ke ʻike ʻia kahi hiʻohiʻona pilikino FME:
• create_feature_instance() build_info_add_sub_feature()
  • E hoʻomaka i ka feature_dev.resource[id].
• feature_platform_data_add()
  • E hoʻomaka i ka feature_platform_data.features[id], nā mea a pau koe wale nō .fops.
• parse_feature() parse_feature_private() parse_feature_port_private()
• Ke ʻike ʻia kahi hiʻohiʻona pilikino Port: * create_feature_instance() build_info_add_sub_feature() * Initialize feature_dev.resource[id]. * feature_platform_data_add() E hoʻomaka i ka feature_platform_data.features[id], nā mea a pau akā .fops.
• parse_ports_mai_fme()
  • Inā hoʻouka ʻia ka mea hoʻokele ma ka Physical Function (PF), a laila:
• E holo i ka parse_feature_list() kahe ma kēlā me kēia awa i wehewehe ʻia ma ke poʻo FME.
• E hoʻohana i ka BAR i ʻōlelo ʻia ma kēlā me kēia puka puka ma ke poʻo.

ʻO ka hoʻomaka ʻana o ka polokalamu FME Platform
Hoʻopau kēia ʻāpanaview o ke kahe helu no ka hoʻomaka ʻana o ka mea FME i hana ʻia e intel-fpga-fme.ko. Hoʻokiʻekiʻe ʻia nā hale ʻikepili nui a me nā hana. ʻOi aku ka maikaʻi o kēia ʻāpana i ka wā viewme ke code kumu (fme-main.c).

Nā Kūlana ʻIkepili Pūnaewele FME

struct feature_ops {
int (* init)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona);
int (*uinit)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona);
lōʻihi (* ioctl)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona,
unsigned int cmd, unsigned long arg);
int (* ho'āʻo)(struct platform_device *pdev, struct hiʻona * hiʻohiʻona);
};
hiʻona hana {
const char *inoa;
int resource_index;
void __iomem *ioaddr;
struct feature_ops *ops;
};
struct feature_platform_data {
struct list_head node;
struct mutex laka;
dev_status lōʻihi i kau inoa ʻole ʻia;
struct cdev cdev;
struct platform_device *dev;
unsigned int disable_count;
void *kaawale;
int helu;
int (* config_port)(struct platform_device *, u32, bool);
struct platform_device *(*fpga_for_each_port)(struct platform_device *,
void *, int (* match)(struct platform_device *, void *)); struct
hiʻona hiʻona[0];
};
struct perf_object {
int id;
const struct attribute_group **attr_groups;
mea hoʻolālā *fme_dev;
struct list_head node;
struct list_head keiki;
struct kobject kobj;
};
struct fpga_fme {
u8 port_id;
u64 pr_err;
struct device *dev_err;
struct perf_object *perf_dev;
struct feature_platform_data *pdata;
};

ʻO ke kahe o ka hoʻomaka ʻana o ka polokalamu FME Platform

Kahe Hoʻomaka FME

• fme_probe() fme_dev_init()
  • E hoʻomaka i kahi struct fpga_fme a mālama iā ia i loko o ke kahua feature_platform_data.private.
• fme_probe() fpga_dev_feature_init() feature_instance_init()
  • E mālama i kahi struct feature_ops i loko o ka feature_platform_data.features no kēlā me kēia hiʻohiʻona.
  • Kāhea i ka hana hoʻāʻo, inā loaʻa, mai ke kūkulu.
  • Kāhea i ka hana init mai ka struct.
• fme_probe() fpga_register_dev_ops()
  • E hoʻokumu i ka node mea hana FME, e hoʻopaʻa inoa i kahi kūkulu file_hana.

ʻO ka hoʻomaka ʻana o nā mea hana Port Platform
Hoʻopau kēia ʻāpanaview o ke kahe o ke code no ka hoʻomaka ʻana o ka hāmeʻa awa i hana ʻia e intel-fpga-afu.ko. Hōʻike ʻia nā ʻōnaehana ʻikepili nui a me nā hana. ʻOi aku ka maikaʻi o kēia ʻāpana i ka wā viewme ke code kumu (afu.c).

Nā Kūlana ʻIkepili ʻIkepili Port Platform

struct feature_ops {
int (* init)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona);
int (*uinit)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona);
lōʻihi (* ioctl)(struct platform_device *pdev, hiʻona hana * hiʻohiʻona,
unsigned int cmd, unsigned long arg);
int (* ho'āʻo)(struct platform_device *pdev, struct hiʻona * hiʻohiʻona);
};
hiʻona hana {
const char *inoa;
int resource_index;
void __iomem *ioaddr;
struct feature_ops *ops;
};
struct feature_platform_data {
struct list_head node;
struct mutex laka;
dev_status lōʻihi i kau inoa ʻole ʻia;
struct cdev cdev;
struct platform_device *dev;
unsigned int disable_count;
void *kaawale;
int helu;
int (* config_port)(struct platform_device *, u32, bool);
struct platform_device *(*fpga_for_each_port)(struct platform_device *,
void *, int (* match)(struct platform_device *, void *));
struct hiʻona hiʻona[0];
};
struct fpga_afu_region {
u32 index;
u32 hae;
u64 nui;
u64 offset;
u64 kino;
struct list_head node;
};
struct fpga_afu_dma_region {
u64 mea hoʻohana_addr;
u64 lōʻihi;
u64 iova;
ʻaoʻao kūkulu ** ʻaoʻao;
struct rb_node node;
bool in_use;
};
struct fpga_afu {
u64 region_cur_offset;
int num_regions;
u8 num_umsgs;
struct list_head regions;
struct rb_root dma_regions;
struct feature_platform_data *pdata;
};

Ke kahe hoʻomaka ʻana o nā mea hana Port Platform

Kahe hoʻomaka ʻana o ke awa

• afu_probe() afu_dev_init()
  • E hoʻomaka i kahi struct fpga_afu a mālama iā ia ma ka māhele feature_platform_data.private.
• afu_probe() fpga_dev_feature_init() feature_instance_init()
  • E mālama i kahi struct feature_ops i loko o ka feature_platform_data.features no kēlā me kēia hiʻohiʻona.
  • Kāhea i ka hana hoʻāʻo, inā loaʻa, mai ke kūkulu.
  • Kāhea i ka hana init mai ka struct.
• afu_probe() fpga_register_dev_ops()
  • E hana i ka node o ka mea Port character, e hoʻopaʻa inoa i kahi kūkulu file_hana.

Nā IOCTL FME
IOCTL i kapa ʻia ma kahi hāmama file wehewehe no /dev/intel-fpga-fme.j FPGA_GET_API_VERSION—e hoʻihoʻi i ka mana o kēia manawa ma ke ʻano he helu helu, e hoʻomaka ana mai ka 0.

FPGA_CHECK_EXTENSION—ʻaʻole i kākoʻo ʻia i kēia manawa.

FPGA_FME_PORT_RELEASE—arg kahi kuhikuhi i kahi:

struct fpga_fme_port_release {
__u32 argsz; // i: sizeof(struct fpga_fme_port_release)
__u32 hae; // i: pono 0
__u32 port_id; // i: port ID (mai 0) e hoʻokuʻu.
};

FPGA_FME_PORT_ASSIGN—arg kahi kuhikuhi i kahi:

struct fpga_fme_port_assign {
__u32 argsz; // i: sizeof(struct fpga_fme_port_assign)
__u32 hae; // i: pono 0
__u32 port_id; // i: port ID (mai 0) e hāʻawi. (ʻo ia paha
i hoʻokuʻu mua ʻia e FPGA_FME_PORT_RELEASE)
};

FPGA_FME_PORT_PR—arg kahi kuhikuhi i kahi:

struct fpga_fme_port_pr {
__u32 argsz; // i: sizeof(struct fpga_fme_port_pr)
__u32 hae; // i: pono 0
__u32 port_id; // ma: ID awa (mai 0)
__u32 buffer_size; // in: ka nui o ka bitstream buffer ma nā bytes. Pono ʻo 4-byte
kaulike.
__u64 buffer_address; // i: ka helu wahi o ka bitstream buffer
__u64 kūlana; // waho: kūlana hewa (bitmask)
};

Port IOCTLs
IOCTL i kapa ʻia ma kahi hāmama file wehewehe no /dev/intel-fpga-port.k FPGA_GET_API_VERSION—e hoʻihoʻi i ka mana o kēia manawa ma ke ʻano he helu helu, e hoʻomaka ana mai ka 0. FPGA_CHECK_EXTENSION—ʻaʻole i kākoʻo ʻia i kēia manawa.

FPGA_PORT_GET_INFO—arg kahi kuhikuhi i kahi:

struct fpga_port_info {
__u32 argsz; // i: sizeof(struct fpga_port_info)
__u32 hae; // i waho: hoʻi mai 0
__u32 num_regions; // i waho: helu o nā ʻāpana MMIO, 2 (1 no AFU a me 1 no
STP)
__u32 num_umsgs; // waho: ka helu o nā UMsg i kākoʻo ʻia e ka lako
};

FPGA_PORT_GET_REGION_INFO—arg kahi kuhikuhi i kahi:

struct fpga_port_region_info {
__u32 argsz; // i: sizeof(struct fpga_port_region_info)
__u32 hae; // waho: (bitmask) { FPGA_REGION_READ, FPGA_REGION_WRITE,
FPGA_REGION_MMAP }
__u32 index; // ma: FPGA_PORT_INDEX_UAFU a i ʻole FPGA_PORT_INDEX_STP
__u32 padding; // i: pono 0
__u64 nui; // waho: ka nui o ka māhele MMIO ma nā paita
__u64 offset; // i waho: offset o MMIO māhele mai ka hoʻomaka ʻana o ka hāmeʻa fd
};

FPGA_PORT_DMA_MAP—arg kahi kuhikuhi i kahi:
struct fpga_port_dma_map {
__u32 argsz; // i: sizeof(struct fpga_port_dma_map)
__u32 hae; // i: pono ʻo 0 __u64 user_addr; // i: kaʻina virtual
helu wahi. Pono e hoʻolikelike ʻia ka ʻaoʻao.
__u64 lōʻihi; // in: ka lōʻihi o ka palapala ʻāina ma nā bytes. Pono he mau ʻaoʻao
nui.
__u64 iova; // i waho: IO virtual address };

FPGA_PORT_DMA_UNMAP—arg kahi kuhikuhi i kahi:
struct fpga_port_dma_unmap {
__u32 argsz; // i: sizeof(struct fpga_port_dma_unmap)
__u32 hae; // i: pono 0
__u64 iova; // i: IO helu helu virtual i hoʻihoʻi ʻia e kahi mua
FPGA_PORT_DMA_MAP };

• FPGA_PORT_RESET—ʻo ka arg he NULL.
• FPGA_PORT_UMSG_ENABLE—ʻo ka arg he NULL.
• FPGA_PORT_UMSG_DISABLE—Pono ka NULL.

FPGA_PORT_UMSG_SET_MODE—arg kahi kuhikuhi i kahi:

struct fpga_port_umsg_cfg {
__u32 argsz; // i: sizeof(struct fpga_port_umsg_cfg)
__u32 hae; // i: pono 0
__u32 hint_bitmap; // i: UMsg hōʻike manaʻo bitmap. E hōʻike ana i nā UMsg
hiki.
};

FPGA_PORT_UMSG_SET_BASE_ADDR—

• Pono e hoʻopau ʻia ka UMsg ma mua o ka hoʻopuka ʻana i kēia ioctl.
• Pono ka māla iova no kahi pale nui no nā UMsg a pau (num_umsgs * PAGE_SIZE).
  • Hōʻailona ʻia ka buffer ma ke ʻano he "hoʻohana" e ka hoʻokele hoʻokele o ka mea hoʻokele.
  • Inā ʻo NULL ka iova, ʻaʻole hōʻailona ʻia kekahi ʻāina ma mua he "hoʻohana ʻia".
• ʻO arg kahi kuhikuhi i kahi:
  struct fpga_port_umsg_base_addr {
  • u32 argsz; // i: sizeof(struct fpga_port_umsg_base_addr)
  • u32 hae; // i: pono 0
  • u64 iova; // i: IO helu kuhi henua mai FPGA_PORT_DMA_MAP. };

Nānā:

• No ka hoʻomaʻemaʻe i nā hewa awa, pono ʻoe e kākau i ka bitmask pololei o nā hewa o kēia manawa, no example, hewa popoki > maopopo
• Kākoʻo ʻia ʻo UMsg ma o Acceleration Stack no Intel Xeon Processor me FPGA Integrated.

sysfs Files

FME Header sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/

sysfs file	kahua mmio	ʻano ʻano	komo
helu_puka	fme_header.capability.num_ports	decimal int	Heluhelu wale
cache_size	fme_header.capability.cache_size	decimal int	Heluhelu wale
manaʻo	fme_header.capability.fabric_verid	decimal int	Heluhelu wale
socket_id	fme_header.capability.socket_id	decimal int	Heluhelu wale
bitstream_id	fme_header.bitstream_id	hex uint64_t	Heluhelu wale
bitstream_metadata	fme_header.bitstream_md	hex uint64_t	Heluhelu wale

ʻO nā sysfs hoʻokele wela FME files
intel-fpga-dev.i/intel-fpga-fme.j/thermal_mgmt/

sysfs file	kahua mmio	ʻano ʻano	komo
paepae1	thermal.threshold.tmp_thshold1	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
paepae2	thermal.threshold.tmp_thshold2	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
paepae_hele	thermal.threshold.therm_trip_thshold	decimal int	Heluhelu wale
paepae1_reached	thermal.threshold.thshold1_status	decimal int	Heluhelu wale
paepae2_reached	thermal.threshold.thshold2_status	decimal int	Heluhelu wale
paepae1_kulekele	wela. paepae.thshold_policy	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
mahana wela	thermal.rdsensor_fm1.fpga_temp	decimal int	Heluhelu wale

FME Mana Mana Mana sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/power_mgmt/

sysfs file	kahua mmio	ʻano ʻano	komo
ʻai ʻia	power.status.pwr_consumed	hex uint64_t	Heluhelu wale
paepae1	mana. paepae. paepae1	hex uint64_t	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
paepae2	mana. paepae. paepae2	hex uint64_t	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
paepae1_kūlana	mana.threshold.threshold1_status	helu helu ʻole	Heluhelu wale
paepae2_kūlana	mana.threshold.threshold2_status	helu helu ʻole	Heluhelu wale
rtl	power.status.fpga_latency_report	helu helu ʻole	Heluhelu wale

FME Global Error sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/errors/

sysfs file	kahua mmio	ʻano ʻano	komo
pcie0_hewa	gerror.pcie0_err	hex uint64_t	Heluhelu-kākau
pcie1_hewa	gerror.pcie1_err	hex uint64_t	Heluhelu-kākau
inject_error	gerror.ras_error_inj	hex uint64_t	Heluhelu-kākau

intel-fpga-dev.i/intel-fpga-fme.j/errors/fme-errors/

sysfs file	kahua mmio	ʻano ʻano	komo
hewa	gerror.fme_err	hex uint64_t	Heluhelu wale
mua_hewa	gerror.fme_first_err.err_reg_status	hex uint64_t	Heluhelu wale
hala_kea	gerror.fme_next_err.err_reg_status	hex uint64_t	Heluhelu wale
maopopo	Holoi i nā hewa, first_error, next_error	like ole uint64_t	Kākau-wale nō

Nānā:
No ka holoi ʻana i nā hewa FME, pono ʻoe e kākau i ka bitmask pololei o nā hewa o kēia manawa, no ka example popoki hewa > maopopo.

ʻO nā sysfs hoʻonohonoho ʻāpana ʻāpana FME files
intel-fpga-dev.i/intel-fpga-fme.j/pr/

sysfs file	kahua mmio	ʻano ʻano	komo
interface_id	pr.fme_pr_intfc_id0_h, pr.fme_pre_intfc_id0_l	hex 16-byte	Heluhelu wale

FME Global Performance sysfs files
intel-fpga-dev.i/intel-fpga-fme.j/dperf/clock

sysfs file	kahua mmio	ʻano ʻano	komo
uaki	gperf.clk.afu_interf_clock	hex uint64_t	Heluhelu wale

intel-fpga-dev.i/intel-fpga-fme.j/dperf/cache/ (ʻAʻole kūpono no ka Acceleration Stack no Intel Xeon CPU me nā FPGA)

sysfs file	kahua mmio	ʻano ʻano	komo
maloʻo	gperf.ch_ctl.freeze	decimal int	Heluhelu-kākau
heluhelu_hit	gperf.CACHE_RD_HIT	hex uint64_t	Heluhelu wale
heluhelu_miss	gperf.CACHE_RD_MISS	hex uint64_t	Heluhelu wale
kākau_paʻi	gperf.CACHE_WR_HIT	hex uint64_t	Heluhelu wale
kākau_miss	gperf.CACHE_WR_MISS	hex uint64_t	Heluhelu wale
paʻa_noi	gperf.CACHE_HOLD_REQ	hex uint64_t	Heluhelu wale
tx_req_stall	gperf.CACHE_TX_REQ_STALL	hex uint64_t	Heluhelu wale

sysfs file	kahua mmio	ʻano ʻano	komo
rx_req_stall	gperf.CACHE_RX_REQ_STALL	hex uint64_t	Heluhelu wale
ʻikepili_write_port_contention	gperf.CACHE_DATA_WR_PORT_CONTEN	hex uint64_t	Heluhelu wale
tag_write_port_contention	gpef.CACHE_TAG_WR_PORT_CONTEN	hex uint64_t	Heluhelu wale

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/ (ʻAʻole kūpono no ka Acceleration Stack no Intel Xeon CPU me nā FPGA)

sysfs file	kahua mmio	ʻano ʻano	komo
maloʻo	gpef.vtd_ctl.freeze	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau

intel-fpga-dev.i/intel-fpga-fme.j/dperf/iommu/afuk/ (ʻAʻole kūpono no ka Acceleration Stack no Intel Xeon CPU me nā FPGA)

sysfs file	kahua mmio	ʻano ʻano	komo
heluhelu_transaction	gperf.VTD_AFU0_MEM_RD_TRANS	hex uint64_t	Heluhelu wale
kakau_transaction	gperf.VTD_AFU0_MEM_WR_TRANS	hex uint64_t	Heluhelu wale
tlb_read_hit	gperf.VTD_AFU0_TLB_RD_HIT	hex uint64_t	Heluhelu wale
tlb_write_hit	gperf.VTD_AFU0_TLB_WR_HIT	hex uint64_t	Heluhelu wale

intel-fpga-dev.i/intel-fpga-fme.j/dperf/fabric/

sysfs file	kahua mmio	ʻano ʻano	komo
hiki	gpperf.fab_ctl.(hoʻohana ʻia)	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
maloʻo	gpef.fab_ctl.freeze	decimal int	Mea hoʻohana: Heluhelu wale nō Root: Heluhelu-kākau
pcie0_heluhelu	gperf.FAB_PCIE0_RD	hex uint64_t	Heluhelu wale
pcie0_kākau	gperf.FAB_PCIE0_WR	hex uint64_t	Heluhelu wale
pcie1_heluhelu	gperf.FAB_PCIE1_RD	hex uint64_t	Heluhelu wale
pcie1_kākau	gperf.FAB_PCIE1_WR	hex uint64_t	Heluhelu wale
upi_heluhelu	gperf.FAB_UPI_RD	hex uint64_t	Heluhelu wale
upi_kākau	gperf.FAB_UPI_WR	hex uint64_t	Heluhelu wale

intel-fpga-ev.i/intel-fpga/fme.j/dperf/fabric/portk/

sysfs file	kahua mmio	ʻano ʻano	komo
pcie0_heluhelu	gperf.FAB_PCIE0_RD	hex uint64_t	Heluhelu wale
pcie0_kākau	gperf.FAB_PCIE0_WR	hex uint64_t	Heluhelu wale
pcie1_heluhelu	gperf.FAB_PCIE1_RD	hex uint64_t	Heluhelu wale
pcie1_kākau	gperf.FAB_PCIE1_WR	hex uint64_t	Heluhelu wale
upi_heluhelu	gperf.FAB_UPI_RD	hex uint64_t	Heluhelu wale
upi_kākau	gperf.FAB_UPI_WR	hex uint64_t	Heluhelu wale

Nā sysfs Poʻomanaʻo Port files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	kahua mmio	ʻano ʻano	komo
id	port_header.capability.port_number	decimal int	Heluhelu wale
ltr	port_header.control.latency_tolerance	decimal int	Heluhelu wale

Port AFU Header sysfs files
intel-fpga-dev.i/intel-fpga-port.k/

sysfs file	kahua mmio	ʻano ʻano	komo
afu_id	afu_header.guid	hex 16-byte	Heluhelu wale

Hapa awa sysfs files
intel-fpga-dev.i/intel-fpga-port.k/errors/

sysfs file	kahua mmio	ʻano ʻano	komo
hewa	perror.port_error	hex uint64_t	Heluhelu wale
mua_hewa	perror.port_first_error	hex uint64_t	Heluhelu wale
first_malformed_req	perror.malreq	hex 16-byte	Heluhelu wale
maopopo	hewa.(hewa a pau)	like ole uint64_t	Kākau-wale nō

Nānā:
No ka holoi ʻana i nā hewa Port, pono ʻoe e kākau i ka bitmask pololei o nā hewa o kēia manawa, no example popoki hewa > maopopo.

Moolelo Hooponopono

Palapala Palapala	Nā hoʻololi
2017.10.02	Hoʻokuʻu mua.

OPAE Intel FPGA Linux Device Driver Architecture Guide

Palapala / Punawai

intel OPAE FPGA Linux Mea Hoʻokele Hoʻokele Hoʻokele [pdf] Ke alakaʻi hoʻohana OPAE FPGA Linux Mea Hoʻokele Hoʻokele Hoʻokele, OPAE FPGA, Linux Mea Hoʻokele Hoʻokele Hoʻokele, Hoʻolālā Keaukaha, Hoʻolālā

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