onsemi 74LVX273 Low Voltage Octal Buffer/Line Driver Datasheet

Product Overview

The 74LVX273 is an octal D-type flip-flop featuring edge-triggered operation. It includes individual D inputs and Q outputs for each of the eight flip-flops. A common buffered Clock (CP) input and a Master Reset (MR) input allow for simultaneous loading and resetting (clearing) of all flip-flops. The register is fully edge-triggered, transferring the state of each D input to its corresponding Q output one setup time before the LOW-to-HIGH clock transition.

A LOW voltage level on the MR input forces all outputs to LOW, independent of the Clock or Data inputs. This device is particularly useful in applications requiring only true outputs where the Clock and Master Reset are common to all storage elements. The inputs are designed to tolerate up to 5.5 V, enabling interface between 5 V systems and 3 V systems.

Key Features

Input Voltage Translation from 5 V to 3 V
Ideal for Low Power/Low Noise 3.3 V Applications
Guaranteed Simultaneous Switching Noise Level and Dynamic Threshold Performance
Devices are Pb-Free, Halogen Free/BFR Free, and RoHS Compliant

Pin Description

Pin Names	Description
D0–D7	Data Inputs
MR	Master Reset
CP	Clock Pulse Input
Q0–Q7	Data Outputs

Truth Table

Operating Mode	Inputs			Outputs
Operating Mode	MR	CP	Dn	Outputs	Qn
Reset (Clear)	L	X	X	L
Load '1'	H	H	H	H
Load '0'	H	L	L	L

Legend: H = High Voltage Level, L = Low Voltage Level, X = Immaterial, Z = High Impedance

Logic Symbols

Figure 1. Logic Symbols (IEEE/IEC)

The logic symbols depict the standard IEEE/IEC representations for the D-type flip-flops. Each flip-flop has a D input, a Clock (CP) input, and a Q output. The device features a common Master Reset (MR) input that affects all flip-flops simultaneously. The diagram shows eight such flip-flops integrated into the device.

Connection Diagram

Figure 2. Connection Diagram

The connection diagram illustrates the pinout for the SOIC-20W and TSSOP-20 packages. For the SOIC-20W package (20 pins), pin 1 is typically marked with a dot and corresponds to the start of the pin numbering sequence. Pins include VCC, GND, Data Inputs (D0-D7), Clock Pulse Input (CP), Master Reset (MR), and Data Outputs (Q0-Q7). For the TSSOP-20 package, the pin assignments are similar, with specific pin numbers corresponding to VCC, GND, inputs, and outputs.

Logic Diagram

Figure 3. Logic Diagram

This diagram shows the internal logic structure of the 74LVX273. It consists of eight D-type flip-flops arranged in parallel. Each flip-flop has its own D input and Q output. All flip-flops share a common Clock (CP) input and a common Master Reset (MR) input. The diagram visually represents how data is clocked into the flip-flops and how the reset function operates across the entire device.

Electrical Characteristics

Maximum Ratings

Symbol	Parameter	Value	Unit
VCC	DC Supply Voltage	-0.5 to +6.5	V
VIN	DC Input Voltage	-0.5 to +6.5	V
VOUT	DC Output Voltage	-0.5 to VCC + 0.5	V
IIN	DC Input Current, per Pin	±20	mA
IOUT	DC Output Current, per Pin	±25	mA
ICC	DC Supply Current, VCC and GND Pins	±75	mA
IIK	Input Clamp Current	-20	mA
IOK	Output Clamp Current	+20	mA
TSTG	Storage Temperature Range	-65 to +150	°C
TL	Lead Temperature, 1 mm from Case for 10 Seconds	260	°C
TJ	Junction Temperature Under Bias	+150	°C
θJA	Thermal Resistance (Note 2)	96 (SOIC-20W)	°C/W
θJA	Thermal Resistance (Note 2)	150 (TSSOP-20)	°C/W
PD	Power Dissipation in Still Air at 25 °C	1302 (SOIC-20W)	mW
PD	Power Dissipation in Still Air at 25 °C	833 (TSSOP-20)	mW
MSL	Moisture Sensitivity	Level 3 (SOIC-20W)	-
MSL	Moisture Sensitivity	Level 1 (All Other Packages)	-
FR	Flammability Rating	UL 94 V-0 @ 0.573 in	-
VESD	ESD Withstand Voltage (Note 3)	2000 (Human Body Model)	V
VESD	ESD Withstand Voltage (Note 3)	N/A (Charged Device Model)	V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Applicable to devices with outputs that may be tri-stated. 2. Measured with minimum pad spacing on an FR4 board, using 76 mm-by-114 mm, 2-ounce copper trace no air flow per JESD51-7. 3. HBM tested to EIA / JESD22-A114-A. CDM tested to JESD22-C101-A. JEDEC recommends that ESD qualification to EIA/JESD22-A115A (Machine Model) be discontinued.

Recommended Operating Conditions

Symbol	Parameter	Min	Max	Unit
VCC	DC Supply Voltage	2.0	3.6	V
VIN	DC Input Voltage (Note 4)	0	5.5	V
VOUT	DC Output Voltage (Note 4)	0	VCC	V
TA	Operating Temperature	-40	+85	°C
tr, tf	Input Rise or Fall Rate	0	100	ns/V

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 4. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

DC Electrical Characteristics

Symbol	Parameter	Conditions	VCC (V)			TA = -40 °C to +85 °C			TA = -40 °C to +125 °C		Unit
Symbol	Parameter	Conditions		Min	Typ	Max	Min	Max	Min	Max	Unit
VIH	High-Level Input Voltage	2.0	1.5		1.5		1.5	V
		3.0	2.0		2.0		2.0	V
		3.6	2.4		2.4		2.4	V
VIL	Low-Level Input Voltage	2.0		0.5	0.5		0.5	V
		3.0		0.8	0.8		0.8	V
		3.6		0.8	0.8		0.8	V
VOH	High-Level Output Voltage	VIN = VIH or VIL, IOH = -50 μA	2.0	1.9		2.0	1.9		1.9	V
		3.0	2.9		3.0	2.9		2.9	V
		IOH = -4 mA	3.6	2.58		2.48		2.48	V
VOL	Low-Level Output Voltage	VIN = VIH or VIL, IOH = -50 μA	2.0	0		0.1	0		0.1	V
		3.0	0		0.1	0		0.1	V
		IOL = -4 mA	3.6	0.36		0.44		0.44	V
IOZ	3-State Output Leakage Current	VIN = VIH or VIL, VOUT = VCC or GND	3.6		±0.25	±2.5	μA
IIN	Input Leakage Current	VIN = 5.5 V or GND	3.6		±0.1	±1.0	μA
ICC	Quiescent Supply Current	VIN = 5.5 V or GND	3.6		±4.0	40.0	μA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

AC Electrical Characteristics

Symbol	Parameter	CL (pF)	VCC (V)	TA = -40 °C to +85 °C			TA = -40 °C to +125 °C			Unit
Symbol	Parameter	CL (pF)	VCC (V)	Min	Typ	Max	Min	Max		Unit
tPLH, tPHL	Propagation Delay CP to Qn	15	2.7	9.0	16.9	1.0	20.5	ns
		50	11.5	20.0	1.0	24.0
		15	3.3 ± 0.3	7.1	11.0	1.0	13.0
		50	9.6	14.5	1.0	16.5
tPHL	Propagation Delay MR to Qn	15	2.7	9.3	17.8	1.0	20.5	ns
		50	11.8	21.1	1.0	24.0
		15	3.3 ± 0.3	7.3	11.5	1.0	13.5
		50	9.8	15.0	1.0	17.0
ts	Setup Time Dn to CP	2.7	8.0	9.5	ns
ts	Setup Time Dn to CP	3.3 ± 0.3	5.5	6.5	ns
th	Hold Time Dn to CP	2.7	1.0	1.0	ns
th	Hold Time Dn to CP	3.3 ± 0.3	1.0	1.0	ns
tREC	Removal Time MR to Qn	2.7	4.0	4.0	ns
tREC	Removal Time MR to Qn	3.3 ± 0.3	2.5	2.5	ns
tw	Clock Pulse Width	2.7	8.0	9.5	ns
tw	Clock Pulse Width	3.3 ± 0.3	5.5	6.5	ns
tw	MR Pulse Width	2.7	7.5	8.5	ns
		3.3 ± 0.3	5.0	6.0
		fMAX	Maximum Clock Frequency	15		2.7	55	110	45	MHz
				50		45	60	40
15	3.3 ± 0.3			95	150	80	MHz
50	60			90	50
tOSLH, tOSHL	Output to Output Skew (Note 5)	50	2.7	1.5	1.5	ns
tOSLH, tOSHL	Output to Output Skew (Note 5)	3.3 ± 0.3	1.5	1.5		ns

5. Parameter guaranteed by design. tOSLH = | tPLHm - tPLHn |, tOSHL = |tPHLm - tPHLn|.

Noise Characteristics

Symbol	Characteristic	CL (pF)	VCC (V)	Typ	Limit	Unit
VOLP	Quiet Output Dynamic Peak VOL	50	3.3	0.5	0.8	V
VOLV	Quiet Output Dynamic Valley VOL	50	3.3	0.5	0.8	V
VIHD	Minimum HIGH Level Dynamic Input Voltage	50	3.3		2.0	V
VILD	Maximum HOW Level Dynamic Input Voltage	50	3.3		0.8	V

Capacitive Characteristics

Symbol	Parameter	TA = +25 °C		TA = -40 °C to +125 °C		Unit
		Min	Typ	Max	Min	Max
CIN	Input Capacitance		4	10		10	pF
COUT	Output Capacitance		6				pF
CPD	Power Dissipation Capacitance (Note 6)			31			pF

6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the following equation: ICC(opr.) = (CPD × VCC × fIN) / 8 (per F/F) (eq. 1)

Ordering Information

Device	Marking	Package	Shipping
74LVX273MTCX	LCX 273	TSSOP-20 (Pb-Free)	2500 / Tape & Reel

† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

Mechanical Case Outlines

SOIC-20W, 300 mils (CASE 751BJ)

Package Dimensions for SOIC-20W, 300 mils. This section provides detailed dimensional drawings and a table of specifications for the SOIC-20W package. Key dimensions include body length (D), body width (E1), overall width (E), lead pitch (e), lead thickness (c), lead width (b), and height (A, A1, A2). Angles (θ, θ1) are also specified. All dimensions are in millimeters, and angles are in degrees. Complies with JEDEC MS-013.

TSSOP20, 4.4x6.5 (CASE 948AQ)

Package Dimensions for TSSOP20, 4.4x6.5. This section provides detailed dimensional drawings and a table of specifications for the TSSOP20 package. Key dimensions include body length (D), body width (E1), overall width (E), lead pitch (e), lead thickness (c), lead width (b), and height (A, A1, A2). The lead length (L) and standoff height (L1) are also specified. All dimensions are in millimeters, and angles are in degrees. Complies with JEDEC MO-153.

Revision History

Revision	Description of Changes	Date
2	Converted the Data Sheet to onsemi format with the updates to Ordering Information and Maximum Ratings tables.	09/15/2025

This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made on the noted approval dates.

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onsemi 74LVX273 Low Voltage Octal Buffer/Line Driver with 5 V Tolerant Inputs and Outputs