onsemi

MC74VHC138

3-to-8 Line Decoder

The MC74VHC138 is an advanced high-speed CMOS 3-to-8 decoder fabricated with silicon gate CMOS technology. It achieves high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.

Features

High Speed: t_PD = 5.7ns (Typ) at V_CC = 5 V
Low Power Dissipation: I_CC = 4 μA (Max) at T_A = 25°C
High Noise Immunity: V_NIH = V_NIL = 28% V_CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V_OLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 122 FETs or 30.5 Equivalent Gates
These Devices are Pb-Free and are RoHS Compliant

Ordering Information

Device	Package	Shipping†
MC74VHC138DR2G	SOIC-16	2500/Tape & Reel
MC74VHC138DTR2G	TSSOP-16	2500/Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

DISCONTINUED (Note 1)

MC74VHC138DG SOIC-16 48 Units / Tube

Note 1: This device is not recommended for new design. Please contact your onsemi representative for information. The most current information on this device may be available on www.onsemi.com.

Pin Assignment

Pin	Signal	Pin	Signal
1	A0	16	Vcc
2	A1	15	Y0
3	A2	14	Y1
4	E1	13	Y2
5	E2	12	Y3
6	E3	11	Y4
7	Y7	10	Y5
8	GND	9	Y6

Function Table

H = high level (steady state); L = low level (steady state); X = don't care

E3	E2	E1	A2	A1	A0	Outputs
E3	E2	E1	A2	A1	A0	Y0	Y1	Y2	Y3	Y4	Y5	Y6	Y7
X	X	X	X	X	X	H	H	H	H	H	H	H	H
L	X	X	X	X	X	H	H	H	H	H	H	H	H
X	H	X	X	X	X	H	H	H	H	H	H	H	H
X	X	L	X	X	X	H	H	H	H	H	H	H	H
H	L	L	L	L	L	L	H	H	H	H	H	H	H
H	L	L	L	L	H	H	L	H	H	H	H	H	H
H	L	L	L	H	L	H	H	L	H	H	H	H	H
H	L	L	L	H	H	H	H	H	L	H	H	H	H
H	L	L	H	L	L	H	H	H	H	L	H	H	H
H	L	L	H	L	H	H	H	H	H	L	H	H
H	L	L	H	H	L	H	H	H	H	H	L	H
H	L	L	H	H	H	H	H	H	H	H	L

Logic Diagram

Expanded Logic Diagram:

[Diagram showing logic gates for the MC74VHC138]

IEC Logic Diagram:

[Diagram showing IEC symbols for the MC74VHC138]

Maximum Ratings

Symbol	Parameter	Value	Unit
V_CC	DC Supply Voltage	-0.5 to +7.0	V
V_in	DC Input Voltage	0.5 to +7.0	V
V_out	DC Output Voltage	0.5 to V_CC + 0.5	V
I_IK	Input Diode Current	20	mA
I_OK	Output Diode Current	±20	mA
I_out	DC Output Current, per Pin	±25	mA
I_CC	DC Supply Current, V_CC and GND Pins	±75	mA
P_D	Power Dissipation in Still Air, SOIC Packages†	500	mW
P_D	Power Dissipation in Still Air, TSSOP Packages†	450	mW
T_stg	Storage Temperature	-65 to +150	°C

*Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.

†Derating: SOIC Packages: – 7 mW/°C from 65° to 125°C; TSSOP Package: – 6.1 mW/°C from 65° to 125°C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V_in and V_out should be constrained to the range GND ≤ (V_in or V_out) ≤ V_CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V_CC). Unused outputs must be left open.

Recommended Operating Conditions

Symbol	Parameter	Min	Max	Unit
V_CC	DC Supply Voltage	2.0	5.5	V
V_in	DC Input Voltage	0	5.5	V
V_out	DC Output Voltage	0	V_CC	V
T_A	Operating Temperature	-55	+125	°C
t_r, t_f	Input Rise and Fall Time	V_CC = 3.3V ±0.3V, C_L = 15pF	0	100	ns/V
t_r, t_f	Input Rise and Fall Time	V_CC = 5.0V ±0.5V, C_L = 50pF	0	20	ns

The O_JA of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and figure below.

Device Junction Temperature Versus Time to 0.1% Bond Failures

Junction Temperature °C	Time, Hours	Time, Years
80	1,032,200	117.8
90	419,300	47.9
100	178,700	20.4
110	79,600	9.4
120	37,000	4.2
130	17,800	2.0
140	8,900	1.0

[Figure 1: Failure Rate vs. Time Junction Temperature]

DC Electrical Characteristics

Symbol	Parameter	Test Conditions	TA = 25°C			TA ≤ 85°C		TA ≤ 125°C		Unit
Symbol	Parameter	Test Conditions	Vcc (V)	Min	Typ	Max	Min	Max	Min	Unit	Max
V_IH	Minimum High-Level Input Voltage	2.0	1.5	-	-	1.5	-	1.5	-	V
		3.0	2.1	-	-	2.1	-	2.1	-	V
		4.5	3.15	-	-	3.15	-	3.15	-	V
V_IL	Maximum Low-Level Input Voltage	2.0	-	0.5	-	0.5	-	0.5	-	V
		3.0	-	0.9	-	0.9	-	0.9	-	V
		4.5	-	1.35	-	1.35	-	1.35	-	V
V_OH	Minimum High-Level Output Voltage	VIN = V_IH or V_IL, I_OH = -50 μA	2.0	1.9	2.0	-	1.9	-	1.9	-	V
		3.0	2.9	3.0	-	2.9	-	2.9	-	V
		4.5	4.4	4.5	-	4.4	-	4.4	-	V
		VIN = V_IH or V_IL, I_OH = -4 mA	3.0	-	2.58	-	2.48	-	2.34	-	V
V_OL	Maximum Low-Level Output Voltage	VIN = V_IH or V_IL, I_OL = 50 μA	2.0	-	0.0	0.1	-	0.1	-	0.1	-	V
		3.0	-	0.0	0.1	-	0.1	-	0.1	-	V
		4.5	-	0.0	0.1	-	0.1	-	0.1	-	V
I_IN	Maximum Input Leakage Current	V_IN = 5.5 V or GND	-	±0.1	-	±1.0	-	±1.0	-	μA
I_CC	Maximum Quiescent Supply Current	V_IN = V_CC or GND	5.5	-	4.0	40.0	-	40.0	-	μA

AC Electrical Characteristics (Input t_r = t_f = 3.0ns)

Symbol	Parameter	Test Conditions	TA = 25°C			TA = -40 to 85°C		TA = -55 to 125°C		Unit
Symbol	Parameter	Test Conditions	Min	Typ	Max	Min Max	Min Max			Unit
t_PLH, t_PHL	Maximum Propagation Delay, A to Y	V_CC = 3.3 ± 0.3V, C_L = 15pF	8.2	11.4	1.0 13.5	1.0 13.5	ns
t_PLH, t_PHL	Maximum Propagation Delay, A to Y	V_CC = 5.0 ± 0.5V, C_L = 50pF	10.0	15.8	1.0 18.0	1.0 18.0	ns
t_PLH, t_PHL	Maximum Propagation Delay, E3 to Y	V_CC = 3.3 ± 0.3V, C_L = 15pF	5.7	8.1	1.0 9.5	1.0 9.5	ns
t_PLH, t_PHL	Maximum Propagation Delay, E3 to Y	V_CC = 5.0 ± 0.5V, C_L = 50pF	7.2	10.1	1.0 11.5	1.0 11.5	ns
t_PLH, t_PHL	Maximum Propagation Delay, E2 or E1 to Y	V_CC = 3.3 ± 0.3V, C_L = 15pF	8.1	12.8	1.0 15.0	1.0 15.0	ns
t_PLH, t_PHL	Maximum Propagation Delay, E2 or E1 to Y	V_CC = 5.0 ± 0.5V, C_L = 50pF	10.6	16.3	1.0 18.5	1.0 18.5	ns
C_IN	Maximum Input Capacitance	-	4	-	10	-	10	-	pF
C_PD	Power Dissipation Capacitance (Note 1)	Typical @ 25°C, V_CC = 5.0V	-	34	-	-	-	-	pF

1. C_PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: I_CC(OPR) = C_PD • V_CC • f_in + I_CC. C_PD is used to determine the no-load dynamic power consumption; P_D = C_PD • V_CC² • f_in + I_CC • V_CC.

Switching Waveforms

[Figure 2: Waveform for input A and output Y]

[Figure 3: Waveform for input E3 and output Y]

[Figure 4: Waveform for input E2 or E1 and output Y]

[Figure 5: Test Circuit diagram]

[Figure 6: Input Equivalent Circuit diagram]

Mechanical Case Outline - SOIC-16

CASE 751B ISSUE M

[Diagram of SOIC-16 package dimensions]

Notes:

Dimensioning and Tolerancing per ASME Y14.5M, 2018.
Dimension in millimeters. Angle in degrees.
Dimensions D and E1 do not include mold protrusion.
Maximum mold protrusion 0.15mm per side.
Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.127mm total in excess of the b dimension at maximum material condition.

Recommended Mounting Footprint

[Diagram of recommended mounting footprint for SOIC-16]

Generic Marking Diagram

[Diagram of generic marking for SOIC-16]

*This information is generic. Please refer to device data sheet for actual part marking. Pb-Free indicator, "G" or microdot "•", may or may not be present. Some products may not follow the Generic Marking.

Mechanical Case Outline - TSSOP-16 WB

CASE 948F ISSUE B

[Diagram of TSSOP-16 WB package dimensions]

Notes:

Dimensioning and Tolerancing per ANSI Y14.5M, 1982.
Controlling Dimension: Millimeter.
Dimension A does not include mold flash. Protrusions or gate burrs. Mold flash or gate burrs shall not exceed 0.15 (0.006) per side.
Dimension B does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 (0.010) per side.
Dimension K does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 (0.003) total in excess of the K dimension at maximum material condition.
Terminal numbers are shown for reference only.
Dimension A and B are to be determined at datum plane -W-.

Recommended Soldering Footprint

[Diagram of recommended soldering footprint for TSSOP-16 WB]

Generic Marking Diagram

[Diagram of generic marking for TSSOP-16 WB]

Additional Information

Technical Publications:

Technical Library: www.onsemi.com/design/resources/technical-documentation

onsemi Website: www.onsemi.com

Online Support:

For additional information, please contact your local Sales Representative at www.onsemi.com/support/sales

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