onsemi Octal D Flip-Flop MC74AC273, MC74ACT273
The MC74AC273/74ACT273 features eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. A common buffered Clock (CP) and Master Reset (MR) input allow simultaneous loading and resetting of all flip-flops. The register is fully edge-triggered, transferring the state of each D input one setup time before the LOW-to-HIGH clock transition to the corresponding Q output. A LOW voltage level on the MR input forces all outputs LOW, independent of Clock or Data inputs. This device is suitable for applications requiring only the true output, with common Clock and Master Reset for all storage elements.
Features
- Ideal buffer for MOS microprocessor or memory
- Eight edge-triggered D flip-flops
- Buffered common clock
- Buffered, asynchronous master reset
- See MC74AC377 for Clock Enable Version
- See MC74AC373 for Transparent Latch Version
- See MC74AC374 for 3-State Version
- Outputs source/sink 24 mA
- 'ACT273 has TTL compatible inputs
- Pb-Free devices
Package Information
The MC74AC273 and MC74ACT273 are available in SOIC-20W and TSSOP-20 packages.
- SOIC-20WB (CASE 751D): 20-lead, surface mount package.
- TSSOP-20 WB (CASE 948E): 20-lead, thin shrink small outline package.
Refer to the mechanical case outline sections for detailed dimensions and marking diagrams.
Logic Diagram
The logic diagram illustrates the internal structure of the octal D flip-flop, showing the D inputs, Q outputs, Clock (CP), and Master Reset (MR) inputs for each of the eight flip-flops.