PCI Express 3.0 Testing Approaches for PHY Layer

PCI Express 3.0 Technology Timeline

This section outlines the timeline for PCI Express 3.0 development, from base specification releases to CEM specification and test specification milestones.

Key development phases include FYI Testing, Silicon Phase, Product Development, PCI-SIG Tool Development, CEM Spec Development, Integration Phase, and Deployment Phase. All information is based on the 1.0 Base Specification.

Tektronix is involved in PCIe EWG, CEM, and SEG Working Groups.

PCI Express 3.0: Trends and Implications

Industry/Technology Trends

• 8 GB/s signaling using the same board material (FR4) and connectors results in increased channel loss.
• Probing access at the silicon transmitter pins is typically not available.
• Receiver equalization can only compensate for channel loss.
• Receiver testing is a requirement and is critical to ensure system interoperability.
• Focus on energy efficiency (Lower mW/Gb/s).

Implications

• Closed data eyes require new techniques for transmitter and receiver equalization.
• Higher data rate signals have less margin, necessitating de-embedding for base specification measurements.
• New Jitter Separation Measurements are required.
• Back channel negotiation is needed to equalize the receiver.
• Link training and power management remain challenging logic layer tasks.

Testing Challenges with PCI Express 3.0

The PCI Express architecture involves multiple layers: Transaction Layer (creating Request/Completion Transactions, Messaging, TLP Flow Control), Data Link Layer (flow control, data integrity, error checking, TLP sequence number, CR calculation), Physical Layer (Logical Sub Block for link initialization, training, packet distribution, power management) and Physical Layer (Electrical Sub Block for transmitter signal quality, reference clock testing, receiver testing, interconnect testing, PLL loop bandwidth).

Diagram Description: A block diagram shows two PCIe Devices (A and B), each with a Device Core, PCIe Core HW/SW Interface, Transaction Layer, Data Link Layer, and Physical Layer (Tx/Rx). Arrows indicate data flow between layers.

Transmitter PHY Layer Analysis for PCIe 3.0

This section focuses on transmitter PHY layer analysis using Tektronix DPO/DSA/MSO70000C Series Oscilloscopes.

PCIe 3.0 Transmitter Compliance Testing

• Compliance testing is based on the CEM Specification, which is under development.
• Features a new compliance 128b/130b data pattern.
• Involves two tests:
• Electrical: Eye Height and Width must pass a pre-set value.
• Preset Test: All pre-sets are tested to be within their limits.
• Measurements are taken after applying the Compliance channel and RX Equalization using the Compliance Base or Load Board.

Image Description: A Tektronix oscilloscope displaying eye diagrams and test results, alongside a circuit board.

Add-In Card Compliance Signal Acquisition and Processing

This process involves acquiring a signal from a compliance board, embedding the add-in card compliance channel, dealing with closed eyes due to the channel, applying base specification CTLE + DFE for long channels, and finally obtaining open eyes for measurements.

System Board Eye Limits

Add-In Card Eye Limits

Note: Measurement Limits Under CEM Review.

Serial Data Link Analysis

• De-embed the effects of a fixture.
• Embed the effects of the channel.
• Equalize the waveform using CTLE, FFE, and/or DFE.

Image Description: A screenshot of the Tektronix Serial Data Link Analysis software interface, showing signal path setup options.

Transmitter Equalization For Compliance

• Transmitter equalization now requires pre-shoot to compensate for channel loss.
• Transmitters must support all defined Pre-Sets.
• Pre-sets are toggled on the CLB or CBB similarly to Gen 2 CLB/CBB.
• All pre-sets are acquired to verify that Pre-shoot and De-emphasis are within the spec limits.

Diagram Description: A circuit board with various test points and connectors labeled for compliance testing. A graph illustrates de-emphasis and pre-shoot measurements.

Testing Beyond Compliance

• What happens if a measurement fails SigTest? Consider if the issue lies with the channel. Measurements can be taken before the channel to evaluate results. Different channel models can be created using Serial Data and Link Analysis.
• How does the optimized RX setting compare to other settings? Easily compare the results of multiple equalization settings.
• Does deeper analysis of the waveform need to be done? PCIe-specific measurements can be taken in Tektronix' DPOJET system to determine data-dependent, uncorrelated, or pulse width jitter. Measurement filters and settings can be adjusted to find the root cause, but SigTest certification requires passing compliance.
• Is the TX compliant? NEW PCIe 3.0 base spec measurements are available to verify TX compliance.

Optimizing Receiver Equalization

This section presents results from optimizing receiver equalization, often using Tektronix' DPOJET software, showing eye diagrams and detailed test results for various equalization settings (e.g., CTLE, DFE).

Image Description: Multiple screenshots of Tektronix DPOJET software displaying eye diagrams and tables of jitter and eye diagram analysis results, demonstrating optimized receiver settings.

CEM Measurements with Optimized RX Settings

This section showcases CEM (Common Electrical Mode) measurements performed with optimized receiver settings, displaying eye diagrams and analysis results, indicating successful equalization.

Image Description: Screenshots of Tektronix DPOJET software showing eye diagrams and detailed test results for CEM measurements with optimized RX settings.

Automated Receiver Optimization

• Manually optimizing over multiple CTLE settings can be time-consuming.
• Optimization is automated with SDLA (Serial Data Link Analysis).
• Optimization is performed on a short record across all settings; the setting with the best eye opening is then computed, and measurements can be taken.
• Results from RX Optimization are presented, showing equalization tap values and corresponding eye metrics.

Image Description: A screenshot of a text file showing PCIe equalizer adaptation results, listing CTLE and DFE tap values and corresponding eye metrics (Eye Area, Eye Height, Eye Width).

Transmitter Characterization

• Base Specification Measurements are defined at the pins of the transmitter.
• Signal access at the pins is often not assessable.
• PCIe Base Specification outlines guidelines for designing the test board with a breakout channel to acquire the signal.
• De-embedding is required to see the signal at the TX pins without the added effects of the channel.
• S-parameters are acquired on the replica channel.

Diagram Description: A block diagram illustrating the transmitter characterization setup, including a low jitter clock source, DUT, breakout channel, and replica channel, with test points (TP1, TP2, TP3).

De-embedding Considerations

• De-embedding amplifies high-frequency noise, thus requiring a bandwidth filter.
• This also impacts the required bandwidth for a real-time (RT) scope.
• Bandwidth is dependent on board material.
• Successful de-embedding starts with good quality board design and S-Parameter data, including matched impedance and low-loss structures, avoiding gain, significant resonances, or large dips.
• Quality of de-embedding is assessed by eye height, jitter, and signal-to-noise ratio.

Diagram Description: Graphs showing the frequency response of 5 GHz and 10 GHz filters, illustrating noise amplification with a 10 GHz filter. The graphs depict insertion loss versus frequency.

Base Specification Transmitter Measurements

• Channel must be de-embedded before measurements can be taken.
• Tektronix offers a PCIe 3.0 De-embed MOI (Method of Implementation) guide.

Diagram Description: A flow diagram showing the process: Signal at TX Pins -> Breakout Channel -> Measured Signal at TP1 -> Apply S-parameters -> Signal with Channel Effects Removed. An oscilloscope and test board are depicted.

NEW PCI Express Base Specification Measurements

Key measurements include:

• Voltage
• Package Loss
• Transmitter Equalization
• Jitter

Image Description: A screenshot of the Tektronix Jitter and Eye Diagram Analysis Tools software, showing various measurement selections and parameters for PCIe 3.0.

Transmitter Equalization Measurements (VTX-BOOST-FS / VTX-BOOST-RS)

• What's new for Gen 3.0: De-Emphasis (Va) and pre-shoot (Vc).
• Transmitters must support 11TX equalization pre-sets.
• The high frequency nature of 8.0 GT/s signaling makes single UI pulse height measurements impractical due to attenuation by the package and breakout channel.
• Amplitude measurements are taken on low-frequency waveforms (64 ones/64 zeros) using the last few UIs of each half period.
• Va and Vc values are obtained by setting the DUT to different preset values where the desired Va or Vc voltage occurs during the Vb interval.

Diagram Description: A waveform showing voltage levels (Va, Vb, Vc, Vd) over time, illustrating de-emphasis and pre-shoot measurements.

Transmitter Voltage Measurements (VTX-EIEOS-FS / VTX-EIEOS-RS)

• Launch Voltage of Electrical Idle Exit Ordered Set: Required to ensure the RX can properly detect an exit from electrical idle.
• Measurements are taken on a pattern of eight ones followed by eight zeros, repeated 128 times, using the middle five UIs to reduce attenuation effects.
• VTX-EIEOS-FS: Full Swing Signaling, measured by Preset 10.
• VTX-EIEOS-RS: Reduced Swing Signaling, measured by Preset 1.

Diagram Description: A waveform illustrating voltage measurements for EIEOS (Electrical Idle Exit Ordered Set), showing upper and lower averages over specific UI intervals for full swing and reduced swing signaling.

Package Loss Measurements (PS21)

• Can be taken at TP1 while capturing silicon package loss and drive characteristics. Due to high-frequency content of the 1010 pattern, measurement must be de-embedded back to the TX pins.
• Measured by comparing 64 zeros and 64 ones PP voltage against a 1010 pattern.
• Measured with de-emphasis and pre-shoot set to 0 at the end of each interval to minimize ISI and low-frequency effects.

Diagram Description: A waveform showing voltage levels (V101, V111) over time, illustrating package loss measurement with de-emphasis and pre-shoot set to zero. The formula for ps21Tx is provided.

Transmitter Jitter Measurements

• Necessary to take jitter measurements with all lanes operating to capture crosstalk effects.
• Measurements are taken at TP1 and de-embedded back to the TX pins.
• It is crucial to separate uncorrelated and data-dependent jitter to ensure recovered jitter is not budgeted as uncorrelated jitter.

Transmitter Jitter Measurements: Data Dependent Jitter (TTX-DDJ)

DDJ Measurement Process

• Measurement is taken on multiple repeats of the compliance pattern using a 1st order CDR function representing a high-pass filter.
• A PDF (Probability Density Function) is created for each edge crossing of the compliance pattern.
• DDJ is calculated as the difference between the mean of each PDF and the recovered clock edge.
• Measurement is defined as the absolute value of DDJ(max) – DDJ(min).

Diagram Description: A waveform showing data from Tx, Data PDF, and Recovered Clock, with DDJ1, DDJ2, DDJ3 markers indicating data-dependent jitter.

Uncorrelated Jitter Example (TTX-UTJ / TTX-UDJDD)

• DDJ is removed from the PDF of each edge.
• Data is converted to Q-Scale.
• Uncorrelated Deterministic Jitter (UDJDD) accounts for Periodic Jitter and Crosstalk; the PDF is converted to Q-Scale.
• Random Jitter is implied by subtracting UDJDD from UTJ.

Diagram Description: A diagram illustrating the derivation of TTX-UTJ and TTX-UDJDD from a PDF curve, showing Q-scale and data clock crossing points.

Uncorrelated Total and Deterministic PWJ (TTX-UPW-TJ / TTX-UPW-DJDD)

• Pulse Width Jitter: Addresses lone bits that are attenuated the most in a lossy channel and could likely cause bit errors.
• DDJ is removed to accurately quantify PWJ.
• Calculate edge-to-edge jitter.
• Construct a Q-scale PDF curve and extrapolate to BER = 10⁻¹² (Q=7.03) to determine Uncorrelated Pulse Width Jitter (containing F/2 or Odd/Even Jitter) and Deterministic Pulse Width Jitter.
• Final measurements are calculated by looking at the left-hand side of the PDF curve.

Diagram Description: A diagram showing a PDF curve with Q-scale, illustrating the extrapolation to BER = 10⁻¹² to determine pulse width jitter.

Recommended Bandwidth for PCI Express 3.0

• Balance instrument bandwidth with application requirements. Noise increases with bandwidth, potentially reducing accuracy and measurement margins.
• PCIe requires analysis of signals with amplitudes as low as 34mV for compliance testing.
• Ensure sufficient bandwidth to capture high-frequency signal content and consider how the channel affects harmonic content and rise time.
• De-embedding requires a bandwidth limit to reduce high-frequency noise amplification.
• Flexibility is needed for different tasks, such as characterization, debug, and compliance.
• Recommended bandwidth: 16 GHz.
• Recommended: 16 GHz offers the best balance for PCI Express 3.0 Measurements.
• Minimum: 12 GHz.

Tektronix Solutions for PCI Express 3.0 Measurements

• Introducing option PCE3 for DSA/DPO/MSO70K Scopes.
• Support for NEW Base Spec measurements.
• Support for CEM Specification.
• Supports all versions of PCI Express.

Image Description: Screenshots of Tektronix oscilloscopes and software interfaces displaying PCIe 3.0 measurement results and analysis tools.

Considerations for Test Equipment Selection

• Test solutions must go beyond compliance to enable root cause analysis.
• Channel Embedding and Receiver equalization require new solutions to characterize optimal settings.
• Solutions need to evolve as test specifications are developed.
• Tektronix provides solutions for PCIe 3.0 testing, including advanced impairments for interoperability verification, debug tools for receiver error analysis, and jitter tolerance algorithms.
• Loopback training sequences and compliance test patterns are available, supporting PCIe 3.0 Transmitter De-emphasis and Pre-shoot.

Image Description: A Tektronix oscilloscope and a computer displaying test software.

Receiver PHY Layer Analysis for PCIe 3.0

This section introduces receiver PHY layer analysis using the Tektronix BSA85C Bit Error Rate Tester.

PCIe 3.0 Implications for Receiver Testing

• System margins are decreasing; testing the transmitter alone does not imply interoperability.
• Receiver testing is mandatory and includes Stressed Voltage Eye and Stressed Jitter Eye tests.
• Differential and Common Mode Interference are new impairment requirements.
• Transmitter Equalization requires De-Emphasis and Pre-Shoot.
• Receiver Equalization is more sophisticated, utilizing behavior equalizers (Continuous Time Linear and Decision Feedback Equalization) to compensate for channel loss.
• Transmitters must support back channel negotiation to auto-negotiate with Receivers to determine optimal equalization settings for testing.

Diagram Description: A binary data stream (0100110101) is shown, followed by a processing block representing a chip, resulting in a corrupted data stream (0000110001) with indicated "Bit Errors".

PCIe Gen3 Receiver Testing

Two types of tests are performed:

1. Stressed Voltage Eye: Achieved by adding interference.
2. Stressed Jitter Eye: Achieved by adding jitter.

Diagram Description: Two diagrams illustrating the concepts of Stressed Voltage Eye (with interference arrows) and Stressed Jitter Eye (with jitter arrows).

Receiver Test Made Easy with the BERTScope

The BERTScope simplifies receiver testing. A Stressed Pattern Generator (DPP) provides pre-emphasis to emulate compliant transmitters. The signal is sent to the Device Under Test (DUT) in loopback. An Error Detector recovers the clock from the retransmitted data and compares it to the expected pattern for Bit Error Ratio (BER) measurement.

Diagram Description: A block diagram showing the BERTScope setup: Stressed Pattern Generator (DPP) connected to DUT via loopback, and an Error Detector receiving data from DUT for BER measurement.

Stressed Voltage Eye: Stressed Pattern Generation

The DPP125A provides pre-emphasis and coefficient space support. It features built-in compliant Random and Sinusoidal Jitter models supporting 2.5, 5, 8, and 16 GT/s. Sinusoidal Interference for DM/CM interference is available externally for combining after pre-emphasis.

Diagram Description: A block diagram of the Stressed Pattern Generation setup using DPP125A, BERTScope, and a signal generator, showing the path of pre-emphasis, jitter, and interference.

Stressed Voltage Eye: Channel

The channel setup involves three different stressed eyes, created using three channel lengths with varying insertion loss (IL) characteristics at 4 GHz. The BERTScope ISI Board is used for calibration.

Diagram Description: A diagram illustrating the channel setup with different channel lengths and their corresponding insertion loss curves. A circuit board (BERTScope ISI Board) is shown.

Stressed Voltage Test

The Stressed Voltage Eye is applied to the DUT, which is placed in loopback for BER testing. The BERTScope performs the BER test, comparing the received signal against a 10⁻¹² threshold.

Diagram Description: A block diagram showing the Stressed Voltage Test setup, including the DUT in loopback, BERTScope, and a 100 MHz Refclk.

Stressed Jitter Pattern Generation

Similar requirements to the Stressed Voltage Eye apply. The setup includes a Stressed Pattern Generator (DPP125A), BERTScope, and a channel, with pre-emphasis, RJ, and SJ adjustments.

Diagram Description: A block diagram of the Stressed Jitter Pattern Generation setup, similar to the voltage test but emphasizing jitter components.

Stressed Jitter Test: Jitter Tolerance

The Stressed Jitter Eye is applied to the DUT, which is placed in loopback for Jitter Tolerance testing. The BERTScope performs the Jitter Tolerance Test, sweeping SJ frequency/amplitude as per a mask.

Diagram Description: A block diagram of the Stressed Jitter Test setup. A graph shows the Jitter Tolerance Template and SJ Sweep Range, indicating limits for Rj and Sj.

Image Description: A screenshot of the BERTScope software performing a Jitter Tolerance Test.

Requirements for PCI Express 3.0 Receiver Compliance Testing

• Receiver compliance is tested with a worst-case eye to ensure BER ≤ 10⁻¹² with short and long channels.
• Channel definitions are part of the CEM specification.
• Before testing, the eye is calibrated with optimal TX equalization settings for each channel using the 128b/130b Compliance Pattern.
• De-emphasis/Pre-shoot, SJ, RJ, 100MHz DJ, and Differential Noise are applied.
• The receiver's ability to change equalization settings is tested by applying a sub-optimal TX equalization setting.
• Some receivers may have RX equalization capability that is more capable than the reference equalizer, potentially not requiring TX equalization changes; in such cases, the sub-optimal TX setting is used for the test.
• The device is put into loopback following the loopback procedure in the base specification.

Jitter Tolerance Test

• Once the link is in loopback and optimal equalization settings are determined, the Jitter Tolerance Test begins.
• The BERTScope counts any errors.
• What if errors occur? Advanced debug tools are used to determine the cause of RX errors.

Diagram Description: A four-step process illustrating the Jitter Tolerance Test: 1. Configure, 2. Stressed Pattern Generator, 3. Loopback to DUT, 4. Detector Results (Bits, Errors, BER).

Advanced Debug Tools to Determine Cause of RX Errors

• Pattern Sensitivity: Quickly determine if the source of receiver errors is pattern-dependent.
• Error Statistics: A tabular display of bit and burst error counts and rates.
• Strip Chart: Determine timing relationships of errors.
• Burst Length: Determine the occurrence of errors of different lengths.
• Error Free Interval: Number of occurrences of different error-free intervals.

Image Description: Three scenarios are presented: 1. Basic BER Statistics are OK. 2. What if Jitter Tolerance Fails? 3. Pattern Sensitivity enables root cause analysis of pattern-dependent errors. Screenshots of BERTScope results (DETECTOR RESULTS, Jitter Tolerance Search) are shown.

Considerations for Receiver Test Equipment Selection

• Test solutions need to go beyond compliance to enable root cause analysis.
• Transmitter Equalization requires generators that provide spec-compliant De-emphasis and Pre-shoot.
• Solutions need to evolve as test specifications are under development.
• Tektronix offers solutions for PCIe 3.0 testing, including advanced impairments for interoperability verification, debug tools for receiver error analysis, and jitter tolerance algorithms.
• Loopback training sequence and compliance test patterns are available, supporting PCIe 3.0 Transmitter De-emphasis and Pre-shoot.

Image Description: A Tektronix oscilloscope and a computer displaying test software.

Important Resources

• Complete Solutions Available on www.tek.com
• Solutions available for PCIe 1.0, 2.0, 3.0 Transmitter, Receiver, PLL Loop bandwidth, and Protocol Testing.
• Support & Resource Links
• Recommended Equipment Configurations: www.tek.com/serial_data
• Access to new PCE3 Software Downloads & Free Trial: www.tek.com/software (search for PCE3)
• PCI Express Base Specification (members only): http://www.pcisig.com/specifications/pciexpress/