Tektronix PCI Express

Overview

Improve the accuracy and precision of cutting-edge PCI Express 6.0 Receiver (Rx) validation with Tektronix automation software. Remove the complexity of Rx testing with a step-by-step user guided interface designed by industry leaders actively engaged in the standards bodies. Industry engagement ensures this solution evolves in step with the technology. Achieving the correct balance of simplicity and user control has been the focus of the design team to ensure your device can complete link training testing with calibrated stress and be efficiently tested with optimized PHY settings.

Applications

• PCI Express 64 GT/s, 32 GT/s, 16 GT/s, and 8 GT/s
• Gen6/Gen5/Gen4/Gen3 Base specification (silicon validation) and Gen6/Gen5/Gen4/Gen3 CEM specification (system verification and compliance)
• Root Complex and Non-Root Complex silicon
• Systems (motherboards and servers), Add-in Cards, Switches, Bridges, and Extension Devices (retimers and redrivers)

Features and Benefits

General

• Receiver automation software for Tektronix DPO70000SX Series Real Time Oscilloscopes and Anritsu MP1900A BERT
• Wizard based user interface for each step of calibration and test
• Pop-up user tips to simplify decision making
• Latest industry tool support (SigTest and Seasim)
• Calibration and test reports

PCI Express Generations

PCI Express Gen6 (64 GT/s)

• Stressed Eye Calibration (64 GT/s)
• Base and CEM
• TP3 - AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, and Random Jitter
• TP2 – DMI, CMI, Preset and CTLE Selection, Stressed Eye
• Automated Oscilloscope Noise Compensation for SJ and RJ calibration
• Insertion Loss computation powered by Seasim Statistical Simulation Tool
• Rx Link Equalization Test (64 GT/s)
• Tx Link Equalization Test (64 GT/s)
• Jitter Tolerance Test (64 GT/s)
• Advanced debug mode for troubleshooting

PCI Express Gen5 (32 GT/s)

• Stressed Eye Calibration (32 GT/s)
• Base and CEM
• TP3 - AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, and Random Jitter
• TP2 – DMI, CMI, Preset and CTLE Selection, Stressed Eye
• Automated loopback through Configuration and Recovery
• Insertion Loss computation powered by Seasim Statistical Simulation Tool
• Rx Link Equalization Test (32 GT/s)
• Tx Link Equalization Test (32 GT/s)
• Jitter Tolerance Test (32 GT/s)
• Advanced debug mode for troubleshooting

PCI Express Gen4 (16 GT/s)

• Stressed Eye Calibration (16 GT/s)
• Base and CEM
• TP1 – AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, and Random Jitter
• TP2 – DMI, CMI, Preset and CTLE Selection, Stressed Eye
• Automated loopback through Configuration and Recovery
• Insertion Loss computation powered by Seasim Statistical Simulation Tool
• Rx Link Equalization Test (16 GT/s)
• Tx Link Equalization Test (16 GT/s)
• Jitter Tolerance Test (16 GT/s)
• Advanced debug mode for troubleshooting

PCI Express Gen3 (8 GT/s)

• Stressed Eye Calibration (8 GT/s)
• CEM
• TP3 - AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, and Random Jitter
• TP2 - DMI, and Stressed Eye
• Rx Link Equalization Test (8 GT/s)
• Tx Link Equalization Test (8 GT/s)
• Jitter Tolerance Test (8 GT/s)
• Advanced debug mode for troubleshooting

PCI Express PLL Bandwidth and Peaking

PCI Express PLL Bandwidth and Peaking automation software for Tektronix DPO70000SX Series Real-Time Oscilloscopes and Anritsu MP1900A BERT.

• Support for Gen 3/4/5 Tx PLL testing
• Support for Anritsu SI PPG (NRZ) and PAM4 PPG
• Similar software look and feel as the Receiver test suite
• Supports testing with compliance (P0 to P10) and jitter measurement (toggle) patterns
• Software CTLE improves accuracy for high loss channel cases

Stressed Eye Calibration

Calibration of the stressed eye signal, generated by the BERT's PPG, is important to ensure the receiver is tested in alignment with the PCI-SIG specifications with the proper amount of impairments. New challenges at 64 GT/s demand the fully automated approach taken by the Tektronix PCI Express Receiver Test Suite to avoid alternative tedious and error-prone approaches. Let the domain expertise and experience of the Tektronix engineers guide you through the steps of calibration starting with accurate TP3 measurements and ending with a TP2 eye diagram easily obtained within the tolerances required. Engineers will spend less time calibrating and more time collecting meaningful data on receiver performance and margin.

TP3 Calibration

PCI Express Gen6 (64 GT/s) and Gen5 (32 GT/s)

The TP3 (point after cable from BERT PPG to oscilloscope) calibration is mandatory for all devices to ensure tolerances are met at the defined reference plane. The Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to ensure the pre-channel signal matches the specification requirements to ensure future calibration steps are completed with ease.

1. AC-DC balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
2. Amplitude – The differential voltage swing is required to be within 720 – 800 mV.
3. Tx Equalization Presets – Calibration of pre-shoot 1, pre-shoot 2 (Gen6 only), and de-emphasis is required to ensure true preset levels are used for testing receivers.
4. IL measurement – Channel insertion loss is calculated using Seasim between TP1 and TP3 (loss before the TP3 reference is computed here for later removal).
5. Random Jitter (RJ) – RJ is calibrated to be 0.25 ps [Gen6], 0.5 ps [Gen5] (RMS value) nominally.
6. Sinusoidal Jitter (SJ) – SJ is calibrated over the required range of 1-3 ps [Gen6]/1-5 ps [Gen5] (p-p) at 100 MHz frequency.

[Description of RJ and SJ calibration for Gen6 graph]

7. SJ@210 MHz – This calibration is required for JTOL measurements with some calibrations.

[Description of SJ@210 MHz calibration for Gen6 graph]

8. Multi-tone SJ – For JTOL measurements where up to maximum 14 frequencies are used, calibration for frequencies other than 100 MHz is required to be performed.

TP2 Calibration

PCI Express Gen6 (64 GT/s), Gen5 (32 GT/s), Gen4 (16 GT/s), and Gen3 (8 GT/s)

The TP2 (end of channel) calibration is a complex process requiring a deep understanding of the BERT, Real Time Oscilloscope, post-processing tools, and the PCIe specifications. The Tektronix PCI Express Receiver Test Suite will remove the complexity and ensure the desired results are achieved through user-friendly automation. Time to complete TP2 is critical, so efficient techniques have been implemented to ensure an accurate stressed eye is achieved within a reasonable time scale. From calibration of DMI (Differential Mode Interference modeling cross-talk) to the fine granularity adjustments to SJ and DMI necessary to find the stressed eye solutions space, our automation software will guide you through this otherwise daunting task.

1. DMI – The differential mode interference is required to be calibrated within 5-25 mV (p-p) [Gen6] / 5-30 mV (p-p) [Gen5] / 10-25 mV (p-p) [Gen4] / 10-100 mV(p-p) [Gen3] by capturing the 2.1 GHz sinusoidal output for a duration of 40 ns.
2. CMI – The common-mode interference is required to be calibrated for a nominal voltage of 75 mV (p-p) [Gen6] / 150 mV (p-p) [Gen5 and Gen4] by capturing the 120 MHz sinusoidal output for a duration of 62.5 us.
3. Channel insertion loss for DMI/CMI and eye diagram measurements computed with Seasim (TP1 to TP2/TP2P for 16 GT/s and TP3 to TP2/ TP2P for 32 GT/s and 64 GT/s).

[Description of AIC CMI calibration result graph]

[Description of AIC DMI calibration result graph]

4. Channel selection based on optimal Tx EQ Preset and Rx CTLE – Base Specification compliant for Eye Area criteria.

5. Stressed-Eye calibration – Fine-tuning of the eye using amplitude, SJ (RJ in case of Gen3), and DMI is utilized to place the stressed eye within allowed tolerances. Automated TP2 calibration plots and stressed eye calibration details along with other important parameters like pattern type, oscilloscope and BERT settings, and regression line slopes and intercept for reference.

[Description of Root complex TP2 calibration sample report]

TP1 Calibration

PCI Express Gen4 (16 GT/s) and Gen3 (8 GT/s)

The TP1 (point after cable from BERT PPG to oscilloscope) calibration is mandatory for all devices to ensure tolerances are met at the defined reference plane. The Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to pre-channel signal is true to the specification requirements to ensure future calibration steps complete with ease.

1. AC-DC balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
2. Amplitude – The differential voltage swing is required to be within 720 – 800 mV.
3. Tx Equalization Presets – Calibration of pre-shoot and de-emphasis is required to ensure true preset levels are used for testing receivers.
4. Random Jitter (RJ) – RJ is calibrated to be 1 ps (RMS) for Gen4 and 1.5 ps (RMS) for Gen3 nominally.

[Description of Stressed eye calibration result table]

6. Stressed eye calibration supported using Sigtest (Gen3/Gen4/Gen5) and Seasim (Gen5/Gen6).

7. Eye height

• 6 ± 0.5 mV @ BER E-6 [Gen6]
• 15 ± 1.5 mV @ BER E-12 [Gen5 and Gen4]
• 47.5 ± 2.5 mV @ BER E-12 [Gen3 System]
• 43.5 ± 2.5 mV @ BER E-12 [Gen3 AIC]

8. Eye Width

• 3.125 ± 0.3 ps @ BER E-6 [Gen6]
• 9.375 ± 0.5 ps @ BER E-12 [Gen5]
• 18.75 ± 0.5 ps @ BER E-12 [Gen4]
• 44 ± 1 ps @ BER E-12 [Gen3 System]

[Description of RJ and SJ calibration for Gen 4 graph]

5. Sinusoidal Jitter (SJ) – SJ is calibrated over the required range of 5-10 ps (p-p) including the nominal SJ specification of 0.1 UI (or 6.25 ps for Gen4 and 12.5 ps for Gen3) at 100 MHz frequency.

6. SJ@210 MHz – This calibration is required for JTOL measurements with some calibrations (only for Gen4).

[Description of SJ@210 MHz calibration for Gen4 graph]

Link Training

Prior to receiver testing, the Device-Under-Test (DUT) must be placed into loopback, where the signal digitized at the Rx latch is re-transmitted by the corresponding Tx giving visibility into a possible bit or burst errors. Entering the loopback test mode requires a complex dance through the Link Training Status State Machine (LTSSM) between the BERT and DUT. The Tektronix PCI Express Receiver Test Suite automates this sequence allowing loopback through configuration (short path) and loopback through recovery (full training of the link Tx and Rx) for different levels of receiver testing. Relevant parameters are exposed to allow user control over this process without unnecessary complexity.

[Description of Flexible link training and loopback control screenshot]

[Description of Link training configuration screenshot]

Receiver and Transmitter Link Equalization Testing

PCI Express compliance at 64 GT/s, 32 GT/s, 16 GT/s, and 8 GT/s requires performing a Receiver Link Equalization test (checking analog Rx performance with a stressed signal after full link training) and a Transmitter Link Equalization test (ensuring key digital timing limits are achieved when an Rx makes Tx change requests to its link partner).

The Tektronix PCI Express Receiver Test Suite controls the BERT and RT Oscilloscope during these required tests to provide efficient test results with minimal overhead and control only where needed.

The advanced debug mode provides additional troubleshooting capability for LEQ tests, allowing customised stressors, Tx presets, custom patterns, auto-search CTLE, and CDR tuning.

[Description of Rx LEQ test configuration screenshot]

[Description of Tx LEQ test configuration screenshot]

[Description of Rx LEQ - Run Test screenshot]

[Description of Tx LEQ - Run Test screenshot]

[Description of Tx LEQ AIC response time test results table]

[Description of AIC Rx LEQ test results table]

Jitter Tolerance (JTOL) Test

Jitter Tolerance (JTOL) testing requires sweeping numerous calibrated SJ tones from low to high amplitude to see how the receiver-under-test CDR tracks the stress (typically in the presence of other noise & jitter sources). Custom JTOL pass/fail masks can be configured while testing with different search algorithms (upward linear, logarithmic, etc.). The Tektronix PCI Express Receiver Test Suite allows engineers minimal setup with quick and descriptive test reports.

[Description of JTOL test configuration settings screenshot]

Both the custom mask and the specification mask are provided in the JTOL test to have a better understanding of the DUT performance, especially at the design stage. The Receiver solution performs an automatic back channel equalization and sampling point optimization to ensuring the best conditions for the DUT transmitted data traffic to be accurately comprehended at the BERT receiver ensuring the correct determination of BER performance.

[Description of JTOL test result with specification graph]

[Description of Error detector and stress settings for JTOL screenshot]

[Description of Different margin search algorithm settings for JTOL test screenshot]

SJ Amplitude Calibration

[Description of SJ amplitude calibration screenshot]

[Description of Result summary for SJ Amplitude calibration table]

PLL Bandwidth and Peaking

This test verifies that the Add-In Card Tx PLL has the correct bandwidth and peaking. Providing a 100 MHz reference clock to the DUT with a calibrated amount of SJ allows us to measure how much SJ passes through the DUT's Tx PLL for a certain SJ tone. Performing this process across multiple tones allows the construction of the PLL frequency response to measure both bandwidth and peaking.

SJ Amplitude Calibration for Gen 5/4/3

• Calibration of SJ amplitude to modulate the 100 MHz Refclk used by DUT's Tx PLL
• Adjustable SJ amplitude
• User-controlled SJ frequency selection to ensure adequate resolution at peaking & 3dB point
• Increased averaging can be used to minimize variation (5 recommended)
• Software CTLE ensures support for higher loss channels and various DUT Tx patterns

[Description of PLL bandwidth test graph]

[Description of Test results graph]

PLL bandwidth and peaking measurements:

• Bandwidth and peaking reported for selected data rates
• DUT Tx can transmit compliance patterns or jitter measurement (toggle) patterns
• Consistent DSP algorithm used for SJ calibration and DUT testing
• Test report with PLL bandwidth, peaking, frequency response plot, and individual measurements

Ordering Information

PCIe Gen6 BASE and CEM software options

PCIe Gen5 BASE and CEM software options

PCIe Gen4 BASE and CEM software options

PCIe PLL BW software options

Overall Setup list: PCIe Gen 6 CEM

Overall Setup list: PCIe Gen 6 Base

PCIe Gen4 CEM

PCIe Gen4 Base

PCIe Gen4 Base

PCIe Gen3 Base/CEM

PCI PLL Bandwidth (Gen 6/5/4/3)

Host system software requirements: Microsoft Windows 10