Tektronix PCI Express Receiver Test Suite Datasheet

Tektronix PCI Express

Improve accuracy and precision of PCI Express Gen5 Receiver Stressed Eye Calibration, Receiver & Transmitter Link Equalization testing, and Receiver Jitter Tolerance with Tektronix automation software. Remove the complexity of receiver testing with a step-by-step user interface designed by industry leaders engaged in the standards bodies to drive the latest specifications to maturity. Industry engagement ensures our software will evolve in-step with the technology. Achieving the correct balance of simplicity and user control has been at the forefront of the design team to ensure your device can complete link training with the correct calibrated stress and be efficiently tested with optimized PHY settings.

Applications

• PCI Express Gen5 (32 GT/s) & Gen4 (16 GT/s)
• Gen5 Base Specification (silicon validation) & Gen5 and Gen5 CEM Specification (system verification & compliance)
• Root Complex & Non-Root Complex silicon
• Systems (motherboards & servers), Add-in Cards, Switches & Bridges, Extension Devices (retimers & redrivers)

Features and Benefits

PCI Express Gen5 (32 GT/s)

• Receiver automation software for Tektronix DPO70000SX Series Real Time Scopes & Anritsu MP1900A BERT
• Wizard based user interface for each step of calibration and test
• Pop-up user tips to simplify decision making
• Stressed Eye Calibration (32 GT/s) &
• Base & CEM
• TP3 – AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, & Random Jitter

PCI Express Gen4 (16 GT/s)

• Receiver automation software for Tektronix DPO70000SX Series Real Time Scopes & Anritsu MP1900A BERT
• Wizard based user interface for each step of calibration and test
• Pop-up user tips to simplify decision making
• Stressed Eye Calibration (32 GT/s)
• CEM
• TP1 – AC/DC Balance, Amplitude, Tx Equalization, Sinusoidal Jitter tones, & Random Jitter
• TP2 – DMI, CMI, Preset & CTLE Selection, Stressed Eye, Automated loopback through Configuration & Recovery
• Insertions Loss computation powered by Seasim Statistical Simulation Tool
• Rx Link Equalization (16 GT/s)
• Tx Link Equalization (16 GT/s)
• Jitter Tolerance (16 GT/s)
• Latest industry tool support (SigTest & Seasim)
• Calibration and test reports

Stressed Eye Calibration

Calibration of the stressed eye signal, generated by the BERT's PPG, is important to ensure the receiver is tested in alignment with the PCI-SIG specifications with the proper amount of impairments. New challenges at 32 GT/s demand the fully automated approach taken by the Tektronix PCI Express Receiver Test Suite to avoid alternative tedious and error-prone approaches. Let the domain expertise and experience of the Tektronix engineers guide you through the steps of calibration starting with accurate TP3 measurements and ending with an end of channel eye diagram easily obtained within the tolerances required. Engineers will spend less time calibrating and more time collecting meaningful data on receiver performance and margin.

TP3 calibration

PCI Express Gen5 (32 GT/s)

The TP3 (cable from BERT PPG to scope) is mandatory for all devices to ensure tolerances are met at the defined reference plane. Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to pre-channel signal is true to the specification requirements to ensure future calibration steps complete with ease.

1. AC-DC Balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
2. Amplitude - The differential voltage swing is required to be within 720 - 800 mV.
3. Tx Equalization Presets – Calibration of pre-shoot and de-emphasis is required to ensure true preset level are used for testing receivers.
4. IL Measurement – Channel insertion loss is calculated using Seasim between TP3 and TP1 (loss before the TP3 reference is computed here for later removal).
5. RJ – Random Jitter (RJ) is calibrated to be 0.5 ps (RMS value) nominally.
6. SJ - Sinusoidal Jitter (SJ) is calibrated over the required range of 1-5 ps (p-p) including the nominal SJ specification of 0.1 UI (or 3.125 ps) at 100 MHz frequency.
7. SJ@210 MHz – This calibration is required for JTOL measurements with some calibrations.
8. Multi-tone SJ – For JTOL measurements where up to maximum 14 frequencies are used, calibration for frequencies other than 100 MHz are required to be performed.

Automatic characterization and precise calibration of presets, RJ, and SJ along with the important parameters used for calibration like pattern type, scope, BERT settings, regression line slopes, and intercept for reference.

TP1 calibration

PCI Express Gen4 (16 GT/s)

The TP1 (cable from BERT PPG to scope) is mandatory for all devices to ensure tolerances are met at the defined reference plane. Tektronix PCI Express Receiver Test Suite wizard will guide the user through all the necessary steps to pre-channel signal is true to the specification requirements to ensure future calibration steps complete with ease.

1. AC-DC Balance – Small amounts of Tx EQ de-emphasis are enabled to balance low and high-frequency sections of the pattern at a common reference plane.
2. Amplitude - The differential voltage swing is required to be within 720-800 mV.
3. Tx Equalization Presets – Calibration of pre-shoot and de-emphasis is required to ensure true preset level are used for testing receivers.
4. IL Measurement – Channel insertion loss is calculated using Seasim between TP3 and TP1 (loss before the TP3 reference is computed here for later removal).
5. RJ - Random Jitter (RJ) is calibrated to be 1 ps (RMS value) nominally.
6. SJ - Sinusoidal Jitter (SJ) is calibrated over the required range of 5-10 ps (p-p) including the nominal SJ specification of 0.1 UI (or 6.25 ps) at 100 MHz frequency.
7. SJ@210 MHz – This calibration is required for JTOL measurements with some calibrations.
8. Multi-tone SJ – For JTOL measurements where up to maximum 14 frequencies are used, calibration for frequencies other than 100 MHz are required to be performed.

Automatic characterization and precise calibration of presets, RJ, and SJ along with the important parameters used for calibration like pattern type, scope, BERT settings, regression line slopes, and intercept for reference.

TP2 calibration

PCI Express Gen5 (32 GT/s) & Gen4 (16GT/s)

The TP2 (end of the channel) calibration is a complex process requiring a deep understanding of the BERT, Real Time Oscilloscope, post-processing tools, and the PCle specifications. The Tektronix PCI Express Receiver Test Suite will remove the complexity and ensure the desired results are achieved through user-friendly automation. Time to TP2 completion is critical, so efficient techniques have been implemented to ensure an accurate stressed eye is achieved within a reasonable time scale. From calibration of DMI (differential mode interference modeling cross-talk) to the fine granularity adjustments to SJ and DMI necessary to find the stressed eye solutions space, our automation software will guide you through this otherwise daunting task.

Automated TP2 calibration plots and stressed eye calibration details along with other important parameters like pattern type, scope and BERT settings and regression line slopes and intercept for reference.

• Eye height 15 +/- 1.5 mV [Gen5 & Gen4] and
• Eye width 9.375 +/- 0.5ps [Gen5]
• Eye width 18.75 +/- 0.55ps [Gen4]

Link training

Prior to receiver testing, the device-under-test (DUT) must be placed into loopback, where the data digitized at the Rx latch is re-transmitted by the corresponding Tx giving visibility into a possible bit or burst errors. Entering the loopback test mode requires a complex dance through the Link Training Status State Machine (LTSSM) between the BERT and DUT. The Tektronix PCI Express Receiver Test Suite automates this sequence allowing loopback through configuration (short path) and loopback through recovery (full training of the link Tx & Rx) for different levels of receiver testing. Relevant parameters are exposed to allow user control over this process without unnecessary complexity.

Receiver and transmitter link equalization testing

PCI Express compliance at 32 GT/s & 16 GT/s requires performing a Receiver Link Equalization test (checking analog Rx performance with a stressed signal after full link training) and a Transmitter Link Equalization test (ensuring key digital timing limits are achieved when an Rx makes Tx change requests to its link partner).

The Tektronix PCI Express Receiver Test Suite controls the BERT and RT Oscilloscope during these required tests to provide efficient test results with minimal overhead and control only where needed.

Remote control protocol

The test software can be operated remotely through ASCII commands sent through TCP/IP, giving engineers further flexibility in designing "Beyond Compliance" tests.

Jitter Tolerance (JTOL) test

Jitter tolerance (JTOL) testing requires sweeping numerous calibrated SJ tones from low to high amplitude to see how the receiver-under-test CDR tracks the stress (typically in the presence of other noise & jitter sources). Custom JTOL pass/fail masks can be configured while testing with different search algorithms (upward linear, logarithmic, etc.). The Tektronix PCI Express Receiver Test Suite allows engineers minimal setup with quick and descriptive test reports.

Both the custom mask and the specification mask are provided in the JTOL test to have a better understanding of the DUT performance, especially at the design stage. The Receiver solution performs an automatic back channel equalization and sampling point optimization ensures to ensure the best conditions for the DUT transmitted data traffic to be accurately comprehended at the BERT receiver to ensure the correct determination of BER performance.

Ordering information

PCIe Gen5 Base and CEM Software Options

Table 1: Models - SX >= 50 GHz DPS + DPO

PCIe Gen5 Pre-compliance Fixture Options

PCIe Gen4 CEM Software Options

Table 2: Models >= 24 GHz and Above (DPO72504DX, DPO73304DX, DPO70KDX)

Overall Setup list:

Table 3: PCIe Gen5 Base Rx

Table 4: PCIe Gen5 CEM LEQ

Table continued...

¹ If ATI channels will be used for refclk measurements they will need Option Key 4 (50 XL)

² Cables required for connection between BERT modules shall be included for the 3rd party vendor

³ Gen5 BaseTest Fixtures are not backwards compatible for Gen3 & Gen4 Base Rx

⁴ It is assumed MMPX cables and MMPX to SMA adaptor cables for test fixture connections are included with the fixture kit

⁵ Configuration for BERT provided by 3rd party vendor

Table 4: PCIe Gen4 CEM

Table continued...

⁶ Another matched pair of cables (e.g. 174-6663-xx) will be required if the Active redriver is used for Rx or Tx LEQ

⁷ Gen5 CEM Test Fixtures are not backwards compatible for Gen3 & Gen4 CEM Rx